1 /*---------------------------------------------------------------------------- 2 * Copyright (c) Huawei Technologies Co., Ltd. 2022-2023. All rights reserved. 3 * Description: LiteOS Perf Riscv Pmu Module HeadFile 4 * Author: Huawei LiteOS Team 5 * Create: 2022-12-20 6 * Redistribution and use in source and binary forms, with or without modification, 7 * are permitted provided that the following conditions are met: 8 * 1. Redistributions of source code must retain the above copyright notice, this list of 9 * conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, this list 11 * of conditions and the following disclaimer in the documentation and/or other materials 12 * provided with the distribution. 13 * 3. Neither the name of the copyright holder nor the names of its contributors may be used 14 * to endorse or promote products derived from this software without specific prior written 15 * permission. 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 *---------------------------------------------------------------------------*/ 28 29 #ifndef _ARCH_PMU_H 30 #define _ARCH_PMU_H 31 32 #include "los_typedef.h" 33 #ifdef __cplusplus 34 extern "C" { 35 #endif /* __cplusplus */ 36 37 /* 38 * According to the spec, an implementation can support counter up to 39 * mhpmcounter31, linx170 processors has at 4 general PMCs, we give 40 * the definition to MHPMCOUNTER6 here 41 */ 42 #define RISCV_PMU_CYCLE 0 43 #define RISCV_PMU_INSTRET 2 44 #define RISCV_PMU_MHPMCOUNTER3 3 45 #define RISCV_PMU_MHPMCOUNTER4 4 46 #define RISCV_PMU_MHPMCOUNTER5 5 47 #define RISCV_PMU_MHPMCOUNTER6 6 48 #define RV32_IDX_MAX_COUNTER 7 49 50 /* Performance counter numbers */ 51 #define RV32_IDX_CYCLE_COUNTER 0 52 #define RV32_IDX_COUNTER0 3 53 54 #define REG_MCOUNTINHIBIT 0x320 55 56 enum PmuEventType { 57 RV32_PERF_HW_CYCLE = 0x000, /* cycle */ 58 RV32_PERF_HW_INSTRET = 0x001, /* instructions */ 59 RV32_PERF_HW_FLUSH_NO = 0x002, /* CPU flushes initiated by Commit */ 60 RV32_PERF_HW_TOTAL_BRANCH = 0x040, /* branch instructions */ 61 RV32_PERF_HW_MIS_BRANCH = 0x041, /* mis-predicted branches */ 62 RV32_PERF_HW_UNCOND_DIRECT_BRANCH = 0x042, 63 RV32_PERF_HW_UNCOND_INDIRECT_BRANCH = 0x043, 64 RV32_PERF_HW_MMEM_FETCH = 0x080, 65 RV32_PERF_HW_MMEM_LOAD = 0x081, 66 RV32_PERF_HW_MMEM_STORE = 0x082, 67 RV32_PERF_HW_ITCM_RD = 0x083, /* ITCM read */ 68 RV32_PERF_HW_DTCM_RD = 0x084, /* DTCM write */ 69 RV32_PERF_HW_ITCM_WR = 0x085, 70 RV32_PERF_HW_DTCM_WR = 0x086, 71 RV32_PERF_HW_PMEM_RD = 0x087, 72 RV32_PERF_HW_PMEM_WR = 0x088, 73 RV32_PERF_HW_UNALIGN_LS_ACC = 0x089, 74 RV32_PERF_HW_ITCM_CONFLICTS = 0x08A, 75 RV32_PERF_HW_DTCM_CONFLICTS = 0x08B, 76 RV32_PERF_HW_DTCM_NARROW_WRITE = 0x08C, 77 RV32_PERF_HW_DTCM_RETRY = 0x08D, 78 RV32_PERF_HW_DTCM_ERR = 0x08E, 79 RV32_PERF_HW_DTCM_ECC_2BIT_ERR = 0x08F, 80 RV32_PERF_HW_ITCM_NARROW_WRITE = 0x090, 81 RV32_PERF_HW_ITCM_RETRY = 0x091, 82 RV32_PERF_HW_ITCM_ERR = 0x092, 83 RV32_PERF_HW_ITCM_ECC_2BIT_ERR = 0x093, 84 RV32_PERF_HW_IC_ACC = 0x0C0, /* icache */ 85 RV32_PERF_HW_IC_MISS = 0x0C1, /* icache-misses */ 86 RV32_PERF_HW_DC_ACC = 0x0C2, /* dcache */ 87 RV32_PERF_HW_DC_MISS = 0x0C3, /* dcache-misses */ 88 RV32_PERF_HW_IC_UNACC = 0x0C4, 89 RV32_PERF_HW_DC_UNACC = 0x0C5, 90 RV32_PERF_HW_IC_AUTO_PREF = 0x0C6, 91 RV32_PERF_HW_DC_AUTO_PREF = 0x0C7, 92 RV32_PERF_HW_IC_TAG_ARRAY_ECC_2BIT_ERR = 0x0C8, 93 RV32_PERF_HW_IC_DATA_ARRAY_ECC_2BIT_ERR = 0x0C9, 94 RV32_PERF_HW_IC_TAG_ARRAY_ECC_1BIT_ERR = 0x0CA, 95 RV32_PERF_HW_IC_DATA_ARRAY_ECC_1BIT_ERR = 0x0CB, 96 RV32_PERF_HW_DC_TAG_ARRAY_ECC_2BIT_ERR = 0x0CC, 97 RV32_PERF_HW_DC_DATA_ARRAY_ECC_2BIT_ERR = 0x0CD, 98 RV32_PERF_HW_DC_TAG_ARRAY_ECC_1BIT_ERR = 0x0CE, 99 RV32_PERF_HW_DC_DATA_ARRAY_ECC_1BIT_ERR = 0x0CF, 100 RV32_PERF_HW_DC_NARROW_WRITE = 0x0D0, 101 RV32_PERF_HW_FETCH_BUBBLE = 0x180, /* fetch bubbles */ 102 RV32_PERF_HW_ISSUE_BUBBLE = 0x181, /* issue bubbles */ 103 RV32_PERF_HW_MAX 104 }; 105 106 VOID OsPerfCheckEventCount(VOID); 107 108 #ifdef __cplusplus 109 } 110 #endif /* __cplusplus */ 111 112 #endif /* _ARCH_PMU_H */ 113