1 /** 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * Description: Provides pmp port template \n 16 * 17 * History: \n 18 * 2022-09-26， Create file. \n 19 */ 20 #ifndef REBOOT_PORTING_H 21 #define REBOOT_PORTING_H 22 23 #ifdef __cplusplus 24 #if __cplusplus 25 extern "C" { 26 #endif 27 #endif 28 29 #define HAL_REBOOT_REASON_MCPU_WDT 0x2002 30 #define HAL_REBOOT_REASON_DSP_WDT 0x4002 31 #define HAL_REBOOT_REASON_BCPU_WDT 0x8002 32 #define HAL_REBOOT_REASON_BCPU_CHIP_WDT 0x8004 33 34 #if MASTER_BY_WS53_ONLY 35 #define HAL_CHIP_RESET_REG (ULP_AON_CTL_RB_ADDR + CHIP_RESET_OFF) 36 #else 37 #define HAL_CHIP_RESET_REG (GLB_CTL_M_RB_BASE + CHIP_RESET_OFF) 38 #endif 39 40 #define HAL_CHIP_RESET_REG_OFFSET 0x0 41 #define HAL_CHIP_RESET_REG_ENABLE_RESET_BIT 2 42 43 #define HAL_PMU_PROTECT_STATUS_REG (PMU1_CTL_RB_BASE + 0x370) 44 #define HAL_PMU_PROTECT_STATUS_CLR_REG (PMU1_CTL_RB_BASE + 0x370) 45 46 // buck short circuit protection, if this case occur, cpu can't read, only ssi can read the status. 47 #define HAL_PMU_PROTECT_BUCK2_SCP_BIT 2 48 #define HAL_PMU_PROTECT_BUCK1_SCP_BIT 3 49 #define HAL_PMU_PROTECT_CHIP_WDG_BIT 4 50 #define HAL_PMU_PROTECT_CHIP_WDG_BIT_CLR 0 51 52 #define HAL_BCPU_RESET_STS_REG (GLB_CTL_M_RB_BASE + 0x30) 53 #define HAL_MCPU_RESET_STS_REG (GLB_CTL_M_RB_BASE + 0x34) 54 55 // This status is valid when CLDO2 power on. 56 #define HAL_DSP_RESET_STS_REG (GLB_CTL_B_RB_BASE + 0x38) 57 #define HAL_RESET_STS_COMMON_RESET_BIT 0 // Control by RST_PULSE0 at GLB_CTL_B + 0x70 58 #define HAL_RESET_STS_CORE_RESET_BIT 1 // Control by RST_PULSE0 at GLB_CTL_B + 0x70 59 #define HAL_RESET_STS_CORE_WDT_RESET_BIT 2 60 #define HAL_RESET_STS_CLEAR_REG (GLB_CTL_M_RB_BASE + 0x3c) 61 #define HAL_RESET_STS_CLEAR_ALL 0xFF 62 63 // Software dedicated whether a hard power failure occurs 64 #define HAL_ULP_AON_GENERAL_REG (ULP_AON_CTL_RB_ADDR + 0x14) 65 66 #define HAL_ULP_AON_NO_POWEROFF_FLAG 0xA5A5 67 68 /** 69 * @defgroup drivers_port_reboot REBOOT 70 * @ingroup drivers_port 71 * @{ 72 */ 73 74 typedef enum reboot_port_rst_reason { 75 RST_REASON_WDT_RST = 0, 76 RST_REASON_SOFT_RST, 77 RST_REASON_HARD_RST, 78 RST_REASON_INVALID 79 } reboot_port_rst_reason_t; 80 81 void reboot_port_reboot_chip(void); 82 uint32_t reboot_port_get_rst_reason(void); 83 void reboot_mem_flash_erase(void); 84 void reboot_mem_save_to_flash(void); 85 /** 86 * @} 87 */ 88 89 #ifdef __cplusplus 90 #if __cplusplus 91 } 92 #endif /* __cplusplus */ 93 #endif /* __cplusplus */ 94 #endif