1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * SiliconBackplane Chipcommon core hardware definitions. 4 * 5 * The chipcommon core provides chip identification, SB control, 6 * JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer, 7 * GPIO interface, extbus, and support for serial and parallel flashes. 8 * 9 * $Id: sbchipc.h 825481 2019-06-14 10:06:03Z $ 10 * 11 * Copyright (C) 1999-2019, Broadcom. 12 * 13 * Unless you and Broadcom execute a separate written software license 14 * agreement governing use of this software, this software is licensed to you 15 * under the terms of the GNU General Public License version 2 (the "GPL"), 16 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 17 * following added to such license: 18 * 19 * As a special exception, the copyright holders of this software give you 20 * permission to link this software with independent modules, and to copy and 21 * distribute the resulting executable under terms of your choice, provided that 22 * you also meet, for each linked independent module, the terms and conditions of 23 * the license of that module. An independent module is a module which is not 24 * derived from this software. The special exception does not apply to any 25 * modifications of the software. 26 * 27 * Notwithstanding the above, under no circumstances may you combine this 28 * software in any way with any other Broadcom software provided under a license 29 * other than the GPL, without Broadcom's express prior written consent. 30 * 31 * 32 * <<Broadcom-WL-IPTag/Open:>> 33 */ 34 35 #ifndef _SBCHIPC_H 36 #define _SBCHIPC_H 37 38 #if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) 39 40 /* cpp contortions to concatenate w/arg prescan */ 41 #ifndef PAD 42 #define _PADLINE(line) pad ## line 43 #define _XSTR(line) _PADLINE(line) 44 #define PAD _XSTR(__LINE__) 45 #endif /* PAD */ 46 47 #define BCM_MASK32(msb, lsb) ((~0u >> (32u - (msb) - 1u)) & (~0u << (lsb))) 48 49 /** 50 * In chipcommon rev 49 the pmu registers have been moved from chipc to the pmu core if the 51 * 'AOBPresent' bit of 'CoreCapabilitiesExt' is set. If this field is set, the traditional chipc to 52 * [pmu|gci|sreng] register interface is deprecated and removed. These register blocks would instead 53 * be assigned their respective chipc-specific address space and connected to the Always On 54 * Backplane via the APB interface. 55 */ 56 typedef volatile struct { 57 uint32 PAD[384]; 58 uint32 pmucontrol; /* 0x600 */ 59 uint32 pmucapabilities; /* 0x604 */ 60 uint32 pmustatus; /* 0x608 */ 61 uint32 res_state; /* 0x60C */ 62 uint32 res_pending; /* 0x610 */ 63 uint32 pmutimer; /* 0x614 */ 64 uint32 min_res_mask; /* 0x618 */ 65 uint32 max_res_mask; /* 0x61C */ 66 uint32 res_table_sel; /* 0x620 */ 67 uint32 res_dep_mask; 68 uint32 res_updn_timer; 69 uint32 res_timer; 70 uint32 clkstretch; 71 uint32 pmuwatchdog; 72 uint32 gpiosel; /* 0x638, rev >= 1 */ 73 uint32 gpioenable; /* 0x63c, rev >= 1 */ 74 uint32 res_req_timer_sel; /* 0x640 */ 75 uint32 res_req_timer; /* 0x644 */ 76 uint32 res_req_mask; /* 0x648 */ 77 uint32 core_cap_ext; /* 0x64C */ 78 uint32 chipcontrol_addr; /* 0x650 */ 79 uint32 chipcontrol_data; /* 0x654 */ 80 uint32 regcontrol_addr; 81 uint32 regcontrol_data; 82 uint32 pllcontrol_addr; 83 uint32 pllcontrol_data; 84 uint32 pmustrapopt; /* 0x668, corerev >= 28 */ 85 uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ 86 uint32 retention_ctl; /* 0x670 */ 87 uint32 ILPPeriod; /* 0x674 */ 88 uint32 PAD[2]; 89 uint32 retention_grpidx; /* 0x680 */ 90 uint32 retention_grpctl; /* 0x684 */ 91 uint32 mac_res_req_timer; /* 0x688 */ 92 uint32 mac_res_req_mask; /* 0x68c */ 93 uint32 PAD[18]; 94 uint32 pmucontrol_ext; /* 0x6d8 */ 95 uint32 slowclkperiod; /* 0x6dc */ 96 uint32 pmu_statstimer_addr; /* 0x6e0 */ 97 uint32 pmu_statstimer_ctrl; /* 0x6e4 */ 98 uint32 pmu_statstimer_N; /* 0x6e8 */ 99 uint32 PAD[1]; 100 uint32 mac_res_req_timer1; /* 0x6f0 */ 101 uint32 mac_res_req_mask1; /* 0x6f4 */ 102 uint32 PAD[2]; 103 uint32 pmuintmask0; /* 0x700 */ 104 uint32 pmuintmask1; /* 0x704 */ 105 uint32 PAD[14]; 106 uint32 pmuintstatus; /* 0x740 */ 107 uint32 extwakeupstatus; /* 0x744 */ 108 uint32 watchdog_res_mask; /* 0x748 */ 109 uint32 PAD[1]; /* 0x74C */ 110 uint32 swscratch; /* 0x750 */ 111 uint32 PAD[3]; /* 0x754-0x75C */ 112 uint32 extwakemask0; /* 0x760 */ 113 uint32 extwakemask1; /* 0x764 */ 114 uint32 PAD[2]; /* 0x768-0x76C */ 115 uint32 extwakereqmask[2]; /* 0x770-0x774 */ 116 uint32 PAD[2]; /* 0x778-0x77C */ 117 uint32 pmuintctrl0; /* 0x780 */ 118 uint32 pmuintctrl1; /* 0x784 */ 119 uint32 PAD[2]; 120 uint32 extwakectrl[2]; /* 0x790 */ 121 uint32 PAD[7]; 122 uint32 fis_ctrl_status; /* 0x7b4 */ 123 uint32 fis_min_res_mask; /* 0x7b8 */ 124 uint32 PAD[1]; 125 uint32 PrecisionTmrCtrlStatus; /* 0x7c0 */ 126 } pmuregs_t; 127 128 typedef struct eci_prerev35 { 129 uint32 eci_output; 130 uint32 eci_control; 131 uint32 eci_inputlo; 132 uint32 eci_inputmi; 133 uint32 eci_inputhi; 134 uint32 eci_inputintpolaritylo; 135 uint32 eci_inputintpolaritymi; 136 uint32 eci_inputintpolarityhi; 137 uint32 eci_intmasklo; 138 uint32 eci_intmaskmi; 139 uint32 eci_intmaskhi; 140 uint32 eci_eventlo; 141 uint32 eci_eventmi; 142 uint32 eci_eventhi; 143 uint32 eci_eventmasklo; 144 uint32 eci_eventmaskmi; 145 uint32 eci_eventmaskhi; 146 uint32 PAD[3]; 147 } eci_prerev35_t; 148 149 typedef struct eci_rev35 { 150 uint32 eci_outputlo; 151 uint32 eci_outputhi; 152 uint32 eci_controllo; 153 uint32 eci_controlhi; 154 uint32 eci_inputlo; 155 uint32 eci_inputhi; 156 uint32 eci_inputintpolaritylo; 157 uint32 eci_inputintpolarityhi; 158 uint32 eci_intmasklo; 159 uint32 eci_intmaskhi; 160 uint32 eci_eventlo; 161 uint32 eci_eventhi; 162 uint32 eci_eventmasklo; 163 uint32 eci_eventmaskhi; 164 uint32 eci_auxtx; 165 uint32 eci_auxrx; 166 uint32 eci_datatag; 167 uint32 eci_uartescvalue; 168 uint32 eci_autobaudctr; 169 uint32 eci_uartfifolevel; 170 } eci_rev35_t; 171 172 typedef struct flash_config { 173 uint32 PAD[19]; 174 /* Flash struct configuration registers (0x18c) for BCM4706 (corerev = 31) */ 175 uint32 flashstrconfig; 176 } flash_config_t; 177 178 typedef volatile struct { 179 uint32 chipid; /* 0x0 */ 180 uint32 capabilities; 181 uint32 corecontrol; /* corerev >= 1 */ 182 uint32 bist; 183 184 /* OTP */ 185 uint32 otpstatus; /* 0x10, corerev >= 10 */ 186 uint32 otpcontrol; 187 uint32 otpprog; 188 uint32 otplayout; /* corerev >= 23 */ 189 190 /* Interrupt control */ 191 uint32 intstatus; /* 0x20 */ 192 uint32 intmask; 193 194 /* Chip specific regs */ 195 uint32 chipcontrol; /* 0x28, rev >= 11 */ 196 uint32 chipstatus; /* 0x2c, rev >= 11 */ 197 198 /* Jtag Master */ 199 uint32 jtagcmd; /* 0x30, rev >= 10 */ 200 uint32 jtagir; 201 uint32 jtagdr; 202 uint32 jtagctrl; 203 204 /* serial flash interface registers */ 205 uint32 flashcontrol; /* 0x40 */ 206 uint32 flashaddress; 207 uint32 flashdata; 208 uint32 otplayoutextension; /* rev >= 35 */ 209 210 /* Silicon backplane configuration broadcast control */ 211 uint32 broadcastaddress; /* 0x50 */ 212 uint32 broadcastdata; 213 214 /* gpio - cleared only by power-on-reset */ 215 uint32 gpiopullup; /* 0x58, corerev >= 20 */ 216 uint32 gpiopulldown; /* 0x5c, corerev >= 20 */ 217 uint32 gpioin; /* 0x60 */ 218 uint32 gpioout; /* 0x64 */ 219 uint32 gpioouten; /* 0x68 */ 220 uint32 gpiocontrol; /* 0x6C */ 221 uint32 gpiointpolarity; /* 0x70 */ 222 uint32 gpiointmask; /* 0x74 */ 223 224 /* GPIO events corerev >= 11 */ 225 uint32 gpioevent; 226 uint32 gpioeventintmask; 227 228 /* Watchdog timer */ 229 uint32 watchdog; /* 0x80 */ 230 231 /* GPIO events corerev >= 11 */ 232 uint32 gpioeventintpolarity; 233 234 /* GPIO based LED powersave registers corerev >= 16 */ 235 uint32 gpiotimerval; /* 0x88 */ 236 uint32 gpiotimeroutmask; 237 238 /* clock control */ 239 uint32 clockcontrol_n; /* 0x90 */ 240 uint32 clockcontrol_sb; /* aka m0 */ 241 uint32 clockcontrol_pci; /* aka m1 */ 242 uint32 clockcontrol_m2; /* mii/uart/mipsref */ 243 uint32 clockcontrol_m3; /* cpu */ 244 uint32 clkdiv; /* corerev >= 3 */ 245 uint32 gpiodebugsel; /* corerev >= 28 */ 246 uint32 capabilities_ext; /* 0xac */ 247 248 /* pll delay registers (corerev >= 4) */ 249 uint32 pll_on_delay; /* 0xb0 */ 250 uint32 fref_sel_delay; 251 uint32 slow_clk_ctl; /* 5 < corerev < 10 */ 252 uint32 PAD; 253 254 /* Instaclock registers (corerev >= 10) */ 255 uint32 system_clk_ctl; /* 0xc0 */ 256 uint32 clkstatestretch; 257 uint32 PAD[2]; 258 259 /* Indirect backplane access (corerev >= 22) */ 260 uint32 bp_addrlow; /* 0xd0 */ 261 uint32 bp_addrhigh; 262 uint32 bp_data; 263 uint32 PAD; 264 uint32 bp_indaccess; 265 /* SPI registers, corerev >= 37 */ 266 uint32 gsioctrl; 267 uint32 gsioaddress; 268 uint32 gsiodata; 269 270 /* More clock dividers (corerev >= 32) */ 271 uint32 clkdiv2; 272 /* FAB ID (corerev >= 40) */ 273 uint32 otpcontrol1; 274 uint32 fabid; /* 0xf8 */ 275 276 /* In AI chips, pointer to erom */ 277 uint32 eromptr; /* 0xfc */ 278 279 /* ExtBus control registers (corerev >= 3) */ 280 uint32 pcmcia_config; /* 0x100 */ 281 uint32 pcmcia_memwait; 282 uint32 pcmcia_attrwait; 283 uint32 pcmcia_iowait; 284 uint32 ide_config; 285 uint32 ide_memwait; 286 uint32 ide_attrwait; 287 uint32 ide_iowait; 288 uint32 prog_config; 289 uint32 prog_waitcount; 290 uint32 flash_config; 291 uint32 flash_waitcount; 292 uint32 SECI_config; /* 0x130 SECI configuration */ 293 uint32 SECI_status; 294 uint32 SECI_statusmask; 295 uint32 SECI_rxnibchanged; 296 297 uint32 PAD[20]; 298 299 /* SROM interface (corerev >= 32) */ 300 uint32 sromcontrol; /* 0x190 */ 301 uint32 sromaddress; 302 uint32 sromdata; 303 uint32 PAD[1]; /* 0x19C */ 304 /* NAND flash registers for BCM4706 (corerev = 31) */ 305 uint32 nflashctrl; /* 0x1a0 */ 306 uint32 nflashconf; 307 uint32 nflashcoladdr; 308 uint32 nflashrowaddr; 309 uint32 nflashdata; 310 uint32 nflashwaitcnt0; /* 0x1b4 */ 311 uint32 PAD[2]; 312 313 uint32 seci_uart_data; /* 0x1C0 */ 314 uint32 seci_uart_bauddiv; 315 uint32 seci_uart_fcr; 316 uint32 seci_uart_lcr; 317 uint32 seci_uart_mcr; 318 uint32 seci_uart_lsr; 319 uint32 seci_uart_msr; 320 uint32 seci_uart_baudadj; 321 /* Clock control and hardware workarounds (corerev >= 20) */ 322 uint32 clk_ctl_st; /* 0x1e0 */ 323 uint32 hw_war; 324 uint32 powerctl; /* 0x1e8 */ 325 uint32 PAD[69]; 326 327 /* UARTs */ 328 uint8 uart0data; /* 0x300 */ 329 uint8 uart0imr; 330 uint8 uart0fcr; 331 uint8 uart0lcr; 332 uint8 uart0mcr; 333 uint8 uart0lsr; 334 uint8 uart0msr; 335 uint8 uart0scratch; 336 uint8 PAD[248]; /* corerev >= 1 */ 337 338 uint8 uart1data; /* 0x400 */ 339 uint8 uart1imr; 340 uint8 uart1fcr; 341 uint8 uart1lcr; 342 uint8 uart1mcr; 343 uint8 uart1lsr; 344 uint8 uart1msr; 345 uint8 uart1scratch; /* 0x407 */ 346 uint32 PAD[50]; 347 uint32 sr_memrw_addr; /* 0x4d0 */ 348 uint32 sr_memrw_data; /* 0x4d4 */ 349 uint32 PAD[10]; 350 351 /* save/restore, corerev >= 48 */ 352 uint32 sr_capability; /* 0x500 */ 353 uint32 sr_control0; /* 0x504 */ 354 uint32 sr_control1; /* 0x508 */ 355 uint32 gpio_control; /* 0x50C */ 356 uint32 PAD[29]; 357 /* 2 SR engines case */ 358 uint32 sr1_control0; /* 0x584 */ 359 uint32 sr1_control1; /* 0x588 */ 360 uint32 PAD[29]; 361 /* PMU registers (corerev >= 20) */ 362 /* Note: all timers driven by ILP clock are updated asynchronously to HT/ALP. 363 * The CPU must read them twice, compare, and retry if different. 364 */ 365 uint32 pmucontrol; /* 0x600 */ 366 uint32 pmucapabilities; 367 uint32 pmustatus; 368 uint32 res_state; 369 uint32 res_pending; 370 uint32 pmutimer; 371 uint32 min_res_mask; 372 uint32 max_res_mask; 373 uint32 res_table_sel; 374 uint32 res_dep_mask; 375 uint32 res_updn_timer; 376 uint32 res_timer; 377 uint32 clkstretch; 378 uint32 pmuwatchdog; 379 uint32 gpiosel; /* 0x638, rev >= 1 */ 380 uint32 gpioenable; /* 0x63c, rev >= 1 */ 381 uint32 res_req_timer_sel; 382 uint32 res_req_timer; 383 uint32 res_req_mask; 384 uint32 core_cap_ext; /* 0x64c */ 385 uint32 chipcontrol_addr; /* 0x650 */ 386 uint32 chipcontrol_data; /* 0x654 */ 387 uint32 regcontrol_addr; 388 uint32 regcontrol_data; 389 uint32 pllcontrol_addr; 390 uint32 pllcontrol_data; 391 uint32 pmustrapopt; /* 0x668, corerev >= 28 */ 392 uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ 393 uint32 retention_ctl; /* 0x670 */ 394 uint32 ILPPeriod; /* 0x674 */ 395 uint32 PAD[2]; 396 uint32 retention_grpidx; /* 0x680 */ 397 uint32 retention_grpctl; /* 0x684 */ 398 uint32 mac_res_req_timer; /* 0x688 */ 399 uint32 mac_res_req_mask; /* 0x68c */ 400 uint32 PAD[18]; 401 uint32 pmucontrol_ext; /* 0x6d8 */ 402 uint32 slowclkperiod; /* 0x6dc */ 403 uint32 pmu_statstimer_addr; /* 0x6e0 */ 404 uint32 pmu_statstimer_ctrl; /* 0x6e4 */ 405 uint32 pmu_statstimer_N; /* 0x6e8 */ 406 uint32 PAD[1]; 407 uint32 mac_res_req_timer1; /* 0x6f0 */ 408 uint32 mac_res_req_mask1; /* 0x6f4 */ 409 uint32 PAD[2]; 410 uint32 pmuintmask0; /* 0x700 */ 411 uint32 pmuintmask1; /* 0x704 */ 412 uint32 PAD[14]; 413 uint32 pmuintstatus; /* 0x740 */ 414 uint32 extwakeupstatus; /* 0x744 */ 415 uint32 PAD[6]; 416 uint32 extwakemask0; /* 0x760 */ 417 uint32 extwakemask1; /* 0x764 */ 418 uint32 PAD[2]; /* 0x768-0x76C */ 419 uint32 extwakereqmask[2]; /* 0x770-0x774 */ 420 uint32 PAD[2]; /* 0x778-0x77C */ 421 uint32 pmuintctrl0; /* 0x780 */ 422 uint32 PAD[3]; /* 0x784 - 0x78c */ 423 uint32 extwakectrl[1]; /* 0x790 */ 424 uint32 PAD[8]; 425 uint32 fis_ctrl_status; /* 0x7b4 */ 426 uint32 fis_min_res_mask; /* 0x7b8 */ 427 uint32 PAD[17]; 428 uint16 sromotp[512]; /* 0x800 */ 429 #ifdef CCNFLASH_SUPPORT 430 /* Nand flash MLC controller registers (corerev >= 38) */ 431 uint32 nand_revision; /* 0xC00 */ 432 uint32 nand_cmd_start; 433 uint32 nand_cmd_addr_x; 434 uint32 nand_cmd_addr; 435 uint32 nand_cmd_end_addr; 436 uint32 nand_cs_nand_select; 437 uint32 nand_cs_nand_xor; 438 uint32 PAD; 439 uint32 nand_spare_rd0; 440 uint32 nand_spare_rd4; 441 uint32 nand_spare_rd8; 442 uint32 nand_spare_rd12; 443 uint32 nand_spare_wr0; 444 uint32 nand_spare_wr4; 445 uint32 nand_spare_wr8; 446 uint32 nand_spare_wr12; 447 uint32 nand_acc_control; 448 uint32 PAD; 449 uint32 nand_config; 450 uint32 PAD; 451 uint32 nand_timing_1; 452 uint32 nand_timing_2; 453 uint32 nand_semaphore; 454 uint32 PAD; 455 uint32 nand_devid; 456 uint32 nand_devid_x; 457 uint32 nand_block_lock_status; 458 uint32 nand_intfc_status; 459 uint32 nand_ecc_corr_addr_x; 460 uint32 nand_ecc_corr_addr; 461 uint32 nand_ecc_unc_addr_x; 462 uint32 nand_ecc_unc_addr; 463 uint32 nand_read_error_count; 464 uint32 nand_corr_stat_threshold; 465 uint32 PAD[2]; 466 uint32 nand_read_addr_x; 467 uint32 nand_read_addr; 468 uint32 nand_page_program_addr_x; 469 uint32 nand_page_program_addr; 470 uint32 nand_copy_back_addr_x; 471 uint32 nand_copy_back_addr; 472 uint32 nand_block_erase_addr_x; 473 uint32 nand_block_erase_addr; 474 uint32 nand_inv_read_addr_x; 475 uint32 nand_inv_read_addr; 476 uint32 PAD[2]; 477 uint32 nand_blk_wr_protect; 478 uint32 PAD[3]; 479 uint32 nand_acc_control_cs1; 480 uint32 nand_config_cs1; 481 uint32 nand_timing_1_cs1; 482 uint32 nand_timing_2_cs1; 483 uint32 PAD[20]; 484 uint32 nand_spare_rd16; 485 uint32 nand_spare_rd20; 486 uint32 nand_spare_rd24; 487 uint32 nand_spare_rd28; 488 uint32 nand_cache_addr; 489 uint32 nand_cache_data; 490 uint32 nand_ctrl_config; 491 uint32 nand_ctrl_status; 492 #endif /* CCNFLASH_SUPPORT */ 493 uint32 gci_corecaps0; /* GCI starting at 0xC00 */ 494 uint32 gci_corecaps1; 495 uint32 gci_corecaps2; 496 uint32 gci_corectrl; 497 uint32 gci_corestat; /* 0xC10 */ 498 uint32 gci_intstat; /* 0xC14 */ 499 uint32 gci_intmask; /* 0xC18 */ 500 uint32 gci_wakemask; /* 0xC1C */ 501 uint32 gci_levelintstat; /* 0xC20 */ 502 uint32 gci_eventintstat; /* 0xC24 */ 503 uint32 PAD[6]; 504 uint32 gci_indirect_addr; /* 0xC40 */ 505 uint32 gci_gpioctl; /* 0xC44 */ 506 uint32 gci_gpiostatus; 507 uint32 gci_gpiomask; /* 0xC4C */ 508 uint32 gci_eventsummary; /* 0xC50 */ 509 uint32 gci_miscctl; /* 0xC54 */ 510 uint32 gci_gpiointmask; 511 uint32 gci_gpiowakemask; 512 uint32 gci_input[32]; /* C60 */ 513 uint32 gci_event[32]; /* CE0 */ 514 uint32 gci_output[4]; /* D60 */ 515 uint32 gci_control_0; /* 0xD70 */ 516 uint32 gci_control_1; /* 0xD74 */ 517 uint32 gci_intpolreg; /* 0xD78 */ 518 uint32 gci_levelintmask; /* 0xD7C */ 519 uint32 gci_eventintmask; /* 0xD80 */ 520 uint32 PAD[3]; 521 uint32 gci_inbandlevelintmask; /* 0xD90 */ 522 uint32 gci_inbandeventintmask; /* 0xD94 */ 523 uint32 PAD[2]; 524 uint32 gci_seciauxtx; /* 0xDA0 */ 525 uint32 gci_seciauxrx; /* 0xDA4 */ 526 uint32 gci_secitx_datatag; /* 0xDA8 */ 527 uint32 gci_secirx_datatag; /* 0xDAC */ 528 uint32 gci_secitx_datamask; /* 0xDB0 */ 529 uint32 gci_seciusef0tx_reg; /* 0xDB4 */ 530 uint32 gci_secif0tx_offset; /* 0xDB8 */ 531 uint32 gci_secif0rx_offset; /* 0xDBC */ 532 uint32 gci_secif1tx_offset; /* 0xDC0 */ 533 uint32 gci_rxfifo_common_ctrl; /* 0xDC4 */ 534 uint32 gci_rxfifoctrl; /* 0xDC8 */ 535 uint32 gci_uartreadid; /* DCC */ 536 uint32 gci_seciuartescval; /* DD0 */ 537 uint32 PAD; 538 uint32 gci_secififolevel; /* DD8 */ 539 uint32 gci_seciuartdata; /* DDC */ 540 uint32 gci_secibauddiv; /* DE0 */ 541 uint32 gci_secifcr; /* DE4 */ 542 uint32 gci_secilcr; /* DE8 */ 543 uint32 gci_secimcr; /* DEC */ 544 uint32 gci_secilsr; /* DF0 */ 545 uint32 gci_secimsr; /* DF4 */ 546 uint32 gci_baudadj; /* DF8 */ 547 uint32 PAD; 548 uint32 gci_chipctrl; /* 0xE00 */ 549 uint32 gci_chipsts; /* 0xE04 */ 550 uint32 gci_gpioout; /* 0xE08 */ 551 uint32 gci_gpioout_read; /* 0xE0C */ 552 uint32 gci_mpwaketx; /* 0xE10 */ 553 uint32 gci_mpwakedetect; /* 0xE14 */ 554 uint32 gci_seciin_ctrl; /* 0xE18 */ 555 uint32 gci_seciout_ctrl; /* 0xE1C */ 556 uint32 gci_seciin_auxfifo_en; /* 0xE20 */ 557 uint32 gci_seciout_txen_txbr; /* 0xE24 */ 558 uint32 gci_seciin_rxbrstatus; /* 0xE28 */ 559 uint32 gci_seciin_rxerrstatus; /* 0xE2C */ 560 uint32 gci_seciin_fcstatus; /* 0xE30 */ 561 uint32 gci_seciout_txstatus; /* 0xE34 */ 562 uint32 gci_seciout_txbrstatus; /* 0xE38 */ 563 } chipcregs_t; 564 565 #endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */ 566 567 #define CC_CHIPID 0 568 #define CC_CAPABILITIES 4 569 #define CC_CHIPST 0x2c 570 #define CC_EROMPTR 0xfc 571 572 #define CC_OTPST 0x10 573 #define CC_INTSTATUS 0x20 574 #define CC_INTMASK 0x24 575 #define CC_JTAGCMD 0x30 576 #define CC_JTAGIR 0x34 577 #define CC_JTAGDR 0x38 578 #define CC_JTAGCTRL 0x3c 579 #define CC_GPIOPU 0x58 580 #define CC_GPIOPD 0x5c 581 #define CC_GPIOIN 0x60 582 #define CC_GPIOOUT 0x64 583 #define CC_GPIOOUTEN 0x68 584 #define CC_GPIOCTRL 0x6c 585 #define CC_GPIOPOL 0x70 586 #define CC_GPIOINTM 0x74 587 #define CC_GPIOEVENT 0x78 588 #define CC_GPIOEVENTMASK 0x7c 589 #define CC_WATCHDOG 0x80 590 #define CC_GPIOEVENTPOL 0x84 591 #define CC_CLKC_N 0x90 592 #define CC_CLKC_M0 0x94 593 #define CC_CLKC_M1 0x98 594 #define CC_CLKC_M2 0x9c 595 #define CC_CLKC_M3 0xa0 596 #define CC_CLKDIV 0xa4 597 #define CC_CAP_EXT 0xac 598 #define CC_SYS_CLK_CTL 0xc0 599 #define CC_CLKDIV2 0xf0 600 #define CC_CLK_CTL_ST SI_CLK_CTL_ST 601 #define PMU_CTL 0x600 602 #define PMU_CAP 0x604 603 #define PMU_ST 0x608 604 #define PMU_RES_STATE 0x60c 605 #define PMU_RES_PENDING 0x610 606 #define PMU_TIMER 0x614 607 #define PMU_MIN_RES_MASK 0x618 608 #define PMU_MAX_RES_MASK 0x61c 609 #define CC_CHIPCTL_ADDR 0x650 610 #define CC_CHIPCTL_DATA 0x654 611 #define PMU_REG_CONTROL_ADDR 0x658 612 #define PMU_REG_CONTROL_DATA 0x65C 613 #define PMU_PLL_CONTROL_ADDR 0x660 614 #define PMU_PLL_CONTROL_DATA 0x664 615 616 #define CC_SROM_CTRL 0x190 617 #define CC_SROM_ADDRESS 0x194u 618 #define CC_SROM_DATA 0x198u 619 #ifdef SROM16K_4364_ADDRSPACE 620 #define CC_SROM_OTP 0xa000 /* SROM/OTP address space */ 621 #else 622 #define CC_SROM_OTP 0x0800 623 #endif // endif 624 #define CC_GCI_INDIRECT_ADDR_REG 0xC40 625 #define CC_GCI_CHIP_CTRL_REG 0xE00 626 #define CC_GCI_CC_OFFSET_2 2 627 #define CC_GCI_CC_OFFSET_5 5 628 #define CC_SWD_CTRL 0x380 629 #define CC_SWD_REQACK 0x384 630 #define CC_SWD_DATA 0x388 631 #define GPIO_SEL_0 0x00001111 632 #define GPIO_SEL_1 0x11110000 633 #define GPIO_SEL_8 0x00001111 634 #define GPIO_SEL_9 0x11110000 635 636 #define CHIPCTRLREG0 0x0 637 #define CHIPCTRLREG1 0x1 638 #define CHIPCTRLREG2 0x2 639 #define CHIPCTRLREG3 0x3 640 #define CHIPCTRLREG4 0x4 641 #define CHIPCTRLREG5 0x5 642 #define CHIPCTRLREG6 0x6 643 #define REGCTRLREG4 0x4 644 #define REGCTRLREG5 0x5 645 #define REGCTRLREG6 0x6 646 #define MINRESMASKREG 0x618 647 #define MAXRESMASKREG 0x61c 648 #define CHIPCTRLADDR 0x650 649 #define CHIPCTRLDATA 0x654 650 #define RSRCTABLEADDR 0x620 651 #define PMU_RES_DEP_MASK 0x624 652 #define RSRCUPDWNTIME 0x628 653 #define PMUREG_RESREQ_MASK 0x68c 654 #define PMUREG_RESREQ_TIMER 0x688 655 #define PMUREG_RESREQ_MASK1 0x6f4 656 #define PMUREG_RESREQ_TIMER1 0x6f0 657 #define EXT_LPO_AVAIL 0x100 658 #define LPO_SEL (1 << 0) 659 #define CC_EXT_LPO_PU 0x200000 660 #define GC_EXT_LPO_PU 0x2 661 #define CC_INT_LPO_PU 0x100000 662 #define GC_INT_LPO_PU 0x1 663 #define EXT_LPO_SEL 0x8 664 #define INT_LPO_SEL 0x4 665 #define ENABLE_FINE_CBUCK_CTRL (1 << 30) 666 #define REGCTRL5_PWM_AUTO_CTRL_MASK 0x007e0000 667 #define REGCTRL5_PWM_AUTO_CTRL_SHIFT 17 668 #define REGCTRL6_PWM_AUTO_CTRL_MASK 0x3fff0000 669 #define REGCTRL6_PWM_AUTO_CTRL_SHIFT 16 670 #define CC_BP_IND_ACCESS_START_SHIFT 9 671 #define CC_BP_IND_ACCESS_START_MASK (1 << CC_BP_IND_ACCESS_START_SHIFT) 672 #define CC_BP_IND_ACCESS_RDWR_SHIFT 8 673 #define CC_BP_IND_ACCESS_RDWR_MASK (1 << CC_BP_IND_ACCESS_RDWR_SHIFT) 674 #define CC_BP_IND_ACCESS_ERROR_SHIFT 10 675 #define CC_BP_IND_ACCESS_ERROR_MASK (1 << CC_BP_IND_ACCESS_ERROR_SHIFT) 676 677 #define LPO_SEL_TIMEOUT 1000 678 679 #define LPO_FINAL_SEL_SHIFT 18 680 681 #define LHL_LPO1_SEL 0 682 #define LHL_LPO2_SEL 0x1 683 #define LHL_32k_SEL 0x2 684 #define LHL_EXT_SEL 0x3 685 686 #define EXTLPO_BUF_PD 0x40 687 #define LPO1_PD_EN 0x1 688 #define LPO1_PD_SEL 0x6 689 #define LPO1_PD_SEL_VAL 0x4 690 #define LPO2_PD_EN 0x8 691 #define LPO2_PD_SEL 0x30 692 #define LPO2_PD_SEL_VAL 0x20 693 #define OSC_32k_PD 0x80 694 695 #define LHL_CLK_DET_CTL_AD_CNTR_CLK_SEL 0x3 696 697 #define LHL_LPO_AUTO 0x0 698 #define LHL_LPO1_ENAB 0x1 699 #define LHL_LPO2_ENAB 0x2 700 #define LHL_OSC_32k_ENAB 0x3 701 #define LHL_EXT_LPO_ENAB 0x4 702 #define RADIO_LPO_ENAB 0x5 703 704 #define LHL_CLK_DET_CTL_ADR_LHL_CNTR_EN 0x4 705 #define LHL_CLK_DET_CTL_ADR_LHL_CNTR_CLR 0x8 706 #define LHL_CLK_DET_CNT 0xF0 707 #define LHL_CLK_DET_CNT_SHIFT 4 708 #define LPO_SEL_SHIFT 9 709 710 #define LHL_MAIN_CTL_ADR_FINAL_CLK_SEL 0x3C0000 711 #define LHL_MAIN_CTL_ADR_LHL_WLCLK_SEL 0x600 712 713 #define CLK_DET_CNT_THRESH 8 714 715 #ifdef SR_DEBUG 716 #define SUBCORE_POWER_ON 0x0001 717 #define PHY_POWER_ON 0x0010 718 #define VDDM_POWER_ON 0x0100 719 #define MEMLPLDO_POWER_ON 0x1000 720 #define SUBCORE_POWER_ON_CHK 0x00040000 721 #define PHY_POWER_ON_CHK 0x00080000 722 #define VDDM_POWER_ON_CHK 0x00100000 723 #define MEMLPLDO_POWER_ON_CHK 0x00200000 724 #endif /* SR_DEBUG */ 725 726 #ifdef CCNFLASH_SUPPORT 727 /* NAND flash support */ 728 #define CC_NAND_REVISION 0xC00 729 #define CC_NAND_CMD_START 0xC04 730 #define CC_NAND_CMD_ADDR 0xC0C 731 #define CC_NAND_SPARE_RD_0 0xC20 732 #define CC_NAND_SPARE_RD_4 0xC24 733 #define CC_NAND_SPARE_RD_8 0xC28 734 #define CC_NAND_SPARE_RD_C 0xC2C 735 #define CC_NAND_CONFIG 0xC48 736 #define CC_NAND_DEVID 0xC60 737 #define CC_NAND_DEVID_EXT 0xC64 738 #define CC_NAND_INTFC_STATUS 0xC6C 739 #endif /* CCNFLASH_SUPPORT */ 740 741 /* chipid */ 742 #define CID_ID_MASK 0x0000ffff /**< Chip Id mask */ 743 #define CID_REV_MASK 0x000f0000 /**< Chip Revision mask */ 744 #define CID_REV_SHIFT 16 /**< Chip Revision shift */ 745 #define CID_PKG_MASK 0x00f00000 /**< Package Option mask */ 746 #define CID_PKG_SHIFT 20 /**< Package Option shift */ 747 #define CID_CC_MASK 0x0f000000 /**< CoreCount (corerev >= 4) */ 748 #define CID_CC_SHIFT 24 749 #define CID_TYPE_MASK 0xf0000000 /**< Chip Type */ 750 #define CID_TYPE_SHIFT 28 751 752 /* capabilities */ 753 #define CC_CAP_UARTS_MASK 0x00000003 /**< Number of UARTs */ 754 #define CC_CAP_MIPSEB 0x00000004 /**< MIPS is in big-endian mode */ 755 #define CC_CAP_UCLKSEL 0x00000018 /**< UARTs clock select */ 756 #define CC_CAP_UINTCLK 0x00000008 /**< UARTs are driven by internal divided clock */ 757 #define CC_CAP_UARTGPIO 0x00000020 /**< UARTs own GPIOs 15:12 */ 758 #define CC_CAP_EXTBUS_MASK 0x000000c0 /**< External bus mask */ 759 #define CC_CAP_EXTBUS_NONE 0x00000000 /**< No ExtBus present */ 760 #define CC_CAP_EXTBUS_FULL 0x00000040 /**< ExtBus: PCMCIA, IDE & Prog */ 761 #define CC_CAP_EXTBUS_PROG 0x00000080 /**< ExtBus: ProgIf only */ 762 #define CC_CAP_FLASH_MASK 0x00000700 /**< Type of flash */ 763 #define CC_CAP_PLL_MASK 0x00038000 /**< Type of PLL */ 764 #define CC_CAP_PWR_CTL 0x00040000 /**< Power control */ 765 #define CC_CAP_OTPSIZE 0x00380000 /**< OTP Size (0 = none) */ 766 #define CC_CAP_OTPSIZE_SHIFT 19 /**< OTP Size shift */ 767 #define CC_CAP_OTPSIZE_BASE 5 /**< OTP Size base */ 768 #define CC_CAP_JTAGP 0x00400000 /**< JTAG Master Present */ 769 #define CC_CAP_ROM 0x00800000 /**< Internal boot rom active */ 770 #define CC_CAP_BKPLN64 0x08000000 /**< 64-bit backplane */ 771 #define CC_CAP_PMU 0x10000000 /**< PMU Present, rev >= 20 */ 772 #define CC_CAP_ECI 0x20000000 /**< ECI Present, rev >= 21 */ 773 #define CC_CAP_SROM 0x40000000 /**< Srom Present, rev >= 32 */ 774 #define CC_CAP_NFLASH 0x80000000 /**< Nand flash present, rev >= 35 */ 775 776 #define CC_CAP2_SECI 0x00000001 /**< SECI Present, rev >= 36 */ 777 #define CC_CAP2_GSIO 0x00000002 /**< GSIO (spi/i2c) present, rev >= 37 */ 778 779 /* capabilities extension */ 780 #define CC_CAP_EXT_SECI_PRESENT 0x00000001 /**< SECI present */ 781 #define CC_CAP_EXT_GSIO_PRESENT 0x00000002 /**< GSIO present */ 782 #define CC_CAP_EXT_GCI_PRESENT 0x00000004 /**< GCI present */ 783 #define CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008 /**< UART present */ 784 #define CC_CAP_EXT_AOB_PRESENT 0x00000040 /**< AOB present */ 785 #define CC_CAP_EXT_SWD_PRESENT 0x00000400 /**< SWD present */ 786 787 /* WL Channel Info to BT via GCI - bits 40 - 47 */ 788 #define GCI_WL_CHN_INFO_MASK (0xFF00) 789 /* WL indication of MCHAN enabled/disabled to BT in awdl mode- bit 36 */ 790 #define GCI_WL_MCHAN_BIT_MASK (0x0010) 791 792 #ifdef WLC_SW_DIVERSITY 793 /* WL indication of SWDIV enabled/disabled to BT - bit 33 */ 794 #define GCI_WL_SWDIV_ANT_VALID_BIT_MASK (0x0002) 795 #define GCI_SWDIV_ANT_VALID_SHIFT 0x1 796 #define GCI_SWDIV_ANT_VALID_DISABLE 0x0 797 #endif // endif 798 799 /* WL Strobe to BT */ 800 #define GCI_WL_STROBE_BIT_MASK (0x0020) 801 /* bits [51:48] - reserved for wlan TX pwr index */ 802 /* bits [55:52] btc mode indication */ 803 #define GCI_WL_BTC_MODE_SHIFT (20) 804 #define GCI_WL_BTC_MODE_MASK (0xF << GCI_WL_BTC_MODE_SHIFT) 805 #define GCI_WL_ANT_BIT_MASK (0x00c0) 806 #define GCI_WL_ANT_SHIFT_BITS (6) 807 /* PLL type */ 808 #define PLL_NONE 0x00000000 809 #define PLL_TYPE1 0x00010000 /**< 48MHz base, 3 dividers */ 810 #define PLL_TYPE2 0x00020000 /**< 48MHz, 4 dividers */ 811 #define PLL_TYPE3 0x00030000 /**< 25MHz, 2 dividers */ 812 #define PLL_TYPE4 0x00008000 /**< 48MHz, 4 dividers */ 813 #define PLL_TYPE5 0x00018000 /**< 25MHz, 4 dividers */ 814 #define PLL_TYPE6 0x00028000 /**< 100/200 or 120/240 only */ 815 #define PLL_TYPE7 0x00038000 /**< 25MHz, 4 dividers */ 816 817 /* ILP clock */ 818 #define ILP_CLOCK 32000 819 820 /* ALP clock on pre-PMU chips */ 821 #define ALP_CLOCK 20000000 822 823 #ifdef CFG_SIM 824 #define NS_ALP_CLOCK 84922 825 #define NS_SLOW_ALP_CLOCK 84922 826 #define NS_CPU_CLOCK 534500 827 #define NS_SLOW_CPU_CLOCK 534500 828 #define NS_SI_CLOCK 271750 829 #define NS_SLOW_SI_CLOCK 271750 830 #define NS_FAST_MEM_CLOCK 271750 831 #define NS_MEM_CLOCK 271750 832 #define NS_SLOW_MEM_CLOCK 271750 833 #else 834 #define NS_ALP_CLOCK 125000000 835 #define NS_SLOW_ALP_CLOCK 100000000 836 #define NS_CPU_CLOCK 1000000000 837 #define NS_SLOW_CPU_CLOCK 800000000 838 #define NS_SI_CLOCK 250000000 839 #define NS_SLOW_SI_CLOCK 200000000 840 #define NS_FAST_MEM_CLOCK 800000000 841 #define NS_MEM_CLOCK 533000000 842 #define NS_SLOW_MEM_CLOCK 400000000 843 #endif /* CFG_SIM */ 844 845 #define ALP_CLOCK_53573 40000000 846 847 /* HT clock */ 848 #define HT_CLOCK 80000000 849 850 /* corecontrol */ 851 #define CC_UARTCLKO 0x00000001 /**< Drive UART with internal clock */ 852 #define CC_SE 0x00000002 /**< sync clk out enable (corerev >= 3) */ 853 #define CC_ASYNCGPIO 0x00000004 /**< 1=generate GPIO interrupt without backplane clock */ 854 #define CC_UARTCLKEN 0x00000008 /**< enable UART Clock (corerev > = 21 */ 855 856 /* retention_ctl */ 857 #define RCTL_MEM_RET_SLEEP_LOG_SHIFT 29 858 #define RCTL_MEM_RET_SLEEP_LOG_MASK (1 << RCTL_MEM_RET_SLEEP_LOG_SHIFT) 859 860 /* 4321 chipcontrol */ 861 #define CHIPCTRL_4321_PLL_DOWN 0x800000 /**< serdes PLL down override */ 862 863 /* Fields in the otpstatus register in rev >= 21 */ 864 #define OTPS_OL_MASK 0x000000ff 865 #define OTPS_OL_MFG 0x00000001 /**< manuf row is locked */ 866 #define OTPS_OL_OR1 0x00000002 /**< otp redundancy row 1 is locked */ 867 #define OTPS_OL_OR2 0x00000004 /**< otp redundancy row 2 is locked */ 868 #define OTPS_OL_GU 0x00000008 /**< general use region is locked */ 869 #define OTPS_GUP_MASK 0x00000f00 870 #define OTPS_GUP_SHIFT 8 871 #define OTPS_GUP_HW 0x00000100 /**< h/w subregion is programmed */ 872 #define OTPS_GUP_SW 0x00000200 /**< s/w subregion is programmed */ 873 #define OTPS_GUP_CI 0x00000400 /**< chipid/pkgopt subregion is programmed */ 874 #define OTPS_GUP_FUSE 0x00000800 /**< fuse subregion is programmed */ 875 #define OTPS_READY 0x00001000 876 #define OTPS_RV(x) (1 << (16 + (x))) /**< redundancy entry valid */ 877 #define OTPS_RV_MASK 0x0fff0000 878 #define OTPS_PROGOK 0x40000000 879 880 /* Fields in the otpcontrol register in rev >= 21 */ 881 #define OTPC_PROGSEL 0x00000001 882 #define OTPC_PCOUNT_MASK 0x0000000e 883 #define OTPC_PCOUNT_SHIFT 1 884 #define OTPC_VSEL_MASK 0x000000f0 885 #define OTPC_VSEL_SHIFT 4 886 #define OTPC_TMM_MASK 0x00000700 887 #define OTPC_TMM_SHIFT 8 888 #define OTPC_ODM 0x00000800 889 #define OTPC_PROGEN 0x80000000 890 891 /* Fields in the 40nm otpcontrol register in rev >= 40 */ 892 #define OTPC_40NM_PROGSEL_SHIFT 0 893 #define OTPC_40NM_PCOUNT_SHIFT 1 894 #define OTPC_40NM_PCOUNT_WR 0xA 895 #define OTPC_40NM_PCOUNT_V1X 0xB 896 #define OTPC_40NM_REGCSEL_SHIFT 5 897 #define OTPC_40NM_REGCSEL_DEF 0x4 898 #define OTPC_40NM_PROGIN_SHIFT 8 899 #define OTPC_40NM_R2X_SHIFT 10 900 #define OTPC_40NM_ODM_SHIFT 11 901 #define OTPC_40NM_DF_SHIFT 15 902 #define OTPC_40NM_VSEL_SHIFT 16 903 #define OTPC_40NM_VSEL_WR 0xA 904 #define OTPC_40NM_VSEL_V1X 0xA 905 #define OTPC_40NM_VSEL_R1X 0x5 906 #define OTPC_40NM_COFAIL_SHIFT 30 907 908 #define OTPC1_CPCSEL_SHIFT 0 909 #define OTPC1_CPCSEL_DEF 6 910 #define OTPC1_TM_SHIFT 8 911 #define OTPC1_TM_WR 0x84 912 #define OTPC1_TM_V1X 0x84 913 #define OTPC1_TM_R1X 0x4 914 #define OTPC1_CLK_EN_MASK 0x00020000 915 #define OTPC1_CLK_DIV_MASK 0x00FC0000 916 917 /* Fields in otpprog in rev >= 21 and HND OTP */ 918 #define OTPP_COL_MASK 0x000000ff 919 #define OTPP_COL_SHIFT 0 920 #define OTPP_ROW_MASK 0x0000ff00 921 #define OTPP_ROW_MASK9 0x0001ff00 /* for ccrev >= 49 */ 922 #define OTPP_ROW_SHIFT 8 923 #define OTPP_OC_MASK 0x0f000000 924 #define OTPP_OC_SHIFT 24 925 #define OTPP_READERR 0x10000000 926 #define OTPP_VALUE_MASK 0x20000000 927 #define OTPP_VALUE_SHIFT 29 928 #define OTPP_START_BUSY 0x80000000 929 #define OTPP_READ 0x40000000 /* HND OTP */ 930 931 /* Fields in otplayout register */ 932 #define OTPL_HWRGN_OFF_MASK 0x00000FFF 933 #define OTPL_HWRGN_OFF_SHIFT 0 934 #define OTPL_WRAP_REVID_MASK 0x00F80000 935 #define OTPL_WRAP_REVID_SHIFT 19 936 #define OTPL_WRAP_TYPE_MASK 0x00070000 937 #define OTPL_WRAP_TYPE_SHIFT 16 938 #define OTPL_WRAP_TYPE_65NM 0 939 #define OTPL_WRAP_TYPE_40NM 1 940 #define OTPL_WRAP_TYPE_28NM 2 941 #define OTPL_ROW_SIZE_MASK 0x0000F000 942 #define OTPL_ROW_SIZE_SHIFT 12 943 944 /* otplayout reg corerev >= 36 */ 945 #define OTP_CISFORMAT_NEW 0x80000000 946 947 /* Opcodes for OTPP_OC field */ 948 #define OTPPOC_READ 0 949 #define OTPPOC_BIT_PROG 1 950 #define OTPPOC_VERIFY 3 951 #define OTPPOC_INIT 4 952 #define OTPPOC_SET 5 953 #define OTPPOC_RESET 6 954 #define OTPPOC_OCST 7 955 #define OTPPOC_ROW_LOCK 8 956 #define OTPPOC_PRESCN_TEST 9 957 958 /* Opcodes for OTPP_OC field (40NM) */ 959 #define OTPPOC_READ_40NM 0 960 #define OTPPOC_PROG_ENABLE_40NM 1 961 #define OTPPOC_PROG_DISABLE_40NM 2 962 #define OTPPOC_VERIFY_40NM 3 963 #define OTPPOC_WORD_VERIFY_1_40NM 4 964 #define OTPPOC_ROW_LOCK_40NM 5 965 #define OTPPOC_STBY_40NM 6 966 #define OTPPOC_WAKEUP_40NM 7 967 #define OTPPOC_WORD_VERIFY_0_40NM 8 968 #define OTPPOC_PRESCN_TEST_40NM 9 969 #define OTPPOC_BIT_PROG_40NM 10 970 #define OTPPOC_WORDPROG_40NM 11 971 #define OTPPOC_BURNIN_40NM 12 972 #define OTPPOC_AUTORELOAD_40NM 13 973 #define OTPPOC_OVST_READ_40NM 14 974 #define OTPPOC_OVST_PROG_40NM 15 975 976 /* Opcodes for OTPP_OC field (28NM) */ 977 #define OTPPOC_READ_28NM 0 978 #define OTPPOC_READBURST_28NM 1 979 #define OTPPOC_PROG_ENABLE_28NM 2 980 #define OTPPOC_PROG_DISABLE_28NM 3 981 #define OTPPOC_PRESCREEN_28NM 4 982 #define OTPPOC_PRESCREEN_RP_28NM 5 983 #define OTPPOC_FLUSH_28NM 6 984 #define OTPPOC_NOP_28NM 7 985 #define OTPPOC_PROG_ECC_28NM 8 986 #define OTPPOC_PROG_ECC_READ_28NM 9 987 #define OTPPOC_PROG_28NM 10 988 #define OTPPOC_PROGRAM_RP_28NM 11 989 #define OTPPOC_PROGRAM_OVST_28NM 12 990 #define OTPPOC_RELOAD_28NM 13 991 #define OTPPOC_ERASE_28NM 14 992 #define OTPPOC_LOAD_RF_28NM 15 993 #define OTPPOC_CTRL_WR_28NM 16 994 #define OTPPOC_CTRL_RD_28NM 17 995 #define OTPPOC_READ_HP_28NM 18 996 #define OTPPOC_READ_OVST_28NM 19 997 #define OTPPOC_READ_VERIFY0_28NM 20 998 #define OTPPOC_READ_VERIFY1_28NM 21 999 #define OTPPOC_READ_FORCE0_28NM 22 1000 #define OTPPOC_READ_FORCE1_28NM 23 1001 #define OTPPOC_BURNIN_28NM 24 1002 #define OTPPOC_PROGRAM_LOCK_28NM 25 1003 #define OTPPOC_PROGRAM_TESTCOL_28NM 26 1004 #define OTPPOC_READ_TESTCOL_28NM 27 1005 #define OTPPOC_READ_FOUT_28NM 28 1006 #define OTPPOC_SFT_RESET_28NM 29 1007 1008 #define OTPP_OC_MASK_28NM 0x0f800000 1009 #define OTPP_OC_SHIFT_28NM 23 1010 #define OTPC_PROGEN_28NM 0x8 1011 #define OTPC_DBLERRCLR 0x20 1012 #define OTPC_CLK_EN_MASK 0x00000040 1013 #define OTPC_CLK_DIV_MASK 0x00000F80 1014 1015 /* Fields in otplayoutextension */ 1016 #define OTPLAYOUTEXT_FUSE_MASK 0x3FF 1017 1018 /* Jtagm characteristics that appeared at a given corerev */ 1019 #define JTAGM_CREV_OLD 10 /**< Old command set, 16bit max IR */ 1020 #define JTAGM_CREV_IRP 22 /**< Able to do pause-ir */ 1021 #define JTAGM_CREV_RTI 28 /**< Able to do return-to-idle */ 1022 1023 /* jtagcmd */ 1024 #define JCMD_START 0x80000000 1025 #define JCMD_BUSY 0x80000000 1026 #define JCMD_STATE_MASK 0x60000000 1027 #define JCMD_STATE_TLR 0x00000000 /**< Test-logic-reset */ 1028 #define JCMD_STATE_PIR 0x20000000 /**< Pause IR */ 1029 #define JCMD_STATE_PDR 0x40000000 /**< Pause DR */ 1030 #define JCMD_STATE_RTI 0x60000000 /**< Run-test-idle */ 1031 #define JCMD0_ACC_MASK 0x0000f000 1032 #define JCMD0_ACC_IRDR 0x00000000 1033 #define JCMD0_ACC_DR 0x00001000 1034 #define JCMD0_ACC_IR 0x00002000 1035 #define JCMD0_ACC_RESET 0x00003000 1036 #define JCMD0_ACC_IRPDR 0x00004000 1037 #define JCMD0_ACC_PDR 0x00005000 1038 #define JCMD0_IRW_MASK 0x00000f00 1039 #define JCMD_ACC_MASK 0x000f0000 /**< Changes for corerev 11 */ 1040 #define JCMD_ACC_IRDR 0x00000000 1041 #define JCMD_ACC_DR 0x00010000 1042 #define JCMD_ACC_IR 0x00020000 1043 #define JCMD_ACC_RESET 0x00030000 1044 #define JCMD_ACC_IRPDR 0x00040000 1045 #define JCMD_ACC_PDR 0x00050000 1046 #define JCMD_ACC_PIR 0x00060000 1047 #define JCMD_ACC_IRDR_I 0x00070000 /**< rev 28: return to run-test-idle */ 1048 #define JCMD_ACC_DR_I 0x00080000 /**< rev 28: return to run-test-idle */ 1049 #define JCMD_IRW_MASK 0x00001f00 1050 #define JCMD_IRW_SHIFT 8 1051 #define JCMD_DRW_MASK 0x0000003f 1052 1053 /* jtagctrl */ 1054 #define JCTRL_FORCE_CLK 4 /**< Force clock */ 1055 #define JCTRL_EXT_EN 2 /**< Enable external targets */ 1056 #define JCTRL_EN 1 /**< Enable Jtag master */ 1057 #define JCTRL_TAPSEL_BIT 0x00000008 /**< JtagMasterCtrl tap_sel bit */ 1058 1059 /* swdmasterctrl */ 1060 #define SWDCTRL_INT_EN 8 /**< Enable internal targets */ 1061 #define SWDCTRL_FORCE_CLK 4 /**< Force clock */ 1062 #define SWDCTRL_OVJTAG 2 /**< Enable shared SWD/JTAG pins */ 1063 #define SWDCTRL_EN 1 /**< Enable Jtag master */ 1064 1065 /* Fields in clkdiv */ 1066 #define CLKD_SFLASH 0x1f000000 1067 #define CLKD_SFLASH_SHIFT 24 1068 #define CLKD_OTP 0x000f0000 1069 #define CLKD_OTP_SHIFT 16 1070 #define CLKD_JTAG 0x00000f00 1071 #define CLKD_JTAG_SHIFT 8 1072 #define CLKD_UART 0x000000ff 1073 1074 #define CLKD2_SROM 0x00000007 1075 #define CLKD2_SROMDIV_32 0 1076 #define CLKD2_SROMDIV_64 1 1077 #define CLKD2_SROMDIV_96 2 1078 #define CLKD2_SROMDIV_128 3 1079 #define CLKD2_SROMDIV_192 4 1080 #define CLKD2_SROMDIV_256 5 1081 #define CLKD2_SROMDIV_384 6 1082 #define CLKD2_SROMDIV_512 7 1083 #define CLKD2_SWD 0xf8000000 1084 #define CLKD2_SWD_SHIFT 27 1085 1086 /* intstatus/intmask */ 1087 #define CI_GPIO 0x00000001 /**< gpio intr */ 1088 #define CI_EI 0x00000002 /**< extif intr (corerev >= 3) */ 1089 #define CI_TEMP 0x00000004 /**< temp. ctrl intr (corerev >= 15) */ 1090 #define CI_SIRQ 0x00000008 /**< serial IRQ intr (corerev >= 15) */ 1091 #define CI_ECI 0x00000010 /**< eci intr (corerev >= 21) */ 1092 #define CI_PMU 0x00000020 /**< pmu intr (corerev >= 21) */ 1093 #define CI_UART 0x00000040 /**< uart intr (corerev >= 21) */ 1094 #define CI_WECI 0x00000080 /* eci wakeup intr (corerev >= 21) */ 1095 #define CI_WDRESET 0x80000000 /**< watchdog reset occurred */ 1096 1097 /* slow_clk_ctl */ 1098 #define SCC_SS_MASK 0x00000007 /**< slow clock source mask */ 1099 #define SCC_SS_LPO 0x00000000 /**< source of slow clock is LPO */ 1100 #define SCC_SS_XTAL 0x00000001 /**< source of slow clock is crystal */ 1101 #define SCC_SS_PCI 0x00000002 /**< source of slow clock is PCI */ 1102 #define SCC_LF 0x00000200 /**< LPOFreqSel, 1: 160Khz, 0: 32KHz */ 1103 #define SCC_LP 0x00000400 /**< LPOPowerDown, 1: LPO is disabled, 1104 * 0: LPO is enabled 1105 */ 1106 #define SCC_FS 0x00000800 /**< ForceSlowClk, 1: sb/cores running on slow clock, 1107 * 0: power logic control 1108 */ 1109 #define SCC_IP 0x00001000 /**< IgnorePllOffReq, 1/0: power logic ignores/honors 1110 * PLL clock disable requests from core 1111 */ 1112 #define SCC_XC 0x00002000 /**< XtalControlEn, 1/0: power logic does/doesn't 1113 * disable crystal when appropriate 1114 */ 1115 #define SCC_XP 0x00004000 /**< XtalPU (RO), 1/0: crystal running/disabled */ 1116 #define SCC_CD_MASK 0xffff0000 /**< ClockDivider (SlowClk = 1/(4+divisor)) */ 1117 #define SCC_CD_SHIFT 16 1118 1119 /* system_clk_ctl */ 1120 #define SYCC_IE 0x00000001 /**< ILPen: Enable Idle Low Power */ 1121 #define SYCC_AE 0x00000002 /**< ALPen: Enable Active Low Power */ 1122 #define SYCC_FP 0x00000004 /**< ForcePLLOn */ 1123 #define SYCC_AR 0x00000008 /**< Force ALP (or HT if ALPen is not set */ 1124 #define SYCC_HR 0x00000010 /**< Force HT */ 1125 #define SYCC_CD_MASK 0xffff0000 /**< ClkDiv (ILP = 1/(4 * (divisor + 1)) */ 1126 #define SYCC_CD_SHIFT 16 1127 1128 /* watchdogcounter */ 1129 /* WL sub-system reset */ 1130 #define WD_SSRESET_PCIE_F0_EN 0x10000000 1131 /* BT sub-system reset */ 1132 #define WD_SSRESET_PCIE_F1_EN 0x20000000 1133 #define WD_SSRESET_PCIE_F2_EN 0x40000000 1134 /* Both WL and BT sub-system reset */ 1135 #define WD_SSRESET_PCIE_ALL_FN_EN 0x80000000 1136 #define WD_COUNTER_MASK 0x0fffffff 1137 #define WD_ENABLE_MASK \ 1138 (WD_SSRESET_PCIE_F0_EN | WD_SSRESET_PCIE_F1_EN | \ 1139 WD_SSRESET_PCIE_F2_EN | WD_SSRESET_PCIE_ALL_FN_EN) 1140 1141 /* Indirect backplane access */ 1142 #define BPIA_BYTEEN 0x0000000f 1143 #define BPIA_SZ1 0x00000001 1144 #define BPIA_SZ2 0x00000003 1145 #define BPIA_SZ4 0x00000007 1146 #define BPIA_SZ8 0x0000000f 1147 #define BPIA_WRITE 0x00000100 1148 #define BPIA_START 0x00000200 1149 #define BPIA_BUSY 0x00000200 1150 #define BPIA_ERROR 0x00000400 1151 1152 /* pcmcia/prog/flash_config */ 1153 #define CF_EN 0x00000001 /**< enable */ 1154 #define CF_EM_MASK 0x0000000e /**< mode */ 1155 #define CF_EM_SHIFT 1 1156 #define CF_EM_FLASH 0 /**< flash/asynchronous mode */ 1157 #define CF_EM_SYNC 2 /**< synchronous mode */ 1158 #define CF_EM_PCMCIA 4 /**< pcmcia mode */ 1159 #define CF_DS 0x00000010 /**< destsize: 0=8bit, 1=16bit */ 1160 #define CF_BS 0x00000020 /**< byteswap */ 1161 #define CF_CD_MASK 0x000000c0 /**< clock divider */ 1162 #define CF_CD_SHIFT 6 1163 #define CF_CD_DIV2 0x00000000 /**< backplane/2 */ 1164 #define CF_CD_DIV3 0x00000040 /**< backplane/3 */ 1165 #define CF_CD_DIV4 0x00000080 /**< backplane/4 */ 1166 #define CF_CE 0x00000100 /**< clock enable */ 1167 #define CF_SB 0x00000200 /**< size/bytestrobe (synch only) */ 1168 1169 /* pcmcia_memwait */ 1170 #define PM_W0_MASK 0x0000003f /**< waitcount0 */ 1171 #define PM_W1_MASK 0x00001f00 /**< waitcount1 */ 1172 #define PM_W1_SHIFT 8 1173 #define PM_W2_MASK 0x001f0000 /**< waitcount2 */ 1174 #define PM_W2_SHIFT 16 1175 #define PM_W3_MASK 0x1f000000 /**< waitcount3 */ 1176 #define PM_W3_SHIFT 24 1177 1178 /* pcmcia_attrwait */ 1179 #define PA_W0_MASK 0x0000003f /**< waitcount0 */ 1180 #define PA_W1_MASK 0x00001f00 /**< waitcount1 */ 1181 #define PA_W1_SHIFT 8 1182 #define PA_W2_MASK 0x001f0000 /**< waitcount2 */ 1183 #define PA_W2_SHIFT 16 1184 #define PA_W3_MASK 0x1f000000 /**< waitcount3 */ 1185 #define PA_W3_SHIFT 24 1186 1187 /* pcmcia_iowait */ 1188 #define PI_W0_MASK 0x0000003f /**< waitcount0 */ 1189 #define PI_W1_MASK 0x00001f00 /**< waitcount1 */ 1190 #define PI_W1_SHIFT 8 1191 #define PI_W2_MASK 0x001f0000 /**< waitcount2 */ 1192 #define PI_W2_SHIFT 16 1193 #define PI_W3_MASK 0x1f000000 /**< waitcount3 */ 1194 #define PI_W3_SHIFT 24 1195 1196 /* prog_waitcount */ 1197 #define PW_W0_MASK 0x0000001f /**< waitcount0 */ 1198 #define PW_W1_MASK 0x00001f00 /**< waitcount1 */ 1199 #define PW_W1_SHIFT 8 1200 #define PW_W2_MASK 0x001f0000 /**< waitcount2 */ 1201 #define PW_W2_SHIFT 16 1202 #define PW_W3_MASK 0x1f000000 /**< waitcount3 */ 1203 #define PW_W3_SHIFT 24 1204 1205 #define PW_W0 0x0000000c 1206 #define PW_W1 0x00000a00 1207 #define PW_W2 0x00020000 1208 #define PW_W3 0x01000000 1209 1210 /* flash_waitcount */ 1211 #define FW_W0_MASK 0x0000003f /**< waitcount0 */ 1212 #define FW_W1_MASK 0x00001f00 /**< waitcount1 */ 1213 #define FW_W1_SHIFT 8 1214 #define FW_W2_MASK 0x001f0000 /**< waitcount2 */ 1215 #define FW_W2_SHIFT 16 1216 #define FW_W3_MASK 0x1f000000 /**< waitcount3 */ 1217 #define FW_W3_SHIFT 24 1218 1219 /* When Srom support present, fields in sromcontrol */ 1220 #define SRC_START 0x80000000 1221 #define SRC_BUSY 0x80000000 1222 #define SRC_OPCODE 0x60000000 1223 #define SRC_OP_READ 0x00000000 1224 #define SRC_OP_WRITE 0x20000000 1225 #define SRC_OP_WRDIS 0x40000000 1226 #define SRC_OP_WREN 0x60000000 1227 #define SRC_OTPSEL 0x00000010 1228 #define SRC_OTPPRESENT 0x00000020 1229 #define SRC_LOCK 0x00000008 1230 #define SRC_SIZE_MASK 0x00000006 1231 #define SRC_SIZE_1K 0x00000000 1232 #define SRC_SIZE_4K 0x00000002 1233 #define SRC_SIZE_16K 0x00000004 1234 #define SRC_SIZE_SHIFT 1 1235 #define SRC_PRESENT 0x00000001 1236 1237 /* Fields in pmucontrol */ 1238 #define PCTL_ILP_DIV_MASK 0xffff0000 1239 #define PCTL_ILP_DIV_SHIFT 16 1240 #define PCTL_LQ_REQ_EN 0x00008000 1241 #define PCTL_PLL_PLLCTL_UPD 0x00000400 /**< rev 2 */ 1242 #define PCTL_NOILP_ON_WAIT 0x00000200 /**< rev 1 */ 1243 #define PCTL_HT_REQ_EN 0x00000100 1244 #define PCTL_ALP_REQ_EN 0x00000080 1245 #define PCTL_XTALFREQ_MASK 0x0000007c 1246 #define PCTL_XTALFREQ_SHIFT 2 1247 #define PCTL_ILP_DIV_EN 0x00000002 1248 #define PCTL_LPO_SEL 0x00000001 1249 1250 /* Fields in pmucontrol_ext */ 1251 #define PCTL_EXT_USE_LHL_TIMER 0x00000010 1252 #define PCTL_EXT_FASTLPO_ENAB 0x00000080 1253 #define PCTL_EXT_FASTLPO_SWENAB 0x00000200 1254 #define PCTL_EXT_FASTSEQ_ENAB 0x00001000 1255 #define PCTL_EXT_FASTLPO_PCIE_SWENAB 0x00004000 /**< rev33 for FLL1M */ 1256 1257 #define DEFAULT_43012_MIN_RES_MASK 0x0f8bfe77 1258 1259 /* Retention Control */ 1260 #define PMU_RCTL_CLK_DIV_SHIFT 0 1261 #define PMU_RCTL_CHAIN_LEN_SHIFT 12 1262 #define PMU_RCTL_MACPHY_DISABLE_SHIFT 26 1263 #define PMU_RCTL_MACPHY_DISABLE_MASK (1 << 26) 1264 #define PMU_RCTL_LOGIC_DISABLE_SHIFT 27 1265 #define PMU_RCTL_LOGIC_DISABLE_MASK (1 << 27) 1266 #define PMU_RCTL_MEMSLP_LOG_SHIFT 28 1267 #define PMU_RCTL_MEMSLP_LOG_MASK (1 << 28) 1268 #define PMU_RCTL_MEMRETSLP_LOG_SHIFT 29 1269 #define PMU_RCTL_MEMRETSLP_LOG_MASK (1 << 29) 1270 1271 /* Retention Group Control */ 1272 #define PMU_RCTLGRP_CHAIN_LEN_SHIFT 0 1273 #define PMU_RCTLGRP_RMODE_ENABLE_SHIFT 14 1274 #define PMU_RCTLGRP_RMODE_ENABLE_MASK (1 << 14) 1275 #define PMU_RCTLGRP_DFT_ENABLE_SHIFT 15 1276 #define PMU_RCTLGRP_DFT_ENABLE_MASK (1 << 15) 1277 #define PMU_RCTLGRP_NSRST_DISABLE_SHIFT 16 1278 #define PMU_RCTLGRP_NSRST_DISABLE_MASK (1 << 16) 1279 1280 /* Fields in clkstretch */ 1281 #define CSTRETCH_HT 0xffff0000 1282 #define CSTRETCH_ALP 0x0000ffff 1283 #define CSTRETCH_REDUCE_8 0x00080008 1284 1285 /* gpiotimerval */ 1286 #define GPIO_ONTIME_SHIFT 16 1287 1288 /* clockcontrol_n */ 1289 #define CN_N1_MASK 0x3f /**< n1 control */ 1290 #define CN_N2_MASK 0x3f00 /**< n2 control */ 1291 #define CN_N2_SHIFT 8 1292 #define CN_PLLC_MASK 0xf0000 /**< pll control */ 1293 #define CN_PLLC_SHIFT 16 1294 1295 /* clockcontrol_sb/pci/uart */ 1296 #define CC_M1_MASK 0x3f /**< m1 control */ 1297 #define CC_M2_MASK 0x3f00 /**< m2 control */ 1298 #define CC_M2_SHIFT 8 1299 #define CC_M3_MASK 0x3f0000 /**< m3 control */ 1300 #define CC_M3_SHIFT 16 1301 #define CC_MC_MASK 0x1f000000 /**< mux control */ 1302 #define CC_MC_SHIFT 24 1303 1304 /* N3M Clock control magic field values */ 1305 #define CC_F6_2 0x02 /**< A factor of 2 in */ 1306 #define CC_F6_3 0x03 /**< 6-bit fields like */ 1307 #define CC_F6_4 0x05 /**< N1, M1 or M3 */ 1308 #define CC_F6_5 0x09 1309 #define CC_F6_6 0x11 1310 #define CC_F6_7 0x21 1311 1312 #define CC_F5_BIAS 5 /**< 5-bit fields get this added */ 1313 1314 #define CC_MC_BYPASS 0x08 1315 #define CC_MC_M1 0x04 1316 #define CC_MC_M1M2 0x02 1317 #define CC_MC_M1M2M3 0x01 1318 #define CC_MC_M1M3 0x11 1319 1320 /* Type 2 Clock control magic field values */ 1321 #define CC_T2_BIAS 2 /**< n1, n2, m1 & m3 bias */ 1322 #define CC_T2M2_BIAS 3 /**< m2 bias */ 1323 1324 #define CC_T2MC_M1BYP 1 1325 #define CC_T2MC_M2BYP 2 1326 #define CC_T2MC_M3BYP 4 1327 1328 /* Type 6 Clock control magic field values */ 1329 #define CC_T6_MMASK 1 /**< bits of interest in m */ 1330 #define CC_T6_M0 120000000 /**< sb clock for m = 0 */ 1331 #define CC_T6_M1 100000000 /**< sb clock for m = 1 */ 1332 #define SB2MIPS_T6(sb) (2 * (sb)) 1333 1334 /* Common clock base */ 1335 #define CC_CLOCK_BASE1 24000000 /**< Half the clock freq */ 1336 #define CC_CLOCK_BASE2 12500000 /**< Alternate crystal on some PLLs */ 1337 1338 /* Clock control values for 200MHz in 5350 */ 1339 #define CLKC_5350_N 0x0311 1340 #define CLKC_5350_M 0x04020009 1341 1342 /* Flash types in the chipcommon capabilities register */ 1343 #define FLASH_NONE 0x000 /**< No flash */ 1344 #define SFLASH_ST 0x100 /**< ST serial flash */ 1345 #define SFLASH_AT 0x200 /**< Atmel serial flash */ 1346 #define NFLASH 0x300 1347 #define PFLASH 0x700 /**< Parallel flash */ 1348 #define QSPIFLASH_ST 0x800 1349 #define QSPIFLASH_AT 0x900 1350 1351 /* Bits in the ExtBus config registers */ 1352 #define CC_CFG_EN 0x0001 /**< Enable */ 1353 #define CC_CFG_EM_MASK 0x000e /**< Extif Mode */ 1354 #define CC_CFG_EM_ASYNC 0x0000 /**< Async/Parallel flash */ 1355 #define CC_CFG_EM_SYNC 0x0002 /**< Synchronous */ 1356 #define CC_CFG_EM_PCMCIA 0x0004 /**< PCMCIA */ 1357 #define CC_CFG_EM_IDE 0x0006 /**< IDE */ 1358 #define CC_CFG_DS 0x0010 /**< Data size, 0=8bit, 1=16bit */ 1359 #define CC_CFG_CD_MASK 0x00e0 /**< Sync: Clock divisor, rev >= 20 */ 1360 #define CC_CFG_CE 0x0100 /**< Sync: Clock enable, rev >= 20 */ 1361 #define CC_CFG_SB 0x0200 /**< Sync: Size/Bytestrobe, rev >= 20 */ 1362 #define CC_CFG_IS 0x0400 /**< Extif Sync Clk Select, rev >= 20 */ 1363 1364 /* ExtBus address space */ 1365 #define CC_EB_BASE 0x1a000000 /**< Chipc ExtBus base address */ 1366 #define CC_EB_PCMCIA_MEM 0x1a000000 /**< PCMCIA 0 memory base address */ 1367 #define CC_EB_PCMCIA_IO 0x1a200000 /**< PCMCIA 0 I/O base address */ 1368 #define CC_EB_PCMCIA_CFG 0x1a400000 /**< PCMCIA 0 config base address */ 1369 #define CC_EB_IDE 0x1a800000 /**< IDE memory base */ 1370 #define CC_EB_PCMCIA1_MEM 0x1a800000 /**< PCMCIA 1 memory base address */ 1371 #define CC_EB_PCMCIA1_IO 0x1aa00000 /**< PCMCIA 1 I/O base address */ 1372 #define CC_EB_PCMCIA1_CFG 0x1ac00000 /**< PCMCIA 1 config base address */ 1373 #define CC_EB_PROGIF 0x1b000000 /**< ProgIF Async/Sync base address */ 1374 1375 /* Start/busy bit in flashcontrol */ 1376 #define SFLASH_OPCODE 0x000000ff 1377 #define SFLASH_ACTION 0x00000700 1378 #define SFLASH_CS_ACTIVE 0x00001000 /**< Chip Select Active, rev >= 20 */ 1379 #define SFLASH_START 0x80000000 1380 #define SFLASH_BUSY SFLASH_START 1381 1382 /* flashcontrol action codes */ 1383 #define SFLASH_ACT_OPONLY 0x0000 /**< Issue opcode only */ 1384 #define SFLASH_ACT_OP1D 0x0100 /**< opcode + 1 data byte */ 1385 #define SFLASH_ACT_OP3A 0x0200 /**< opcode + 3 addr bytes */ 1386 #define SFLASH_ACT_OP3A1D 0x0300 /**< opcode + 3 addr & 1 data bytes */ 1387 #define SFLASH_ACT_OP3A4D 0x0400 /**< opcode + 3 addr & 4 data bytes */ 1388 #define SFLASH_ACT_OP3A4X4D 0x0500 /**< opcode + 3 addr, 4 don't care & 4 data bytes */ 1389 #define SFLASH_ACT_OP3A1X4D 0x0700 /**< opcode + 3 addr, 1 don't care & 4 data bytes */ 1390 1391 /* flashcontrol action+opcodes for ST flashes */ 1392 #define SFLASH_ST_WREN 0x0006 /**< Write Enable */ 1393 #define SFLASH_ST_WRDIS 0x0004 /**< Write Disable */ 1394 #define SFLASH_ST_RDSR 0x0105 /**< Read Status Register */ 1395 #define SFLASH_ST_WRSR 0x0101 /**< Write Status Register */ 1396 #define SFLASH_ST_READ 0x0303 /**< Read Data Bytes */ 1397 #define SFLASH_ST_PP 0x0302 /**< Page Program */ 1398 #define SFLASH_ST_SE 0x02d8 /**< Sector Erase */ 1399 #define SFLASH_ST_BE 0x00c7 /**< Bulk Erase */ 1400 #define SFLASH_ST_DP 0x00b9 /**< Deep Power-down */ 1401 #define SFLASH_ST_RES 0x03ab /**< Read Electronic Signature */ 1402 #define SFLASH_ST_CSA 0x1000 /**< Keep chip select asserted */ 1403 #define SFLASH_ST_SSE 0x0220 /**< Sub-sector Erase */ 1404 1405 #define SFLASH_ST_READ4B 0x6313 /* Read Data Bytes in 4Byte address */ 1406 #define SFLASH_ST_PP4B 0x6312 /* Page Program in 4Byte address */ 1407 #define SFLASH_ST_SE4B 0x62dc /* Sector Erase in 4Byte address */ 1408 #define SFLASH_ST_SSE4B 0x6221 /* Sub-sector Erase */ 1409 1410 #define SFLASH_MXIC_RDID 0x0390 /* Read Manufacture ID */ 1411 #define SFLASH_MXIC_MFID 0xc2 /* MXIC Manufacture ID */ 1412 1413 /* Status register bits for ST flashes */ 1414 #define SFLASH_ST_WIP 0x01 /**< Write In Progress */ 1415 #define SFLASH_ST_WEL 0x02 /**< Write Enable Latch */ 1416 #define SFLASH_ST_BP_MASK 0x1c /**< Block Protect */ 1417 #define SFLASH_ST_BP_SHIFT 2 1418 #define SFLASH_ST_SRWD 0x80 /**< Status Register Write Disable */ 1419 1420 /* flashcontrol action+opcodes for Atmel flashes */ 1421 #define SFLASH_AT_READ 0x07e8 1422 #define SFLASH_AT_PAGE_READ 0x07d2 1423 #define SFLASH_AT_BUF1_READ 1424 #define SFLASH_AT_BUF2_READ 1425 #define SFLASH_AT_STATUS 0x01d7 1426 #define SFLASH_AT_BUF1_WRITE 0x0384 1427 #define SFLASH_AT_BUF2_WRITE 0x0387 1428 #define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 1429 #define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 1430 #define SFLASH_AT_BUF1_PROGRAM 0x0288 1431 #define SFLASH_AT_BUF2_PROGRAM 0x0289 1432 #define SFLASH_AT_PAGE_ERASE 0x0281 1433 #define SFLASH_AT_BLOCK_ERASE 0x0250 1434 #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 1435 #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 1436 #define SFLASH_AT_BUF1_LOAD 0x0253 1437 #define SFLASH_AT_BUF2_LOAD 0x0255 1438 #define SFLASH_AT_BUF1_COMPARE 0x0260 1439 #define SFLASH_AT_BUF2_COMPARE 0x0261 1440 #define SFLASH_AT_BUF1_REPROGRAM 0x0258 1441 #define SFLASH_AT_BUF2_REPROGRAM 0x0259 1442 1443 /* Status register bits for Atmel flashes */ 1444 #define SFLASH_AT_READY 0x80 1445 #define SFLASH_AT_MISMATCH 0x40 1446 #define SFLASH_AT_ID_MASK 0x38 1447 #define SFLASH_AT_ID_SHIFT 3 1448 1449 /* SPI register bits, corerev >= 37 */ 1450 #define GSIO_START 0x80000000 1451 #define GSIO_BUSY GSIO_START 1452 1453 /* GCI UART Function sel related */ 1454 #define MUXENAB_GCI_UART_MASK (0x00000f00) 1455 #define MUXENAB_GCI_UART_SHIFT 8 1456 #define MUXENAB_GCI_UART_FNSEL_MASK (0x00003000) 1457 #define MUXENAB_GCI_UART_FNSEL_SHIFT 12 1458 1459 /* 1460 * These are the UART port assignments, expressed as offsets from the base 1461 * register. These assignments should hold for any serial port based on 1462 * a 8250, 16450, or 16550(A). 1463 */ 1464 1465 #define UART_RX 0 /**< In: Receive buffer (DLAB=0) */ 1466 #define UART_TX 0 /**< Out: Transmit buffer (DLAB=0) */ 1467 #define UART_DLL 0 /**< Out: Divisor Latch Low (DLAB=1) */ 1468 #define UART_IER 1 /**< In/Out: Interrupt Enable Register (DLAB=0) */ 1469 #define UART_DLM 1 /**< Out: Divisor Latch High (DLAB=1) */ 1470 #define UART_IIR 2 /**< In: Interrupt Identity Register */ 1471 #define UART_FCR 2 /**< Out: FIFO Control Register */ 1472 #define UART_LCR 3 /**< Out: Line Control Register */ 1473 #define UART_MCR 4 /**< Out: Modem Control Register */ 1474 #define UART_LSR 5 /**< In: Line Status Register */ 1475 #define UART_MSR 6 /**< In: Modem Status Register */ 1476 #define UART_SCR 7 /**< I/O: Scratch Register */ 1477 #define UART_LCR_DLAB 0x80 /**< Divisor latch access bit */ 1478 #define UART_LCR_WLEN8 0x03 /**< Word length: 8 bits */ 1479 #define UART_MCR_OUT2 0x08 /**< MCR GPIO out 2 */ 1480 #define UART_MCR_LOOP 0x10 /**< Enable loopback test mode */ 1481 #define UART_LSR_RX_FIFO 0x80 /**< Receive FIFO error */ 1482 #define UART_LSR_TDHR 0x40 /**< Data-hold-register empty */ 1483 #define UART_LSR_THRE 0x20 /**< Transmit-hold-register empty */ 1484 #define UART_LSR_BREAK 0x10 /**< Break interrupt */ 1485 #define UART_LSR_FRAMING 0x08 /**< Framing error */ 1486 #define UART_LSR_PARITY 0x04 /**< Parity error */ 1487 #define UART_LSR_OVERRUN 0x02 /**< Overrun error */ 1488 #define UART_LSR_RXRDY 0x01 /**< Receiver ready */ 1489 #define UART_FCR_FIFO_ENABLE 1 /**< FIFO control register bit controlling FIFO enable/disable */ 1490 1491 /* Interrupt Identity Register (IIR) bits */ 1492 #define UART_IIR_FIFO_MASK 0xc0 /**< IIR FIFO disable/enabled mask */ 1493 #define UART_IIR_INT_MASK 0xf /**< IIR interrupt ID source */ 1494 #define UART_IIR_MDM_CHG 0x0 /**< Modem status changed */ 1495 #define UART_IIR_NOINT 0x1 /**< No interrupt pending */ 1496 #define UART_IIR_THRE 0x2 /**< THR empty */ 1497 #define UART_IIR_RCVD_DATA 0x4 /**< Received data available */ 1498 #define UART_IIR_RCVR_STATUS 0x6 /**< Receiver status */ 1499 #define UART_IIR_CHAR_TIME 0xc /**< Character time */ 1500 1501 /* Interrupt Enable Register (IER) bits */ 1502 #define UART_IER_PTIME 128 /**< Programmable THRE Interrupt Mode Enable */ 1503 #define UART_IER_EDSSI 8 /**< enable modem status interrupt */ 1504 #define UART_IER_ELSI 4 /**< enable receiver line status interrupt */ 1505 #define UART_IER_ETBEI 2 /**< enable transmitter holding register empty interrupt */ 1506 #define UART_IER_ERBFI 1 /**< enable data available interrupt */ 1507 1508 /* pmustatus */ 1509 #define PST_SLOW_WR_PENDING 0x0400 1510 #define PST_EXTLPOAVAIL 0x0100 1511 #define PST_WDRESET 0x0080 1512 #define PST_INTPEND 0x0040 1513 #define PST_SBCLKST 0x0030 1514 #define PST_SBCLKST_ILP 0x0010 1515 #define PST_SBCLKST_ALP 0x0020 1516 #define PST_SBCLKST_HT 0x0030 1517 #define PST_ALPAVAIL 0x0008 1518 #define PST_HTAVAIL 0x0004 1519 #define PST_RESINIT 0x0003 1520 #define PST_ILPFASTLPO 0x00010000 1521 1522 /* pmucapabilities */ 1523 #define PCAP_REV_MASK 0x000000ff 1524 #define PCAP_RC_MASK 0x00001f00 1525 #define PCAP_RC_SHIFT 8 1526 #define PCAP_TC_MASK 0x0001e000 1527 #define PCAP_TC_SHIFT 13 1528 #define PCAP_PC_MASK 0x001e0000 1529 #define PCAP_PC_SHIFT 17 1530 #define PCAP_VC_MASK 0x01e00000 1531 #define PCAP_VC_SHIFT 21 1532 #define PCAP_CC_MASK 0x1e000000 1533 #define PCAP_CC_SHIFT 25 1534 #define PCAP5_PC_MASK 0x003e0000 /**< PMU corerev >= 5 */ 1535 #define PCAP5_PC_SHIFT 17 1536 #define PCAP5_VC_MASK 0x07c00000 1537 #define PCAP5_VC_SHIFT 22 1538 #define PCAP5_CC_MASK 0xf8000000 1539 #define PCAP5_CC_SHIFT 27 1540 1541 /* pmucapabilities ext */ 1542 #define PCAP_EXT_ST_NUM_SHIFT (8) /* stat timer number */ 1543 #define PCAP_EXT_ST_NUM_MASK (0xf << PCAP_EXT_ST_NUM_SHIFT) 1544 #define PCAP_EXT_ST_SRC_NUM_SHIFT (12) /* stat timer source number */ 1545 #define PCAP_EXT_ST_SRC_NUM_MASK (0xf << PCAP_EXT_ST_SRC_NUM_SHIFT) 1546 1547 /* pmustattimer ctrl */ 1548 #define PMU_ST_SRC_SHIFT (0) /* stat timer source number */ 1549 #define PMU_ST_SRC_MASK (0xff << PMU_ST_SRC_SHIFT) 1550 #define PMU_ST_CNT_MODE_SHIFT (10) /* stat timer count mode */ 1551 #define PMU_ST_CNT_MODE_MASK (0x3 << PMU_ST_CNT_MODE_SHIFT) 1552 #define PMU_ST_EN_SHIFT (8) /* stat timer enable */ 1553 #define PMU_ST_EN_MASK (0x1 << PMU_ST_EN_SHIFT) 1554 #define PMU_ST_ENAB 1 1555 #define PMU_ST_DISAB 0 1556 #define PMU_ST_INT_EN_SHIFT (9) /* stat timer enable */ 1557 #define PMU_ST_INT_EN_MASK (0x1 << PMU_ST_INT_EN_SHIFT) 1558 #define PMU_ST_INT_ENAB 1 1559 #define PMU_ST_INT_DISAB 0 1560 1561 /* CoreCapabilitiesExtension */ 1562 #define PCAP_EXT_USE_MUXED_ILP_CLK_MASK 0x04000000 1563 1564 /* PMU Resource Request Timer registers */ 1565 /* This is based on PmuRev0 */ 1566 #define PRRT_TIME_MASK 0x03ff 1567 #define PRRT_INTEN 0x0400 1568 /* ReqActive 25 1569 * The hardware sets this field to 1 when the timer expires. 1570 * Software writes this field to 1 to make immediate resource requests. 1571 */ 1572 #define PRRT_REQ_ACTIVE 0x0800 /* To check h/w status */ 1573 #define PRRT_IMMEDIATE_RES_REQ 0x0800 /* macro for sw immediate res req */ 1574 #define PRRT_ALP_REQ 0x1000 1575 #define PRRT_HT_REQ 0x2000 1576 #define PRRT_HQ_REQ 0x4000 1577 1578 /* PMU Int Control register bits */ 1579 #define PMU_INTC_ALP_REQ 0x1 1580 #define PMU_INTC_HT_REQ 0x2 1581 #define PMU_INTC_HQ_REQ 0x4 1582 1583 /* bit 0 of the PMU interrupt vector is asserted if this mask is enabled */ 1584 #define RSRC_INTR_MASK_TIMER_INT_0 1 1585 #define PMU_INTR_MASK_EXTWAKE_REQ_ACTIVE_0 (1 << 20) 1586 1587 /* bit 16 of the PMU interrupt vector - Stats Timer Interrupt */ 1588 #define PMU_INT_STAT_TIMER_INT_SHIFT 16 1589 #define PMU_INT_STAT_TIMER_INT_MASK (1 << PMU_INT_STAT_TIMER_INT_SHIFT) 1590 1591 /* PMU resource bit position */ 1592 #define PMURES_BIT(bit) (1 << (bit)) 1593 1594 /* PMU resource number limit */ 1595 #define PMURES_MAX_RESNUM 30 1596 1597 /* PMU chip control0 register */ 1598 #define PMU_CHIPCTL0 0 1599 1600 #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_START_VAL (0x20 << 0) 1601 #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3F << 0) 1602 #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0xF << 6) 1603 #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3F << 6) 1604 #define PMU_CC0_4369_XTAL_RES_BYPASS_START_VAL (0 << 12) 1605 #define PMU_CC0_4369_XTAL_RES_BYPASS_START_MASK (0x7 << 12) 1606 #define PMU_CC0_4369_XTAL_RES_BYPASS_NORMAL_VAL (0x1 << 15) 1607 #define PMU_CC0_4369_XTAL_RES_BYPASS_NORMAL_MASK (0x7 << 15) 1608 1609 /* clock req types */ 1610 #define PMU_CC1_CLKREQ_TYPE_SHIFT 19 1611 #define PMU_CC1_CLKREQ_TYPE_MASK (1 << PMU_CC1_CLKREQ_TYPE_SHIFT) 1612 1613 #define CLKREQ_TYPE_CONFIG_OPENDRAIN 0 1614 #define CLKREQ_TYPE_CONFIG_PUSHPULL 1 1615 1616 /* Power Control */ 1617 #define PWRCTL_ENAB_MEM_CLK_GATE_SHIFT 5 1618 #define PWRCTL_AUTO_MEM_STBYRET 28 1619 1620 /* PMU chip control1 register */ 1621 #define PMU_CHIPCTL1 1 1622 #define PMU_CC1_RXC_DLL_BYPASS 0x00010000 1623 #define PMU_CC1_ENABLE_BBPLL_PWR_DOWN 0x00000010 1624 1625 #define PMU_CC1_IF_TYPE_MASK 0x00000030 1626 #define PMU_CC1_IF_TYPE_RMII 0x00000000 1627 #define PMU_CC1_IF_TYPE_MII 0x00000010 1628 #define PMU_CC1_IF_TYPE_RGMII 0x00000020 1629 1630 #define PMU_CC1_SW_TYPE_MASK 0x000000c0 1631 #define PMU_CC1_SW_TYPE_EPHY 0x00000000 1632 #define PMU_CC1_SW_TYPE_EPHYMII 0x00000040 1633 #define PMU_CC1_SW_TYPE_EPHYRMII 0x00000080 1634 #define PMU_CC1_SW_TYPE_RGMII 0x000000c0 1635 1636 #define PMU_CC1_ENABLE_CLOSED_LOOP_MASK 0x00000080 1637 #define PMU_CC1_ENABLE_CLOSED_LOOP 0x00000000 1638 1639 #define PMU_CC1_PWRSW_CLKSTRSTP_DELAY_MASK 0x00003F00u 1640 #define PMU_CC1_PWRSW_CLKSTRSTP_DELAY 0x00000400u 1641 1642 /* PMU chip control2 register */ 1643 #define PMU_CC2_RFLDO3P3_PU_FORCE_ON (1 << 15) 1644 #define PMU_CC2_RFLDO3P3_PU_CLEAR 0x00000000 1645 1646 #define PMU_CC2_WL2CDIG_I_PMU_SLEEP (1 << 16) 1647 #define PMU_CHIPCTL2 2 1648 #define PMU_CC2_FORCE_SUBCORE_PWR_SWITCH_ON (1 << 18) 1649 #define PMU_CC2_FORCE_PHY_PWR_SWITCH_ON (1 << 19) 1650 #define PMU_CC2_FORCE_VDDM_PWR_SWITCH_ON (1 << 20) 1651 #define PMU_CC2_FORCE_MEMLPLDO_PWR_SWITCH_ON (1 << 21) 1652 #define PMU_CC2_MASK_WL_DEV_WAKE (1 << 22) 1653 #define PMU_CC2_INV_GPIO_POLARITY_PMU_WAKE (1 << 25) 1654 #define PMU_CC2_GCI2_WAKE (1 << 31) 1655 1656 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3 << 26) 1657 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3 << 26) 1658 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0 << 28) 1659 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3 << 28) 1660 1661 /* PMU chip control3 register */ 1662 #define PMU_CHIPCTL3 3 1663 #define PMU_CC3_ENABLE_SDIO_WAKEUP_SHIFT 19 1664 #define PMU_CC3_ENABLE_RF_SHIFT 22 1665 #define PMU_CC3_RF_DISABLE_IVALUE_SHIFT 23 1666 1667 #define PMU_CC3_4369_XTALCORESIZE_PMOS_START_VAL (0x3F << 0) 1668 #define PMU_CC3_4369_XTALCORESIZE_PMOS_START_MASK (0x3F << 0) 1669 #define PMU_CC3_4369_XTALCORESIZE_PMOS_NORMAL_VAL (0x3F << 15) 1670 #define PMU_CC3_4369_XTALCORESIZE_PMOS_NORMAL_MASK (0x3F << 15) 1671 #define PMU_CC3_4369_XTALCORESIZE_NMOS_START_VAL (0x3F << 6) 1672 #define PMU_CC3_4369_XTALCORESIZE_NMOS_START_MASK (0x3F << 6) 1673 #define PMU_CC3_4369_XTALCORESIZE_NMOS_NORMAL_VAL (0x3F << 21) 1674 #define PMU_CC3_4369_XTALCORESIZE_NMOS_NORMAL_MASK (0x3F << 21) 1675 #define PMU_CC3_4369_XTALSEL_BIAS_RES_START_VAL (0x2 << 12) 1676 #define PMU_CC3_4369_XTALSEL_BIAS_RES_START_MASK (0x7 << 12) 1677 #define PMU_CC3_4369_XTALSEL_BIAS_RES_NORMAL_VAL (0x6 << 27) 1678 #define PMU_CC3_4369_XTALSEL_BIAS_RES_NORMAL_MASK (0x7 << 27) 1679 1680 /* PMU chip control4 register */ 1681 #define PMU_CHIPCTL4 4 1682 1683 /* 53537 series moved switch_type and gmac_if_type to CC4 [15:14] and [13:12] */ 1684 #define PMU_CC4_IF_TYPE_MASK 0x00003000 1685 #define PMU_CC4_IF_TYPE_RMII 0x00000000 1686 #define PMU_CC4_IF_TYPE_MII 0x00001000 1687 #define PMU_CC4_IF_TYPE_RGMII 0x00002000 1688 1689 #define PMU_CC4_SW_TYPE_MASK 0x0000c000 1690 #define PMU_CC4_SW_TYPE_EPHY 0x00000000 1691 #define PMU_CC4_SW_TYPE_EPHYMII 0x00004000 1692 #define PMU_CC4_SW_TYPE_EPHYRMII 0x00008000 1693 #define PMU_CC4_SW_TYPE_RGMII 0x0000c000 1694 #define PMU_CC4_DISABLE_LQ_AVAIL (1<<27) 1695 1696 #define PMU_CC4_4369_MAIN_PD_CBUCK2VDDB_ON (1u << 15u) 1697 #define PMU_CC4_4369_MAIN_PD_CBUCK2VDDRET_ON (1u << 16u) 1698 #define PMU_CC4_4369_MAIN_PD_MEMLPLDO2VDDB_ON (1u << 17u) 1699 #define PMU_CC4_4369_MAIN_PD_MEMLPDLO2VDDRET_ON (1u << 18u) 1700 1701 #define PMU_CC4_4369_AUX_PD_CBUCK2VDDB_ON (1u << 21u) 1702 #define PMU_CC4_4369_AUX_PD_CBUCK2VDDRET_ON (1u << 22u) 1703 #define PMU_CC4_4369_AUX_PD_MEMLPLDO2VDDB_ON (1u << 23u) 1704 #define PMU_CC4_4369_AUX_PD_MEMLPLDO2VDDRET_ON (1u << 24u) 1705 1706 /* PMU chip control5 register */ 1707 #define PMU_CHIPCTL5 5 1708 1709 #define PMU_CC5_4369_SUBCORE_CBUCK2VDDB_ON (1u << 9u) 1710 #define PMU_CC5_4369_SUBCORE_CBUCK2VDDRET_ON (1u << 10u) 1711 #define PMU_CC5_4369_SUBCORE_MEMLPLDO2VDDB_ON (1u << 11u) 1712 #define PMU_CC5_4369_SUBCORE_MEMLPLDO2VDDRET_ON (1u << 12u) 1713 1714 /* PMU chip control6 register */ 1715 #define PMU_CHIPCTL6 6 1716 #define PMU_CC6_ENABLE_CLKREQ_WAKEUP (1 << 4) 1717 #define PMU_CC6_ENABLE_PMU_WAKEUP_ALP (1 << 6) 1718 #define PMU_CC6_ENABLE_PCIE_RETENTION (1 << 12) 1719 #define PMU_CC6_ENABLE_PMU_EXT_PERST (1 << 13) 1720 #define PMU_CC6_ENABLE_PMU_WAKEUP_PERST (1 << 14) 1721 1722 /* PMU chip control7 register */ 1723 #define PMU_CHIPCTL7 7 1724 #define PMU_CC7_ENABLE_L2REFCLKPAD_PWRDWN (1 << 25) 1725 #define PMU_CC7_ENABLE_MDIO_RESET_WAR (1 << 27) 1726 /* 53537 series have gmca1 gmac_if_type in cc7 [7:6](defalut 0b01) */ 1727 #define PMU_CC7_IF_TYPE_MASK 0x000000c0 1728 #define PMU_CC7_IF_TYPE_RMII 0x00000000 1729 #define PMU_CC7_IF_TYPE_MII 0x00000040 1730 #define PMU_CC7_IF_TYPE_RGMII 0x00000080 1731 1732 #define PMU_CHIPCTL8 8 1733 #define PMU_CHIPCTL9 9 1734 1735 #define PMU_CHIPCTL10 10 1736 #define PMU_CC10_PCIE_PWRSW_RESET0_CNT_SHIFT 0 1737 #define PMU_CC10_PCIE_PWRSW_RESET0_CNT_MASK 0x000000ff 1738 #define PMU_CC10_PCIE_PWRSW_RESET1_CNT_SHIFT 8 1739 #define PMU_CC10_PCIE_PWRSW_RESET1_CNT_MASK 0x0000ff00 1740 #define PMU_CC10_PCIE_PWRSW_UP_DLY_SHIFT 16 1741 #define PMU_CC10_PCIE_PWRSW_UP_DLY_MASK 0x000f0000 1742 #define PMU_CC10_PCIE_PWRSW_FORCE_PWROK_DLY_SHIFT 20 1743 #define PMU_CC10_PCIE_PWRSW_FORCE_PWROK_DLY_MASK 0x00f00000 1744 #define PMU_CC10_FORCE_PCIE_ON (1 << 24) 1745 #define PMU_CC10_FORCE_PCIE_SW_ON (1 << 25) 1746 #define PMU_CC10_FORCE_PCIE_RETNT_ON (1 << 26) 1747 1748 #define PMU_CC10_PCIE_PWRSW_RESET_CNT_4US 1 1749 #define PMU_CC10_PCIE_PWRSW_RESET_CNT_8US 2 1750 1751 #define PMU_CC10_PCIE_PWRSW_UP_DLY_0US 0 1752 1753 #define PMU_CC10_PCIE_PWRSW_FORCE_PWROK_DLY_4US 1 1754 1755 #define PMU_CHIPCTL11 11 1756 #define PMU_CHIPCTL12 12 1757 1758 /* PMU chip control13 register */ 1759 #define PMU_CHIPCTL13 13 1760 1761 #define PMU_CC13_SUBCORE_CBUCK2VDDB_OFF (1u << 0u) 1762 #define PMU_CC13_SUBCORE_CBUCK2VDDRET_OFF (1u << 1u) 1763 #define PMU_CC13_SUBCORE_MEMLPLDO2VDDB_OFF (1u << 2u) 1764 #define PMU_CC13_SUBCORE_MEMLPLDO2VDDRET_OFF (1u << 3u) 1765 1766 #define PMU_CC13_MAIN_CBUCK2VDDB_OFF (1u << 4u) 1767 #define PMU_CC13_MAIN_CBUCK2VDDRET_OFF (1u << 5u) 1768 #define PMU_CC13_MAIN_MEMLPLDO2VDDB_OFF (1u << 6u) 1769 #define PMU_CC13_MAIN_MEMLPLDO2VDDRET_OFF (1u << 7u) 1770 1771 #define PMU_CC13_AUX_CBUCK2VDDB_OFF (1u << 8u) 1772 #define PMU_CC13_AUX_MEMLPLDO2VDDB_OFF (1u << 10u) 1773 #define PMU_CC13_AUX_MEMLPLDO2VDDRET_OFF (1u << 11u) 1774 #define PMU_CC13_AUX_CBUCK2VDDRET_OFF (1u << 12u) 1775 1776 #define PMU_CHIPCTL14 14 1777 #define PMU_CHIPCTL15 15 1778 #define PMU_CHIPCTL16 16 1779 #define PMU_CC16_CLK4M_DIS (1 << 4) 1780 #define PMU_CC16_FF_ZERO_ADJ (4 << 5) 1781 1782 /* PMU chip control14 register */ 1783 #define PMU_CC14_MAIN_VDDB2VDDRET_UP_DLY_MASK (0xF) 1784 #define PMU_CC14_MAIN_VDDB2VDD_UP_DLY_MASK (0xF << 4) 1785 #define PMU_CC14_AUX_VDDB2VDDRET_UP_DLY_MASK (0xF << 8) 1786 #define PMU_CC14_AUX_VDDB2VDD_UP_DLY_MASK (0xF << 12) 1787 #define PMU_CC14_PCIE_VDDB2VDDRET_UP_DLY_MASK (0xF << 16) 1788 #define PMU_CC14_PCIE_VDDB2VDD_UP_DLY_MASK (0xF << 20) 1789 1790 /* PMU corerev and chip specific PLL controls. 1791 * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number 1792 * to differentiate different PLLs controlled by the same PMU rev. 1793 */ 1794 /* pllcontrol registers */ 1795 /* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ 1796 #define PMU0_PLL0_PLLCTL0 0 1797 #define PMU0_PLL0_PC0_PDIV_MASK 1 1798 #define PMU0_PLL0_PC0_PDIV_FREQ 25000 1799 #define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 1800 #define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 1801 #define PMU0_PLL0_PC0_DIV_ARM_BASE 8 1802 1803 /* PC0_DIV_ARM for PLLOUT_ARM */ 1804 #define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 1805 #define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 1806 #define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 1807 #define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ 1808 #define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 1809 #define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 1810 #define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 1811 #define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 1812 1813 /* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ 1814 #define PMU0_PLL0_PLLCTL1 1 1815 #define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 1816 #define PMU0_PLL0_PC1_WILD_INT_SHIFT 28 1817 #define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 1818 #define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 1819 #define PMU0_PLL0_PC1_STOP_MOD 0x00000040 1820 1821 /* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ 1822 #define PMU0_PLL0_PLLCTL2 2 1823 #define PMU0_PLL0_PC2_WILD_INT_MASK 0xf 1824 #define PMU0_PLL0_PC2_WILD_INT_SHIFT 4 1825 1826 /* pllcontrol registers */ 1827 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 1828 #define PMU1_PLL0_PLLCTL0 0 1829 #define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 1830 #define PMU1_PLL0_PC0_P1DIV_SHIFT 20 1831 #define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 1832 #define PMU1_PLL0_PC0_P2DIV_SHIFT 24 1833 1834 /* m<x>div */ 1835 #define PMU1_PLL0_PLLCTL1 1 1836 #define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff 1837 #define PMU1_PLL0_PC1_M1DIV_SHIFT 0 1838 #define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 1839 #define PMU1_PLL0_PC1_M2DIV_SHIFT 8 1840 #define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 1841 #define PMU1_PLL0_PC1_M3DIV_SHIFT 16 1842 #define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 1843 #define PMU1_PLL0_PC1_M4DIV_SHIFT 24 1844 #define PMU1_PLL0_PC1_M4DIV_BY_9 9 1845 #define PMU1_PLL0_PC1_M4DIV_BY_18 0x12 1846 #define PMU1_PLL0_PC1_M4DIV_BY_36 0x24 1847 #define PMU1_PLL0_PC1_M4DIV_BY_60 0x3C 1848 #define PMU1_PLL0_PC1_M2_M4DIV_MASK 0xff00ff00 1849 #define PMU1_PLL0_PC1_HOLD_LOAD_CH 0x28 1850 #define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 1851 #define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 1852 #define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 1853 1854 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 1855 #define PMU1_PLL0_PLLCTL2 2 1856 #define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff 1857 #define PMU1_PLL0_PC2_M5DIV_SHIFT 0 1858 #define PMU1_PLL0_PC2_M5DIV_BY_12 0xc 1859 #define PMU1_PLL0_PC2_M5DIV_BY_18 0x12 1860 #define PMU1_PLL0_PC2_M5DIV_BY_31 0x1f 1861 #define PMU1_PLL0_PC2_M5DIV_BY_36 0x24 1862 #define PMU1_PLL0_PC2_M5DIV_BY_42 0x2a 1863 #define PMU1_PLL0_PC2_M5DIV_BY_60 0x3c 1864 #define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 1865 #define PMU1_PLL0_PC2_M6DIV_SHIFT 8 1866 #define PMU1_PLL0_PC2_M6DIV_BY_18 0x12 1867 #define PMU1_PLL0_PC2_M6DIV_BY_36 0x24 1868 #define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 1869 #define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 1870 #define PMU1_PLL0_PC2_NDIV_MODE_MASH 1 1871 #define PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /**< recommended for 4319 */ 1872 #define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 1873 #define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 1874 1875 /* ndiv_frac */ 1876 #define PMU1_PLL0_PLLCTL3 3 1877 #define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff 1878 #define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 1879 1880 /* pll_ctrl */ 1881 #define PMU1_PLL0_PLLCTL4 4 1882 1883 /* pll_ctrl, vco_rng, clkdrive_ch<x> */ 1884 #define PMU1_PLL0_PLLCTL5 5 1885 #define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 1886 #define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 1887 #define PMU1_PLL0_PC5_ASSERT_CH_MASK 0x3f000000 1888 #define PMU1_PLL0_PC5_ASSERT_CH_SHIFT 24 1889 #define PMU1_PLL0_PC5_DEASSERT_CH_MASK 0xff000000 1890 1891 #define PMU1_PLL0_PLLCTL6 6 1892 #define PMU1_PLL0_PLLCTL7 7 1893 #define PMU1_PLL0_PLLCTL8 8 1894 1895 #define PMU1_PLLCTL8_OPENLOOP_MASK (1 << 1) 1896 #define PMU_PLL4350_OPENLOOP_MASK (1 << 7) 1897 1898 #define PMU1_PLL0_PLLCTL9 9 1899 1900 #define PMU1_PLL0_PLLCTL10 10 1901 1902 /* PMU rev 2 control words */ 1903 #define PMU2_PHY_PLL_PLLCTL 4 1904 #define PMU2_SI_PLL_PLLCTL 10 1905 1906 /* PMU rev 2 */ 1907 /* pllcontrol registers */ 1908 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 1909 #define PMU2_PLL_PLLCTL0 0 1910 #define PMU2_PLL_PC0_P1DIV_MASK 0x00f00000 1911 #define PMU2_PLL_PC0_P1DIV_SHIFT 20 1912 #define PMU2_PLL_PC0_P2DIV_MASK 0x0f000000 1913 #define PMU2_PLL_PC0_P2DIV_SHIFT 24 1914 1915 /* m<x>div */ 1916 #define PMU2_PLL_PLLCTL1 1 1917 #define PMU2_PLL_PC1_M1DIV_MASK 0x000000ff 1918 #define PMU2_PLL_PC1_M1DIV_SHIFT 0 1919 #define PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00 1920 #define PMU2_PLL_PC1_M2DIV_SHIFT 8 1921 #define PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000 1922 #define PMU2_PLL_PC1_M3DIV_SHIFT 16 1923 #define PMU2_PLL_PC1_M4DIV_MASK 0xff000000 1924 #define PMU2_PLL_PC1_M4DIV_SHIFT 24 1925 1926 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 1927 #define PMU2_PLL_PLLCTL2 2 1928 #define PMU2_PLL_PC2_M5DIV_MASK 0x000000ff 1929 #define PMU2_PLL_PC2_M5DIV_SHIFT 0 1930 #define PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00 1931 #define PMU2_PLL_PC2_M6DIV_SHIFT 8 1932 #define PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000 1933 #define PMU2_PLL_PC2_NDIV_MODE_SHIFT 17 1934 #define PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000 1935 #define PMU2_PLL_PC2_NDIV_INT_SHIFT 20 1936 1937 /* ndiv_frac */ 1938 #define PMU2_PLL_PLLCTL3 3 1939 #define PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff 1940 #define PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0 1941 1942 /* pll_ctrl */ 1943 #define PMU2_PLL_PLLCTL4 4 1944 1945 /* pll_ctrl, vco_rng, clkdrive_ch<x> */ 1946 #define PMU2_PLL_PLLCTL5 5 1947 #define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00 1948 #define PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8 1949 #define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000 1950 #define PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12 1951 #define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000 1952 #define PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16 1953 #define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000 1954 #define PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20 1955 #define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000 1956 #define PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24 1957 #define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000 1958 #define PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28 1959 1960 /* PMU rev 5 (& 6) */ 1961 #define PMU5_PLL_P1P2_OFF 0 1962 #define PMU5_PLL_P1_MASK 0x0f000000 1963 #define PMU5_PLL_P1_SHIFT 24 1964 #define PMU5_PLL_P2_MASK 0x00f00000 1965 #define PMU5_PLL_P2_SHIFT 20 1966 #define PMU5_PLL_M14_OFF 1 1967 #define PMU5_PLL_MDIV_MASK 0x000000ff 1968 #define PMU5_PLL_MDIV_WIDTH 8 1969 #define PMU5_PLL_NM5_OFF 2 1970 #define PMU5_PLL_NDIV_MASK 0xfff00000 1971 #define PMU5_PLL_NDIV_SHIFT 20 1972 #define PMU5_PLL_NDIV_MODE_MASK 0x000e0000 1973 #define PMU5_PLL_NDIV_MODE_SHIFT 17 1974 #define PMU5_PLL_FMAB_OFF 3 1975 #define PMU5_PLL_MRAT_MASK 0xf0000000 1976 #define PMU5_PLL_MRAT_SHIFT 28 1977 #define PMU5_PLL_ABRAT_MASK 0x08000000 1978 #define PMU5_PLL_ABRAT_SHIFT 27 1979 #define PMU5_PLL_FDIV_MASK 0x07ffffff 1980 #define PMU5_PLL_PLLCTL_OFF 4 1981 #define PMU5_PLL_PCHI_OFF 5 1982 #define PMU5_PLL_PCHI_MASK 0x0000003f 1983 1984 /* pmu XtalFreqRatio */ 1985 #define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF 1986 #define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000 1987 #define PMU_XTALFREQ_REG_MEASURE_SHIFT 31 1988 1989 /* Divider allocation in 4716/47162/5356/5357 */ 1990 #define PMU5_MAINPLL_CPU 1 1991 #define PMU5_MAINPLL_MEM 2 1992 #define PMU5_MAINPLL_SI 3 1993 1994 #define PMU7_PLL_PLLCTL7 7 1995 #define PMU7_PLL_CTL7_M4DIV_MASK 0xff000000 1996 #define PMU7_PLL_CTL7_M4DIV_SHIFT 24 1997 #define PMU7_PLL_CTL7_M4DIV_BY_6 6 1998 #define PMU7_PLL_CTL7_M4DIV_BY_12 0xc 1999 #define PMU7_PLL_CTL7_M4DIV_BY_24 0x18 2000 #define PMU7_PLL_PLLCTL8 8 2001 #define PMU7_PLL_CTL8_M5DIV_MASK 0x000000ff 2002 #define PMU7_PLL_CTL8_M5DIV_SHIFT 0 2003 #define PMU7_PLL_CTL8_M5DIV_BY_8 8 2004 #define PMU7_PLL_CTL8_M5DIV_BY_12 0xc 2005 #define PMU7_PLL_CTL8_M5DIV_BY_24 0x18 2006 #define PMU7_PLL_CTL8_M6DIV_MASK 0x0000ff00 2007 #define PMU7_PLL_CTL8_M6DIV_SHIFT 8 2008 #define PMU7_PLL_CTL8_M6DIV_BY_12 0xc 2009 #define PMU7_PLL_CTL8_M6DIV_BY_24 0x18 2010 #define PMU7_PLL_PLLCTL11 11 2011 #define PMU7_PLL_PLLCTL11_MASK 0xffffff00 2012 #define PMU7_PLL_PLLCTL11_VAL 0x22222200 2013 2014 /* PMU rev 15 */ 2015 #define PMU15_PLL_PLLCTL0 0 2016 #define PMU15_PLL_PC0_CLKSEL_MASK 0x00000003 2017 #define PMU15_PLL_PC0_CLKSEL_SHIFT 0 2018 #define PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC 2019 #define PMU15_PLL_PC0_FREQTGT_SHIFT 2 2020 #define PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000 2021 #define PMU15_PLL_PC0_PRESCALE_SHIFT 22 2022 #define PMU15_PLL_PC0_KPCTRL_MASK 0x07000000 2023 #define PMU15_PLL_PC0_KPCTRL_SHIFT 24 2024 #define PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000 2025 #define PMU15_PLL_PC0_FCNTCTRL_SHIFT 27 2026 #define PMU15_PLL_PC0_FDCMODE_MASK 0x40000000 2027 #define PMU15_PLL_PC0_FDCMODE_SHIFT 30 2028 #define PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000 2029 #define PMU15_PLL_PC0_CTRLBIAS_SHIFT 31 2030 2031 #define PMU15_PLL_PLLCTL1 1 2032 #define PMU15_PLL_PC1_BIAS_CTLM_MASK 0x00000060 2033 #define PMU15_PLL_PC1_BIAS_CTLM_SHIFT 5 2034 #define PMU15_PLL_PC1_BIAS_CTLM_RST_MASK 0x00000040 2035 #define PMU15_PLL_PC1_BIAS_CTLM_RST_SHIFT 6 2036 #define PMU15_PLL_PC1_BIAS_SS_DIVR_MASK 0x0001FF80 2037 #define PMU15_PLL_PC1_BIAS_SS_DIVR_SHIFT 7 2038 #define PMU15_PLL_PC1_BIAS_SS_RSTVAL_MASK 0x03FE0000 2039 #define PMU15_PLL_PC1_BIAS_SS_RSTVAL_SHIFT 17 2040 #define PMU15_PLL_PC1_BIAS_INTG_BW_MASK 0x0C000000 2041 #define PMU15_PLL_PC1_BIAS_INTG_BW_SHIFT 26 2042 #define PMU15_PLL_PC1_BIAS_INTG_BYP_MASK 0x10000000 2043 #define PMU15_PLL_PC1_BIAS_INTG_BYP_SHIFT 28 2044 #define PMU15_PLL_PC1_OPENLP_EN_MASK 0x40000000 2045 #define PMU15_PLL_PC1_OPENLP_EN_SHIFT 30 2046 2047 #define PMU15_PLL_PLLCTL2 2 2048 #define PMU15_PLL_PC2_CTEN_MASK 0x00000001 2049 #define PMU15_PLL_PC2_CTEN_SHIFT 0 2050 2051 #define PMU15_PLL_PLLCTL3 3 2052 #define PMU15_PLL_PC3_DITHER_EN_MASK 0x00000001 2053 #define PMU15_PLL_PC3_DITHER_EN_SHIFT 0 2054 #define PMU15_PLL_PC3_DCOCTLSP_MASK 0xFE000000 2055 #define PMU15_PLL_PC3_DCOCTLSP_SHIFT 25 2056 #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_MASK 0x01 2057 #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_SHIFT 0 2058 #define PMU15_PLL_PC3_DCOCTLSP_CH0EN_MASK 0x02 2059 #define PMU15_PLL_PC3_DCOCTLSP_CH0EN_SHIFT 1 2060 #define PMU15_PLL_PC3_DCOCTLSP_CH1EN_MASK 0x04 2061 #define PMU15_PLL_PC3_DCOCTLSP_CH1EN_SHIFT 2 2062 #define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_MASK 0x18 2063 #define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_SHIFT 3 2064 #define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_MASK 0x60 2065 #define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_SHIFT 5 2066 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV1 0 2067 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV2 1 2068 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV3 2 2069 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV5 3 2070 2071 #define PMU15_PLL_PLLCTL4 4 2072 #define PMU15_PLL_PC4_FLLCLK1_DIV_MASK 0x00000007 2073 #define PMU15_PLL_PC4_FLLCLK1_DIV_SHIFT 0 2074 #define PMU15_PLL_PC4_FLLCLK2_DIV_MASK 0x00000038 2075 #define PMU15_PLL_PC4_FLLCLK2_DIV_SHIFT 3 2076 #define PMU15_PLL_PC4_FLLCLK3_DIV_MASK 0x000001C0 2077 #define PMU15_PLL_PC4_FLLCLK3_DIV_SHIFT 6 2078 #define PMU15_PLL_PC4_DBGMODE_MASK 0x00000E00 2079 #define PMU15_PLL_PC4_DBGMODE_SHIFT 9 2080 #define PMU15_PLL_PC4_FLL480_CTLSP_LK_MASK 0x00001000 2081 #define PMU15_PLL_PC4_FLL480_CTLSP_LK_SHIFT 12 2082 #define PMU15_PLL_PC4_FLL480_CTLSP_MASK 0x000FE000 2083 #define PMU15_PLL_PC4_FLL480_CTLSP_SHIFT 13 2084 #define PMU15_PLL_PC4_DINPOL_MASK 0x00100000 2085 #define PMU15_PLL_PC4_DINPOL_SHIFT 20 2086 #define PMU15_PLL_PC4_CLKOUT_PD_MASK 0x00200000 2087 #define PMU15_PLL_PC4_CLKOUT_PD_SHIFT 21 2088 #define PMU15_PLL_PC4_CLKDIV2_PD_MASK 0x00400000 2089 #define PMU15_PLL_PC4_CLKDIV2_PD_SHIFT 22 2090 #define PMU15_PLL_PC4_CLKDIV4_PD_MASK 0x00800000 2091 #define PMU15_PLL_PC4_CLKDIV4_PD_SHIFT 23 2092 #define PMU15_PLL_PC4_CLKDIV8_PD_MASK 0x01000000 2093 #define PMU15_PLL_PC4_CLKDIV8_PD_SHIFT 24 2094 #define PMU15_PLL_PC4_CLKDIV16_PD_MASK 0x02000000 2095 #define PMU15_PLL_PC4_CLKDIV16_PD_SHIFT 25 2096 #define PMU15_PLL_PC4_TEST_EN_MASK 0x04000000 2097 #define PMU15_PLL_PC4_TEST_EN_SHIFT 26 2098 2099 #define PMU15_PLL_PLLCTL5 5 2100 #define PMU15_PLL_PC5_FREQTGT_MASK 0x000FFFFF 2101 #define PMU15_PLL_PC5_FREQTGT_SHIFT 0 2102 #define PMU15_PLL_PC5_DCOCTLSP_MASK 0x07F00000 2103 #define PMU15_PLL_PC5_DCOCTLSP_SHIFT 20 2104 #define PMU15_PLL_PC5_PRESCALE_MASK 0x18000000 2105 #define PMU15_PLL_PC5_PRESCALE_SHIFT 27 2106 2107 #define PMU15_PLL_PLLCTL6 6 2108 #define PMU15_PLL_PC6_FREQTGT_MASK 0x000FFFFF 2109 #define PMU15_PLL_PC6_FREQTGT_SHIFT 0 2110 #define PMU15_PLL_PC6_DCOCTLSP_MASK 0x07F00000 2111 #define PMU15_PLL_PC6_DCOCTLSP_SHIFT 20 2112 #define PMU15_PLL_PC6_PRESCALE_MASK 0x18000000 2113 #define PMU15_PLL_PC6_PRESCALE_SHIFT 27 2114 2115 #define PMU15_FREQTGT_480_DEFAULT 0x19AB1 2116 #define PMU15_FREQTGT_492_DEFAULT 0x1A4F5 2117 #define PMU15_ARM_96MHZ 96000000 /**< 96 Mhz */ 2118 #define PMU15_ARM_98MHZ 98400000 /**< 98.4 Mhz */ 2119 #define PMU15_ARM_97MHZ 97000000 /**< 97 Mhz */ 2120 2121 #define PMU17_PLLCTL2_NDIVTYPE_MASK 0x00000070 2122 #define PMU17_PLLCTL2_NDIVTYPE_SHIFT 4 2123 2124 #define PMU17_PLLCTL2_NDIV_MODE_INT 0 2125 #define PMU17_PLLCTL2_NDIV_MODE_INT1B8 1 2126 #define PMU17_PLLCTL2_NDIV_MODE_MASH111 2 2127 #define PMU17_PLLCTL2_NDIV_MODE_MASH111B8 3 2128 2129 #define PMU17_PLLCTL0_BBPLL_PWRDWN 0 2130 #define PMU17_PLLCTL0_BBPLL_DRST 3 2131 #define PMU17_PLLCTL0_BBPLL_DISBL_CLK 8 2132 2133 /* PLL usage in 4716/47162 */ 2134 #define PMU4716_MAINPLL_PLL0 12 2135 2136 /* PLL usage in 4335 */ 2137 #define PMU4335_PLL0_PC2_P1DIV_MASK 0x000f0000 2138 #define PMU4335_PLL0_PC2_P1DIV_SHIFT 16 2139 #define PMU4335_PLL0_PC2_NDIV_INT_MASK 0xff800000 2140 #define PMU4335_PLL0_PC2_NDIV_INT_SHIFT 23 2141 #define PMU4335_PLL0_PC1_MDIV2_MASK 0x0000ff00 2142 #define PMU4335_PLL0_PC1_MDIV2_SHIFT 8 2143 2144 /* PLL usage in 4347 */ 2145 #define PMU4347_PLL0_PC2_P1DIV_MASK 0x000f0000 2146 #define PMU4347_PLL0_PC2_P1DIV_SHIFT 16 2147 #define PMU4347_PLL0_PC2_NDIV_INT_MASK 0x3ff00000 2148 #define PMU4347_PLL0_PC2_NDIV_INT_SHIFT 20 2149 #define PMU4347_PLL0_PC3_NDIV_FRAC_MASK 0x000fffff 2150 #define PMU4347_PLL0_PC3_NDIV_FRAC_SHIFT 0 2151 #define PMU4347_PLL1_PC5_P1DIV_MASK 0xc0000000 2152 #define PMU4347_PLL1_PC5_P1DIV_SHIFT 30 2153 #define PMU4347_PLL1_PC6_P1DIV_MASK 0x00000003 2154 #define PMU4347_PLL1_PC6_P1DIV_SHIFT 0 2155 #define PMU4347_PLL1_PC6_NDIV_INT_MASK 0x00000ffc 2156 #define PMU4347_PLL1_PC6_NDIV_INT_SHIFT 2 2157 #define PMU4347_PLL1_PC6_NDIV_FRAC_MASK 0xfffff000 2158 #define PMU4347_PLL1_PC6_NDIV_FRAC_SHIFT 12 2159 2160 /* Even though the masks are same as 4347, separate macros are 2161 created for 4369 2162 */ 2163 /* PLL usage in 4369 */ 2164 #define PMU4369_PLL0_PC2_PDIV_MASK 0x000f0000 2165 #define PMU4369_PLL0_PC2_PDIV_SHIFT 16 2166 #define PMU4369_PLL0_PC2_NDIV_INT_MASK 0x3ff00000 2167 #define PMU4369_PLL0_PC2_NDIV_INT_SHIFT 20 2168 #define PMU4369_PLL0_PC3_NDIV_FRAC_MASK 0x000fffff 2169 #define PMU4369_PLL0_PC3_NDIV_FRAC_SHIFT 0 2170 #define PMU4369_PLL1_PC5_P1DIV_MASK 0xc0000000 2171 #define PMU4369_PLL1_PC5_P1DIV_SHIFT 30 2172 #define PMU4369_PLL1_PC6_P1DIV_MASK 0x00000003 2173 #define PMU4369_PLL1_PC6_P1DIV_SHIFT 0 2174 #define PMU4369_PLL1_PC6_NDIV_INT_MASK 0x00000ffc 2175 #define PMU4369_PLL1_PC6_NDIV_INT_SHIFT 2 2176 #define PMU4369_PLL1_PC6_NDIV_FRAC_MASK 0xfffff000 2177 #define PMU4369_PLL1_PC6_NDIV_FRAC_SHIFT 12 2178 2179 /* 5357 Chip specific ChipControl register bits */ 2180 #define CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */ 2181 #define CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */ 2182 #define CCTRL5357_NFLASH (1<<16) /* Nandflash in ChipControl 1, bit 16 */ 2183 /* 43217 Chip specific ChipControl register bits */ 2184 #define CCTRL43217_EXTPA_C0 (1<<13) /* core0 extPA in ChipControl 1, bit 13 */ 2185 #define CCTRL43217_EXTPA_C1 (1<<8) /* core1 extPA in ChipControl 1, bit 8 */ 2186 2187 /* 43236 resources */ 2188 #define RES43236_REGULATOR 0 2189 #define RES43236_ILP_REQUEST 1 2190 #define RES43236_XTAL_PU 2 2191 #define RES43236_ALP_AVAIL 3 2192 #define RES43236_SI_PLL_ON 4 2193 #define RES43236_HT_SI_AVAIL 5 2194 2195 /* 43236 chip-specific ChipControl register bits */ 2196 #define CCTRL43236_BT_COEXIST (1<<0) /**< 0 disable */ 2197 #define CCTRL43236_SECI (1<<1) /**< 0 SECI is disabled (JATG functional) */ 2198 #define CCTRL43236_EXT_LNA (1<<2) /**< 0 disable */ 2199 #define CCTRL43236_ANT_MUX_2o3 (1<<3) /**< 2o3 mux, chipcontrol bit 3 */ 2200 #define CCTRL43236_GSIO (1<<4) /**< 0 disable */ 2201 2202 /* 43236 Chip specific ChipStatus register bits */ 2203 #define CST43236_SFLASH_MASK 0x00000040 2204 #define CST43236_OTP_SEL_MASK 0x00000080 2205 #define CST43236_OTP_SEL_SHIFT 7 2206 #define CST43236_HSIC_MASK 0x00000100 /**< USB/HSIC */ 2207 #define CST43236_BP_CLK 0x00000200 /**< 120/96Mbps */ 2208 #define CST43236_BOOT_MASK 0x00001800 2209 #define CST43236_BOOT_SHIFT 11 2210 #define CST43236_BOOT_FROM_SRAM 0 /**< boot from SRAM, ARM in reset */ 2211 #define CST43236_BOOT_FROM_ROM 1 /**< boot from ROM */ 2212 #define CST43236_BOOT_FROM_FLASH 2 /**< boot from FLASH */ 2213 #define CST43236_BOOT_FROM_INVALID 3 2214 2215 #define PMU1_PLL0_CHIPCTL0 0 2216 #define PMU1_PLL0_CHIPCTL1 1 2217 #define PMU1_PLL0_CHIPCTL2 2 2218 2219 #define SOCDEVRAM_BP_ADDR 0x1E000000 2220 #define SOCDEVRAM_ARM_ADDR 0x00800000 2221 2222 #define PMU_VREG0_I_SR_CNTL_EN_SHIFT 0 2223 #define PMU_VREG0_DISABLE_PULLD_BT_SHIFT 2 2224 #define PMU_VREG0_DISABLE_PULLD_WL_SHIFT 3 2225 #define PMU_VREG0_CBUCKFSW_ADJ_SHIFT 7 2226 #define PMU_VREG0_CBUCKFSW_ADJ_MASK 0x1F 2227 #define PMU_VREG0_RAMP_SEL_SHIFT 13 2228 #define PMU_VREG0_RAMP_SEL_MASK 0x7 2229 #define PMU_VREG0_VFB_RSEL_SHIFT 17 2230 #define PMU_VREG0_VFB_RSEL_MASK 3 2231 2232 #define PMU_VREG4_ADDR 4 2233 2234 #define PMU_VREG4_CLDO_PWM_SHIFT 4 2235 #define PMU_VREG4_CLDO_PWM_MASK 0x7 2236 2237 #define PMU_VREG4_LPLDO1_SHIFT 15 2238 #define PMU_VREG4_LPLDO1_MASK 0x7 2239 #define PMU_VREG4_LPLDO1_1p20V 0 2240 #define PMU_VREG4_LPLDO1_1p15V 1 2241 #define PMU_VREG4_LPLDO1_1p10V 2 2242 #define PMU_VREG4_LPLDO1_1p25V 3 2243 #define PMU_VREG4_LPLDO1_1p05V 4 2244 #define PMU_VREG4_LPLDO1_1p00V 5 2245 #define PMU_VREG4_LPLDO1_0p95V 6 2246 #define PMU_VREG4_LPLDO1_0p90V 7 2247 2248 /* 4350/4345 VREG4 settings */ 2249 #define PMU4350_VREG4_LPLDO1_1p10V 0 2250 #define PMU4350_VREG4_LPLDO1_1p15V 1 2251 #define PMU4350_VREG4_LPLDO1_1p21V 2 2252 #define PMU4350_VREG4_LPLDO1_1p24V 3 2253 #define PMU4350_VREG4_LPLDO1_0p90V 4 2254 #define PMU4350_VREG4_LPLDO1_0p96V 5 2255 #define PMU4350_VREG4_LPLDO1_1p01V 6 2256 #define PMU4350_VREG4_LPLDO1_1p04V 7 2257 2258 #define PMU_VREG4_LPLDO2_LVM_SHIFT 18 2259 #define PMU_VREG4_LPLDO2_LVM_MASK 0x7 2260 #define PMU_VREG4_LPLDO2_HVM_SHIFT 21 2261 #define PMU_VREG4_LPLDO2_HVM_MASK 0x7 2262 #define PMU_VREG4_LPLDO2_LVM_HVM_MASK 0x3f 2263 #define PMU_VREG4_LPLDO2_1p00V 0 2264 #define PMU_VREG4_LPLDO2_1p15V 1 2265 #define PMU_VREG4_LPLDO2_1p20V 2 2266 #define PMU_VREG4_LPLDO2_1p10V 3 2267 #define PMU_VREG4_LPLDO2_0p90V 4 /**< 4 - 7 is 0.90V */ 2268 2269 #define PMU_VREG4_HSICLDO_BYPASS_SHIFT 27 2270 #define PMU_VREG4_HSICLDO_BYPASS_MASK 0x1 2271 2272 #define PMU_VREG5_ADDR 5 2273 #define PMU_VREG5_HSICAVDD_PD_SHIFT 6 2274 #define PMU_VREG5_HSICAVDD_PD_MASK 0x1 2275 #define PMU_VREG5_HSICDVDD_PD_SHIFT 11 2276 #define PMU_VREG5_HSICDVDD_PD_MASK 0x1 2277 2278 /* 43228 chipstatus reg bits */ 2279 #define CST43228_OTP_PRESENT 0x2 2280 2281 /* 4360 Chip specific ChipControl register bits */ 2282 #define CCTRL4360_I2C_MODE (1 << 0) 2283 #define CCTRL4360_UART_MODE (1 << 1) 2284 #define CCTRL4360_SECI_MODE (1 << 2) 2285 #define CCTRL4360_BTSWCTRL_MODE (1 << 3) 2286 #define CCTRL4360_DISCRETE_FEMCTRL_MODE (1 << 4) 2287 #define CCTRL4360_DIGITAL_PACTRL_MODE (1 << 5) 2288 #define CCTRL4360_BTSWCTRL_AND_DIGPA_PRESENT (1 << 6) 2289 #define CCTRL4360_EXTRA_GPIO_MODE (1 << 7) 2290 #define CCTRL4360_EXTRA_FEMCTRL_MODE (1 << 8) 2291 #define CCTRL4360_BT_LGCY_MODE (1 << 9) 2292 #define CCTRL4360_CORE2FEMCTRL4_ON (1 << 21) 2293 #define CCTRL4360_SECI_ON_GPIO01 (1 << 24) 2294 2295 /* 4360 Chip specific Regulator Control register bits */ 2296 #define RCTRL4360_RFLDO_PWR_DOWN (1 << 1) 2297 2298 /* 4360 PMU resources and chip status bits */ 2299 #define RES4360_REGULATOR 0 2300 #define RES4360_ILP_AVAIL 1 2301 #define RES4360_ILP_REQ 2 2302 #define RES4360_XTAL_LDO_PU 3 2303 #define RES4360_XTAL_PU 4 2304 #define RES4360_ALP_AVAIL 5 2305 #define RES4360_BBPLLPWRSW_PU 6 2306 #define RES4360_HT_AVAIL 7 2307 #define RES4360_OTP_PU 8 2308 #define RES4360_AVB_PLL_PWRSW_PU 9 2309 #define RES4360_PCIE_TL_CLK_AVAIL 10 2310 2311 #define CST4360_XTAL_40MZ 0x00000001 2312 #define CST4360_SFLASH 0x00000002 2313 #define CST4360_SPROM_PRESENT 0x00000004 2314 #define CST4360_SFLASH_TYPE 0x00000004 2315 #define CST4360_OTP_ENABLED 0x00000008 2316 #define CST4360_REMAP_ROM 0x00000010 2317 #define CST4360_RSRC_INIT_MODE_MASK 0x00000060 2318 #define CST4360_RSRC_INIT_MODE_SHIFT 5 2319 #define CST4360_ILP_DIVEN 0x00000080 2320 #define CST4360_MODE_USB 0x00000100 2321 #define CST4360_SPROM_SIZE_MASK 0x00000600 2322 #define CST4360_SPROM_SIZE_SHIFT 9 2323 #define CST4360_BBPLL_LOCK 0x00000800 2324 #define CST4360_AVBBPLL_LOCK 0x00001000 2325 #define CST4360_USBBBPLL_LOCK 0x00002000 2326 #define CST4360_RSRC_INIT_MODE(cs) ((cs & CST4360_RSRC_INIT_MODE_MASK) >> \ 2327 CST4360_RSRC_INIT_MODE_SHIFT) 2328 2329 #define CCTRL_4360_UART_SEL 0x2 2330 2331 #define CST4360_RSRC_INIT_MODE(cs) ((cs & CST4360_RSRC_INIT_MODE_MASK) >> \ 2332 CST4360_RSRC_INIT_MODE_SHIFT) 2333 2334 #define PMU4360_CC1_GPIO7_OVRD (1<<23) /* GPIO7 override */ 2335 2336 /* 43602 PMU resources based on pmu_params.xls version v0.95 */ 2337 #define RES43602_LPLDO_PU 0 2338 #define RES43602_REGULATOR 1 2339 #define RES43602_PMU_SLEEP 2 2340 #define RES43602_RSVD_3 3 2341 #define RES43602_XTALLDO_PU 4 2342 #define RES43602_SERDES_PU 5 2343 #define RES43602_BBPLL_PWRSW_PU 6 2344 #define RES43602_SR_CLK_START 7 2345 #define RES43602_SR_PHY_PWRSW 8 2346 #define RES43602_SR_SUBCORE_PWRSW 9 2347 #define RES43602_XTAL_PU 10 2348 #define RES43602_PERST_OVR 11 2349 #define RES43602_SR_CLK_STABLE 12 2350 #define RES43602_SR_SAVE_RESTORE 13 2351 #define RES43602_SR_SLEEP 14 2352 #define RES43602_LQ_START 15 2353 #define RES43602_LQ_AVAIL 16 2354 #define RES43602_WL_CORE_RDY 17 2355 #define RES43602_ILP_REQ 18 2356 #define RES43602_ALP_AVAIL 19 2357 #define RES43602_RADIO_PU 20 2358 #define RES43602_RFLDO_PU 21 2359 #define RES43602_HT_START 22 2360 #define RES43602_HT_AVAIL 23 2361 #define RES43602_MACPHY_CLKAVAIL 24 2362 #define RES43602_PARLDO_PU 25 2363 #define RES43602_RSVD_26 26 2364 2365 /* 43602 chip status bits */ 2366 #define CST43602_SPROM_PRESENT (1<<1) 2367 #define CST43602_SPROM_SIZE (1<<10) /* 0 = 16K, 1 = 4K */ 2368 #define CST43602_BBPLL_LOCK (1<<11) 2369 #define CST43602_RF_LDO_OUT_OK (1<<15) /* RF LDO output OK */ 2370 2371 #define PMU43602_CC1_GPIO12_OVRD (1<<28) /* GPIO12 override */ 2372 2373 #define PMU43602_CC2_PCIE_CLKREQ_L_WAKE_EN (1<<1) /* creates gated_pcie_wake, pmu_wakeup logic */ 2374 #define PMU43602_CC2_PCIE_PERST_L_WAKE_EN (1<<2) /* creates gated_pcie_wake, pmu_wakeup logic */ 2375 #define PMU43602_CC2_ENABLE_L2REFCLKPAD_PWRDWN (1<<3) 2376 #define PMU43602_CC2_PMU_WAKE_ALP_AVAIL_EN (1<<5) /* enable pmu_wakeup to request for ALP_AVAIL */ 2377 #define PMU43602_CC2_PERST_L_EXTEND_EN (1<<9) /* extend perst_l until rsc PERST_OVR comes up */ 2378 #define PMU43602_CC2_FORCE_EXT_LPO (1<<19) /* 1=ext LPO clock is the final LPO clock */ 2379 #define PMU43602_CC2_XTAL32_SEL (1<<30) /* 0=ext_clock, 1=xtal */ 2380 2381 #define CC_SR1_43602_SR_ASM_ADDR (0x0) 2382 2383 /* PLL CTL register values for open loop, used during S/R operation */ 2384 #define PMU43602_PLL_CTL6_VAL 0x68000528 2385 #define PMU43602_PLL_CTL7_VAL 0x6 2386 2387 #define PMU43602_CC3_ARMCR4_DBG_CLK (1 << 29) 2388 2389 /* 4365 PMU resources */ 2390 #define RES4365_REGULATOR_PU 0 2391 #define RES4365_XTALLDO_PU 1 2392 #define RES4365_XTAL_PU 2 2393 #define RES4365_CPU_PLLLDO_PU 3 2394 #define RES4365_CPU_PLL_PU 4 2395 #define RES4365_WL_CORE_RDY 5 2396 #define RES4365_ILP_REQ 6 2397 #define RES4365_ALP_AVAIL 7 2398 #define RES4365_HT_AVAIL 8 2399 #define RES4365_BB_PLLLDO_PU 9 2400 #define RES4365_BB_PLL_PU 10 2401 #define RES4365_MINIMU_PU 11 2402 #define RES4365_RADIO_PU 12 2403 #define RES4365_MACPHY_CLK_AVAIL 13 2404 2405 /* 43684 PMU resources */ 2406 #define RES43684_REGULATOR_PU 0 2407 #define RES43684_PCIE_LDO_BG_PU 1 2408 #define RES43684_XTAL_LDO_PU 2 2409 #define RES43684_XTAL_PU 3 2410 #define RES43684_CPU_PLL_LDO_PU 4 2411 #define RES43684_CPU_PLL_PU 5 2412 #define RES43684_WL_CORE_RDY 6 2413 #define RES43684_ILP_REQ 7 2414 #define RES43684_ALP_AVAIL 8 2415 #define RES43684_HT_AVAIL 9 2416 #define RES43684_BB_PLL_LDO_PU 10 2417 #define RES43684_BB_PLL_PU 11 2418 #define RES43684_MINI_PMU_PU 12 2419 #define RES43684_RADIO_PU 13 2420 #define RES43684_MACPHY_CLK_AVAIL 14 2421 #define RES43684_PCIE_LDO_PU 15 2422 2423 /* 7271 PMU resources */ 2424 #define RES7271_REGULATOR_PU 0 2425 #define RES7271_WL_CORE_RDY 1 2426 #define RES7271_ILP_REQ 2 2427 #define RES7271_ALP_AVAIL 3 2428 #define RES7271_HT_AVAIL 4 2429 #define RES7271_BB_PLL_PU 5 2430 #define RES7271_MINIPMU_PU 6 2431 #define RES7271_RADIO_PU 7 2432 #define RES7271_MACPHY_CLK_AVAIL 8 2433 2434 /* 4349 related */ 2435 #define RES4349_LPLDO_PU 0 2436 #define RES4349_BG_PU 1 2437 #define RES4349_PMU_SLEEP 2 2438 #define RES4349_PALDO3P3_PU 3 2439 #define RES4349_CBUCK_LPOM_PU 4 2440 #define RES4349_CBUCK_PFM_PU 5 2441 #define RES4349_COLD_START_WAIT 6 2442 #define RES4349_RSVD_7 7 2443 #define RES4349_LNLDO_PU 8 2444 #define RES4349_XTALLDO_PU 9 2445 #define RES4349_LDO3P3_PU 10 2446 #define RES4349_OTP_PU 11 2447 #define RES4349_XTAL_PU 12 2448 #define RES4349_SR_CLK_START 13 2449 #define RES4349_LQ_AVAIL 14 2450 #define RES4349_LQ_START 15 2451 #define RES4349_PERST_OVR 16 2452 #define RES4349_WL_CORE_RDY 17 2453 #define RES4349_ILP_REQ 18 2454 #define RES4349_ALP_AVAIL 19 2455 #define RES4349_MINI_PMU 20 2456 #define RES4349_RADIO_PU 21 2457 #define RES4349_SR_CLK_STABLE 22 2458 #define RES4349_SR_SAVE_RESTORE 23 2459 #define RES4349_SR_PHY_PWRSW 24 2460 #define RES4349_SR_VDDM_PWRSW 25 2461 #define RES4349_SR_SUBCORE_PWRSW 26 2462 #define RES4349_SR_SLEEP 27 2463 #define RES4349_HT_START 28 2464 #define RES4349_HT_AVAIL 29 2465 #define RES4349_MACPHY_CLKAVAIL 30 2466 2467 /* 4373 PMU resources */ 2468 #define RES4373_LPLDO_PU 0 2469 #define RES4373_BG_PU 1 2470 #define RES4373_PMU_SLEEP 2 2471 #define RES4373_PALDO3P3_PU 3 2472 #define RES4373_CBUCK_LPOM_PU 4 2473 #define RES4373_CBUCK_PFM_PU 5 2474 #define RES4373_COLD_START_WAIT 6 2475 #define RES4373_RSVD_7 7 2476 #define RES4373_LNLDO_PU 8 2477 #define RES4373_XTALLDO_PU 9 2478 #define RES4373_LDO3P3_PU 10 2479 #define RES4373_OTP_PU 11 2480 #define RES4373_XTAL_PU 12 2481 #define RES4373_SR_CLK_START 13 2482 #define RES4373_LQ_AVAIL 14 2483 #define RES4373_LQ_START 15 2484 #define RES4373_PERST_OVR 16 2485 #define RES4373_WL_CORE_RDY 17 2486 #define RES4373_ILP_REQ 18 2487 #define RES4373_ALP_AVAIL 19 2488 #define RES4373_MINI_PMU 20 2489 #define RES4373_RADIO_PU 21 2490 #define RES4373_SR_CLK_STABLE 22 2491 #define RES4373_SR_SAVE_RESTORE 23 2492 #define RES4373_SR_PHY_PWRSW 24 2493 #define RES4373_SR_VDDM_PWRSW 25 2494 #define RES4373_SR_SUBCORE_PWRSW 26 2495 #define RES4373_SR_SLEEP 27 2496 #define RES4373_HT_START 28 2497 #define RES4373_HT_AVAIL 29 2498 #define RES4373_MACPHY_CLKAVAIL 30 2499 /* SR Control0 bits */ 2500 #define CC_SR0_4349_SR_ENG_EN_MASK 0x1 2501 #define CC_SR0_4349_SR_ENG_EN_SHIFT 0 2502 #define CC_SR0_4349_SR_ENG_CLK_EN (1 << 1) 2503 #define CC_SR0_4349_SR_RSRC_TRIGGER (0xC << 2) 2504 #define CC_SR0_4349_SR_WD_MEM_MIN_DIV (0x3 << 6) 2505 #define CC_SR0_4349_SR_MEM_STBY_ALLOW_MSK (1 << 16) 2506 #define CC_SR0_4349_SR_MEM_STBY_ALLOW_SHIFT 16 2507 #define CC_SR0_4349_SR_ENABLE_ILP (1 << 17) 2508 #define CC_SR0_4349_SR_ENABLE_ALP (1 << 18) 2509 #define CC_SR0_4349_SR_ENABLE_HT (1 << 19) 2510 #define CC_SR0_4349_SR_ALLOW_PIC (3 << 20) 2511 #define CC_SR0_4349_SR_PMU_MEM_DISABLE (1 << 30) 2512 /* SR Control0 bits */ 2513 #define CC_SR0_4349_SR_ENG_EN_MASK 0x1 2514 #define CC_SR0_4349_SR_ENG_EN_SHIFT 0 2515 #define CC_SR0_4349_SR_ENG_CLK_EN (1 << 1) 2516 #define CC_SR0_4349_SR_RSRC_TRIGGER (0xC << 2) 2517 #define CC_SR0_4349_SR_WD_MEM_MIN_DIV (0x3 << 6) 2518 #define CC_SR0_4349_SR_MEM_STBY_ALLOW (1 << 16) 2519 #define CC_SR0_4349_SR_ENABLE_ILP (1 << 17) 2520 #define CC_SR0_4349_SR_ENABLE_ALP (1 << 18) 2521 #define CC_SR0_4349_SR_ENABLE_HT (1 << 19) 2522 #define CC_SR0_4349_SR_ALLOW_PIC (3 << 20) 2523 #define CC_SR0_4349_SR_PMU_MEM_DISABLE (1 << 30) 2524 2525 /* SR binary offset is at 8K */ 2526 #define CC_SR1_4349_SR_ASM_ADDR (0x10) 2527 #define CST4349_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */ 2528 #define CST4349_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */ 2529 #define CST4349_SPROM_PRESENT 0x00000010 2530 2531 /* 4373 related */ 2532 #define CST4373_CHIPMODE_USB20D(cs) (((cs) & (1 << 8)) != 0) /* USB */ 2533 #define CST4373_CHIPMODE_SDIOD(cs) (((cs) & (1 << 7)) != 0) /* SDIO */ 2534 #define CST4373_CHIPMODE_PCIE(cs) (((cs) & (1 << 6)) != 0) /* PCIE */ 2535 #define CST4373_SFLASH_PRESENT 0x00000010 2536 2537 #define VREG4_4349_MEMLPLDO_PWRUP_MASK (1 << 31) 2538 #define VREG4_4349_MEMLPLDO_PWRUP_SHIFT (31) 2539 #define VREG4_4349_LPLDO1_OUTPUT_VOLT_ADJ_MASK (0x7 << 15) 2540 #define VREG4_4349_LPLDO1_OUTPUT_VOLT_ADJ_SHIFT (15) 2541 #define CC2_4349_PHY_PWRSE_RST_CNT_MASK (0xF << 0) 2542 #define CC2_4349_PHY_PWRSE_RST_CNT_SHIFT (0) 2543 #define CC2_4349_VDDM_PWRSW_EN_MASK (1 << 20) 2544 #define CC2_4349_VDDM_PWRSW_EN_SHIFT (20) 2545 #define CC2_4349_MEMLPLDO_PWRSW_EN_MASK (1 << 21) 2546 #define CC2_4349_MEMLPLDO_PWRSW_EN_SHIFT (21) 2547 #define CC2_4349_SDIO_AOS_WAKEUP_MASK (1 << 24) 2548 #define CC2_4349_SDIO_AOS_WAKEUP_SHIFT (24) 2549 #define CC2_4349_PMUWAKE_EN_MASK (1 << 31) 2550 #define CC2_4349_PMUWAKE_EN_SHIFT (31) 2551 2552 #define CC5_4349_MAC_PHY_CLK_8_DIV (1 << 27) 2553 2554 #define CC6_4349_PCIE_CLKREQ_WAKEUP_MASK (1 << 4) 2555 #define CC6_4349_PCIE_CLKREQ_WAKEUP_SHIFT (4) 2556 #define CC6_4349_PMU_WAKEUP_ALPAVAIL_MASK (1 << 6) 2557 #define CC6_4349_PMU_WAKEUP_ALPAVAIL_SHIFT (6) 2558 #define CC6_4349_PMU_EN_EXT_PERST_MASK (1 << 13) 2559 #define CC6_4349_PMU_EN_L2_DEASSERT_MASK (1 << 14) 2560 #define CC6_4349_PMU_EN_L2_DEASSERT_SHIF (14) 2561 #define CC6_4349_PMU_ENABLE_L2REFCLKPAD_PWRDWN (1 << 15) 2562 #define CC6_4349_PMU_EN_MDIO_MASK (1 << 16) 2563 #define CC6_4349_PMU_EN_ASSERT_L2_MASK (1 << 25) 2564 2565 /* 4349 GCI function sel values */ 2566 /* 2567 * Reference 2568 * http://hwnbu-twiki.sj.broadcom.com/bin/view/Mwgroup/ToplevelArchitecture4349B0#Function_Sel 2569 */ 2570 #define CC4349_FNSEL_HWDEF (0) 2571 #define CC4349_FNSEL_SAMEASPIN (1) 2572 #define CC4349_FNSEL_GPIO (2) 2573 #define CC4349_FNSEL_FAST_UART (3) 2574 #define CC4349_FNSEL_GCI0 (4) 2575 #define CC4349_FNSEL_GCI1 (5) 2576 #define CC4349_FNSEL_DGB_UART (6) 2577 #define CC4349_FNSEL_I2C (7) 2578 #define CC4349_FNSEL_SPROM (8) 2579 #define CC4349_FNSEL_MISC0 (9) 2580 #define CC4349_FNSEL_MISC1 (10) 2581 #define CC4349_FNSEL_MISC2 (11) 2582 #define CC4349_FNSEL_IND (12) 2583 #define CC4349_FNSEL_PDN (13) 2584 #define CC4349_FNSEL_PUP (14) 2585 #define CC4349_FNSEL_TRISTATE (15) 2586 2587 /* 4364 related */ 2588 #define RES4364_LPLDO_PU 0 2589 #define RES4364_BG_PU 1 2590 #define RES4364_MEMLPLDO_PU 2 2591 #define RES4364_PALDO3P3_PU 3 2592 #define RES4364_CBUCK_1P2 4 2593 #define RES4364_CBUCK_1V8 5 2594 #define RES4364_COLD_START_WAIT 6 2595 #define RES4364_SR_3x3_VDDM_PWRSW 7 2596 #define RES4364_3x3_MACPHY_CLKAVAIL 8 2597 #define RES4364_XTALLDO_PU 9 2598 #define RES4364_LDO3P3_PU 10 2599 #define RES4364_OTP_PU 11 2600 #define RES4364_XTAL_PU 12 2601 #define RES4364_SR_CLK_START 13 2602 #define RES4364_3x3_RADIO_PU 14 2603 #define RES4364_RF_LDO 15 2604 #define RES4364_PERST_OVR 16 2605 #define RES4364_WL_CORE_RDY 17 2606 #define RES4364_ILP_REQ 18 2607 #define RES4364_ALP_AVAIL 19 2608 #define RES4364_1x1_MINI_PMU 20 2609 #define RES4364_1x1_RADIO_PU 21 2610 #define RES4364_SR_CLK_STABLE 22 2611 #define RES4364_SR_SAVE_RESTORE 23 2612 #define RES4364_SR_PHY_PWRSW 24 2613 #define RES4364_SR_VDDM_PWRSW 25 2614 #define RES4364_SR_SUBCORE_PWRSW 26 2615 #define RES4364_SR_SLEEP 27 2616 #define RES4364_HT_START 28 2617 #define RES4364_HT_AVAIL 29 2618 #define RES4364_MACPHY_CLKAVAIL 30 2619 2620 /* 4349 GPIO */ 2621 #define CC4349_PIN_GPIO_00 (0) 2622 #define CC4349_PIN_GPIO_01 (1) 2623 #define CC4349_PIN_GPIO_02 (2) 2624 #define CC4349_PIN_GPIO_03 (3) 2625 #define CC4349_PIN_GPIO_04 (4) 2626 #define CC4349_PIN_GPIO_05 (5) 2627 #define CC4349_PIN_GPIO_06 (6) 2628 #define CC4349_PIN_GPIO_07 (7) 2629 #define CC4349_PIN_GPIO_08 (8) 2630 #define CC4349_PIN_GPIO_09 (9) 2631 #define CC4349_PIN_GPIO_10 (10) 2632 #define CC4349_PIN_GPIO_11 (11) 2633 #define CC4349_PIN_GPIO_12 (12) 2634 #define CC4349_PIN_GPIO_13 (13) 2635 #define CC4349_PIN_GPIO_14 (14) 2636 #define CC4349_PIN_GPIO_15 (15) 2637 #define CC4349_PIN_GPIO_16 (16) 2638 #define CC4349_PIN_GPIO_17 (17) 2639 #define CC4349_PIN_GPIO_18 (18) 2640 #define CC4349_PIN_GPIO_19 (19) 2641 2642 /* Mask used to decide whether HOSTWAKE MUX to be performed or not */ 2643 #define MUXENAB4349_HOSTWAKE_MASK (0x000000f0) /* configure GPIO for SDIO host_wake */ 2644 #define MUXENAB4349_HOSTWAKE_SHIFT 4 2645 #define MUXENAB4349_GETIX(val, name) \ 2646 ((((val) & MUXENAB4349_ ## name ## _MASK) >> MUXENAB4349_ ## name ## _SHIFT) - 1) 2647 2648 #define CR4_4364_RAM_BASE (0x160000) 2649 2650 /* SR binary offset is at 8K */ 2651 #define CC_SR1_4364_SR_CORE0_ASM_ADDR (0x10) 2652 #define CC_SR1_4364_SR_CORE1_ASM_ADDR (0x10) 2653 2654 #define CC_SR0_4364_SR_ENG_EN_MASK 0x1 2655 #define CC_SR0_4364_SR_ENG_EN_SHIFT 0 2656 #define CC_SR0_4364_SR_ENG_CLK_EN (1 << 1) 2657 #define CC_SR0_4364_SR_RSRC_TRIGGER (0xC << 2) 2658 #define CC_SR0_4364_SR_WD_MEM_MIN_DIV (0x3 << 6) 2659 #define CC_SR0_4364_SR_MEM_STBY_ALLOW_MSK (1 << 16) 2660 #define CC_SR0_4364_SR_MEM_STBY_ALLOW_SHIFT 16 2661 #define CC_SR0_4364_SR_ENABLE_ILP (1 << 17) 2662 #define CC_SR0_4364_SR_ENABLE_ALP (1 << 18) 2663 #define CC_SR0_4364_SR_ENABLE_HT (1 << 19) 2664 #define CC_SR0_4364_SR_INVERT_CLK (1 << 11) 2665 #define CC_SR0_4364_SR_ALLOW_PIC (3 << 20) 2666 #define CC_SR0_4364_SR_PMU_MEM_DISABLE (1 << 30) 2667 2668 #define PMU_4364_CC1_ENABLE_BBPLL_PWR_DWN (0x1 << 4) 2669 #define PMU_4364_CC1_BBPLL_ARESET_LQ_TIME (0x1 << 8) 2670 #define PMU_4364_CC1_BBPLL_ARESET_HT_UPTIME (0x1 << 10) 2671 #define PMU_4364_CC1_BBPLL_DRESET_LQ_UPTIME (0x1 << 12) 2672 #define PMU_4364_CC1_BBPLL_DRESET_HT_UPTIME (0x4 << 16) 2673 #define PMU_4364_CC1_SUBCORE_PWRSW_UP_DELAY (0x8 << 20) 2674 #define PMU_4364_CC1_SUBCORE_PWRSW_RESET_CNT (0x4 << 24) 2675 2676 #define PMU_4364_CC2_PHY_PWRSW_RESET_CNT (0x2 << 0) 2677 #define PMU_4364_CC2_PHY_PWRSW_RESET_MASK (0x7) 2678 #define PMU_4364_CC2_SEL_CHIPC_IF_FOR_SR (1 << 21) 2679 2680 #define PMU_4364_CC3_MEMLPLDO3x3_PWRSW_FORCE_MASK (1 << 23) 2681 #define PMU_4364_CC3_MEMLPLDO1x1_PWRSW_FORCE_MASK (1 << 24) 2682 #define PMU_4364_CC3_CBUCK1P2_PU_SR_VDDM_REQ_ON (1 << 25) 2683 #define PMU_4364_CC3_MEMLPLDO3x3_PWRSW_FORCE_OFF (0) 2684 #define PMU_4364_CC3_MEMLPLDO1x1_PWRSW_FORCE_OFF (0) 2685 2686 #define PMU_4364_CC5_DISABLE_BBPLL_CLKOUT6_DIV2_MASK (1 << 26) 2687 #define PMU_4364_CC5_ENABLE_ARMCR4_DEBUG_CLK_MASK (1 << 4) 2688 #define PMU_4364_CC5_DISABLE_BBPLL_CLKOUT6_DIV2 (1 << 26) 2689 #define PMU_4364_CC5_ENABLE_ARMCR4_DEBUG_CLK_OFF (0) 2690 2691 #define PMU_4364_CC6_MDI_RESET_MASK (1 << 16) 2692 #define PMU_4364_CC6_USE_CLK_REQ_MASK (1 << 18) 2693 #define PMU_4364_CC6_HIGHER_CLK_REQ_ALP_MASK (1 << 20) 2694 #define PMU_4364_CC6_HT_AVAIL_REQ_ALP_AVAIL_MASK (1 << 21) 2695 #define PMU_4364_CC6_PHY_CLK_REQUESTS_ALP_AVAIL_MASK (1 << 22) 2696 #define PMU_4364_CC6_MDI_RESET (1 << 16) 2697 #define PMU_4364_CC6_USE_CLK_REQ (1 << 18) 2698 2699 #define PMU_4364_CC6_HIGHER_CLK_REQ_ALP (1 << 20) 2700 #define PMU_4364_CC6_HT_AVAIL_REQ_ALP_AVAIL (1 << 21) 2701 #define PMU_4364_CC6_PHY_CLK_REQUESTS_ALP_AVAIL (1 << 22) 2702 2703 #define PMU_4364_VREG0_DISABLE_BT_PULL_DOWN (1 << 2) 2704 #define PMU_4364_VREG1_DISABLE_WL_PULL_DOWN (1 << 2) 2705 2706 /* Indices of PMU voltage regulator registers */ 2707 #define PMU_VREG_0 (0u) 2708 #define PMU_VREG_1 (1u) 2709 #define PMU_VREG_2 (2u) 2710 #define PMU_VREG_3 (3u) 2711 #define PMU_VREG_4 (4u) 2712 #define PMU_VREG_5 (5u) 2713 #define PMU_VREG_6 (6u) 2714 #define PMU_VREG_7 (7u) 2715 #define PMU_VREG_8 (8u) 2716 #define PMU_VREG_9 (9u) 2717 #define PMU_VREG_10 (10u) 2718 #define PMU_VREG_11 (11u) 2719 #define PMU_VREG_12 (12u) 2720 #define PMU_VREG_13 (13u) 2721 #define PMU_VREG_14 (14u) 2722 #define PMU_VREG_15 (15u) 2723 #define PMU_VREG_16 (16u) 2724 2725 /* 43012 Chipcommon ChipStatus bits */ 2726 #define CST43012_FLL_LOCK (1 << 13) 2727 /* 43012 resources - End */ 2728 2729 /* 43012 related Cbuck modes */ 2730 #define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE0 0x00001c03 2731 #define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE0 0x00492490 2732 #define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE1 0x00001c03 2733 #define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE1 0x00490410 2734 2735 /* 43012 related dynamic cbuck mode mask */ 2736 #define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE_MASK 0xFFFFFC07 2737 #define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE_MASK 0xFFFFFFFF 2738 2739 /* 4369 related VREG masks */ 2740 #define PMU_4369_VREG_5_MISCLDO_POWER_UP_MASK (1u << 11u) 2741 #define PMU_4369_VREG_5_MISCLDO_POWER_UP_SHIFT 11u 2742 #define PMU_4369_VREG_5_LPLDO_POWER_UP_MASK (1u << 27u) 2743 #define PMU_4369_VREG_5_LPLDO_POWER_UP_SHIFT 27u 2744 #define PMU_4369_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_MASK BCM_MASK32(31, 28) 2745 #define PMU_4369_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_SHIFT 28u 2746 2747 #define PMU_4369_VREG_6_MEMLPLDO_POWER_UP_MASK (1u << 3u) 2748 #define PMU_4369_VREG_6_MEMLPLDO_POWER_UP_SHIFT 3u 2749 2750 #define PMU_4369_VREG_7_PMU_FORCE_HP_MODE_MASK (1u << 27u) 2751 #define PMU_4369_VREG_7_PMU_FORCE_HP_MODE_SHIFT 27u 2752 #define PMU_4369_VREG_7_WL_PMU_LP_MODE_MASK (1u << 28u) 2753 #define PMU_4369_VREG_7_WL_PMU_LP_MODE_SHIFT 28u 2754 #define PMU_4369_VREG_7_WL_PMU_LV_MODE_MASK (1u << 29u) 2755 #define PMU_4369_VREG_7_WL_PMU_LV_MODE_SHIFT 29u 2756 2757 #define PMU_4369_VREG8_ASR_OVADJ_LPPFM_MASK BCM_MASK32(4, 0) 2758 #define PMU_4369_VREG8_ASR_OVADJ_LPPFM_SHIFT 0u 2759 2760 #define PMU_4369_VREG13_RSRC_EN_ASR_MASK4_MASK BCM_MASK32(10, 9) 2761 #define PMU_4369_VREG13_RSRC_EN_ASR_MASK4_SHIFT 9u 2762 2763 #define PMU_4369_VREG14_RSRC_EN_CSR_MASK0_MASK (1u << 23u) 2764 #define PMU_4369_VREG14_RSRC_EN_CSR_MASK0_SHIFT 23u 2765 2766 #define PMU_4369_VREG16_RSRC0_CBUCK_MODE_MASK BCM_MASK32(2, 0) 2767 #define PMU_4369_VREG16_RSRC0_CBUCK_MODE_SHIFT 0u 2768 #define PMU_4369_VREG16_RSRC0_ABUCK_MODE_MASK BCM_MASK32(17, 15) 2769 #define PMU_4369_VREG16_RSRC0_ABUCK_MODE_SHIFT 15u 2770 #define PMU_4369_VREG16_RSRC1_ABUCK_MODE_MASK BCM_MASK32(20, 18) 2771 #define PMU_4369_VREG16_RSRC1_ABUCK_MODE_SHIFT 18u 2772 2773 /* 4364 related VREG masks */ 2774 #define PMU_4364_VREG3_DISABLE_WPT_REG_ON_PULL_DOWN (1 << 11) 2775 2776 #define PMU_4364_VREG4_MEMLPLDO_PU_ON (1 << 31) 2777 #define PMU_4364_VREG4_LPLPDO_ADJ (3 << 16) 2778 #define PMU_4364_VREG4_LPLPDO_ADJ_MASK (3 << 16) 2779 #define PMU_4364_VREG5_MAC_CLK_1x1_AUTO (0x1 << 18) 2780 #define PMU_4364_VREG5_SR_AUTO (0x1 << 20) 2781 #define PMU_4364_VREG5_BT_PWM_MASK (0x1 << 21) 2782 #define PMU_4364_VREG5_BT_AUTO (0x1 << 22) 2783 #define PMU_4364_VREG5_WL2CLB_DVFS_EN_MASK (0x1 << 23) 2784 #define PMU_4364_VREG5_BT_PWMK (0) 2785 #define PMU_4364_VREG5_WL2CLB_DVFS_EN (0) 2786 2787 #define PMU_4364_VREG6_BBPLL_AUTO (0x1 << 17) 2788 #define PMU_4364_VREG6_MINI_PMU_PWM (0x1 << 18) 2789 #define PMU_4364_VREG6_LNLDO_AUTO (0x1 << 21) 2790 #define PMU_4364_VREG6_PCIE_PWRDN_0_AUTO (0x1 << 23) 2791 #define PMU_4364_VREG6_PCIE_PWRDN_1_AUTO (0x1 << 25) 2792 #define PMU_4364_VREG6_MAC_CLK_3x3_PWM (0x1 << 27) 2793 #define PMU_4364_VREG6_ENABLE_FINE_CTRL (0x1 << 30) 2794 2795 #define PMU_4364_PLL0_DISABLE_CHANNEL6 (0x1 << 18) 2796 2797 #define CC_GCI1_REG (0x1) 2798 #define CC_GCI1_4364_IND_STATE_FOR_GPIO9_11 (0x0ccccccc) 2799 #define CC2_4364_SDIO_AOS_WAKEUP_MASK (1 << 24) 2800 #define CC2_4364_SDIO_AOS_WAKEUP_SHIFT (24) 2801 2802 #define CC6_4364_PCIE_CLKREQ_WAKEUP_MASK (1 << 4) 2803 #define CC6_4364_PCIE_CLKREQ_WAKEUP_SHIFT (4) 2804 #define CC6_4364_PMU_WAKEUP_ALPAVAIL_MASK (1 << 6) 2805 #define CC6_4364_PMU_WAKEUP_ALPAVAIL_SHIFT (6) 2806 2807 #define CST4364_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */ 2808 #define CST4364_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */ 2809 #define CST4364_SPROM_PRESENT 0x00000010 2810 2811 #define PMU_4364_MACCORE_0_RES_REQ_MASK 0x3FCBF7FF 2812 #define PMU_4364_MACCORE_1_RES_REQ_MASK 0x7FFB3647 2813 2814 #define PMU_4364_RSDB_MODE (0) 2815 #define PMU_4364_1x1_MODE (1) 2816 #define PMU_4364_3x3_MODE (2) 2817 2818 #define PMU_4364_MAX_MASK_1x1 (0x7FFF3E47) 2819 #define PMU_4364_MAX_MASK_RSDB (0x7FFFFFFF) 2820 #define PMU_4364_MAX_MASK_3x3 (0x3FCFFFFF) 2821 2822 #define PMU_4364_SAVE_RESTORE_UPDNTIME_1x1 (0xC000C) 2823 #define PMU_4364_SAVE_RESTORE_UPDNTIME_3x3 (0xF000F) 2824 2825 #define FORCE_CLK_ON 1 2826 #define FORCE_CLK_OFF 0 2827 2828 #define PMU1_PLL0_SWITCH_MACCLOCK_120MHZ (0) 2829 #define PMU1_PLL0_SWITCH_MACCLOCK_160MHZ (1) 2830 #define TSF_CLK_FRAC_L_4364_120MHZ 0x8889 2831 #define TSF_CLK_FRAC_H_4364_120MHZ 0x8 2832 #define TSF_CLK_FRAC_L_4364_160MHZ 0x6666 2833 #define TSF_CLK_FRAC_H_4364_160MHZ 0x6 2834 #define PMU1_PLL0_PC1_M2DIV_VALUE_120MHZ 8 2835 #define PMU1_PLL0_PC1_M2DIV_VALUE_160MHZ 6 2836 2837 /* 4347/4369 Related */ 2838 2839 /* 2840 * PMU VREG Definitions: 2841 * http://confluence.broadcom.com/display/WLAN/BCM4347+PMU+Vreg+Control+Register 2842 * http://confluence.broadcom.com/display/WLAN/BCM4369+PMU+Vreg+Control+Register 2843 */ 2844 /* PMU VREG4 */ 2845 #define PMU_28NM_VREG4_WL_LDO_CNTL_EN (0x1 << 10) 2846 2847 /* PMU VREG6 */ 2848 #define PMU_28NM_VREG6_BTLDO3P3_PU (0x1 << 12) 2849 2850 /* PMU resources */ 2851 #define RES4347_MEMLPLDO_PU 0 2852 #define RES4347_AAON 1 2853 #define RES4347_PMU_SLEEP 2 2854 #define RES4347_RESERVED_3 3 2855 #define RES4347_LDO3P3_PU 4 2856 #define RES4347_FAST_LPO_AVAIL 5 2857 #define RES4347_XTAL_PU 6 2858 #define RES4347_XTAL_STABLE 7 2859 #define RES4347_PWRSW_DIG 8 2860 #define RES4347_SR_DIG 9 2861 #define RES4347_SLEEP_DIG 10 2862 #define RES4347_PWRSW_AUX 11 2863 #define RES4347_SR_AUX 12 2864 #define RES4347_SLEEP_AUX 13 2865 #define RES4347_PWRSW_MAIN 14 2866 #define RES4347_SR_MAIN 15 2867 #define RES4347_SLEEP_MAIN 16 2868 #define RES4347_CORE_RDY_DIG 17 2869 #define RES4347_CORE_RDY_AUX 18 2870 #define RES4347_ALP_AVAIL 19 2871 #define RES4347_RADIO_AUX_PU 20 2872 #define RES4347_MINIPMU_AUX_PU 21 2873 #define RES4347_CORE_RDY_MAIN 22 2874 #define RES4347_RADIO_MAIN_PU 23 2875 #define RES4347_MINIPMU_MAIN_PU 24 2876 #define RES4347_PCIE_EP_PU 25 2877 #define RES4347_COLD_START_WAIT 26 2878 #define RES4347_ARMHTAVAIL 27 2879 #define RES4347_HT_AVAIL 28 2880 #define RES4347_MACPHY_AUX_CLK_AVAIL 29 2881 #define RES4347_MACPHY_MAIN_CLK_AVAIL 30 2882 #define RES4347_RESERVED_31 31 2883 2884 /* 4369 PMU Resources */ 2885 #define RES4369_DUMMY 0 2886 #define RES4369_ABUCK 1 2887 #define RES4369_PMU_SLEEP 2 2888 #define RES4369_MISCLDO 3 2889 #define RES4369_LDO3P3 4 2890 #define RES4369_FAST_LPO_AVAIL 5 2891 #define RES4369_XTAL_PU 6 2892 #define RES4369_XTAL_STABLE 7 2893 #define RES4369_PWRSW_DIG 8 2894 #define RES4369_SR_DIG 9 2895 #define RES4369_SLEEP_DIG 10 2896 #define RES4369_PWRSW_AUX 11 2897 #define RES4369_SR_AUX 12 2898 #define RES4369_SLEEP_AUX 13 2899 #define RES4369_PWRSW_MAIN 14 2900 #define RES4369_SR_MAIN 15 2901 #define RES4369_SLEEP_MAIN 16 2902 #define RES4369_DIG_CORE_RDY 17 2903 #define RES4369_CORE_RDY_AUX 18 2904 #define RES4369_ALP_AVAIL 19 2905 #define RES4369_RADIO_AUX_PU 20 2906 #define RES4369_MINIPMU_AUX_PU 21 2907 #define RES4369_CORE_RDY_MAIN 22 2908 #define RES4369_RADIO_MAIN_PU 23 2909 #define RES4369_MINIPMU_MAIN_PU 24 2910 #define RES4369_PCIE_EP_PU 25 2911 #define RES4369_COLD_START_WAIT 26 2912 #define RES4369_ARMHTAVAIL 27 2913 #define RES4369_HT_AVAIL 28 2914 #define RES4369_MACPHY_AUX_CLK_AVAIL 29 2915 #define RES4369_MACPHY_MAIN_CLK_AVAIL 30 2916 2917 /* chip status */ 2918 #define CST4347_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */ 2919 #define CST4347_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */ 2920 #define CST4347_JTAG_STRAP_ENABLED(cs) (((cs) & (1 << 20)) != 0) /* JTAG strap st */ 2921 #define CST4347_SPROM_PRESENT 0x00000010 2922 2923 /* GCI chip status */ 2924 #define GCI_CS_4347_FLL1MHZ_LOCK_MASK (1 << 1) 2925 2926 /* GCI chip control registers */ 2927 #define GCI_CC7_AAON_BYPASS_PWRSW_SEL 13 2928 #define GCI_CC7_AAON_BYPASS_PWRSW_SEQ_ON 14 2929 2930 /* PMU chip control registers */ 2931 #define CC2_4347_VASIP_MEMLPLDO_VDDB_OFF_MASK (1 << 11) 2932 #define CC2_4347_VASIP_MEMLPLDO_VDDB_OFF_SHIFT 11 2933 #define CC2_4347_MAIN_MEMLPLDO_VDDB_OFF_MASK (1 << 12) 2934 #define CC2_4347_MAIN_MEMLPLDO_VDDB_OFF_SHIFT 12 2935 #define CC2_4347_AUX_MEMLPLDO_VDDB_OFF_MASK (1 << 13) 2936 #define CC2_4347_AUX_MEMLPLDO_VDDB_OFF_SHIFT 13 2937 #define CC2_4347_VASIP_VDDRET_ON_MASK (1 << 14) 2938 #define CC2_4347_VASIP_VDDRET_ON_SHIFT 14 2939 #define CC2_4347_MAIN_VDDRET_ON_MASK (1 << 15) 2940 #define CC2_4347_MAIN_VDDRET_ON_SHIFT 15 2941 #define CC2_4347_AUX_VDDRET_ON_MASK (1 << 16) 2942 #define CC2_4347_AUX_VDDRET_ON_SHIFT 16 2943 #define CC2_4347_GCI2WAKE_MASK (1 << 31) 2944 #define CC2_4347_GCI2WAKE_SHIFT 31 2945 2946 #define CC2_4347_SDIO_AOS_WAKEUP_MASK (1 << 24) 2947 #define CC2_4347_SDIO_AOS_WAKEUP_SHIFT 24 2948 2949 #define CC4_4347_LHL_TIMER_SELECT (1 << 0) 2950 2951 #define CC6_4347_PWROK_WDT_EN_IN_MASK (1 << 6) 2952 #define CC6_4347_PWROK_WDT_EN_IN_SHIFT 6 2953 2954 #define CC6_4347_SDIO_AOS_CHIP_WAKEUP_MASK (1 << 24) 2955 #define CC6_4347_SDIO_AOS_CHIP_WAKEUP_SHIFT 24 2956 2957 #define PCIE_GPIO1_GPIO_PIN CC_GCI_GPIO_0 2958 #define PCIE_PERST_GPIO_PIN CC_GCI_GPIO_1 2959 #define PCIE_CLKREQ_GPIO_PIN CC_GCI_GPIO_2 2960 2961 #define VREG5_4347_MEMLPLDO_ADJ_MASK 0xF0000000 2962 #define VREG5_4347_MEMLPLDO_ADJ_SHIFT 28 2963 #define VREG5_4347_LPLDO_ADJ_MASK 0x00F00000 2964 #define VREG5_4347_LPLDO_ADJ_SHIFT 20 2965 2966 /* lpldo/memlpldo voltage */ 2967 #define PMU_VREG5_LPLDO_VOLT_0_88 0xf /* 0.88v */ 2968 #define PMU_VREG5_LPLDO_VOLT_0_86 0xe /* 0.86v */ 2969 #define PMU_VREG5_LPLDO_VOLT_0_84 0xd /* 0.84v */ 2970 #define PMU_VREG5_LPLDO_VOLT_0_82 0xc /* 0.82v */ 2971 #define PMU_VREG5_LPLDO_VOLT_0_80 0xb /* 0.80v */ 2972 #define PMU_VREG5_LPLDO_VOLT_0_78 0xa /* 0.78v */ 2973 #define PMU_VREG5_LPLDO_VOLT_0_76 0x9 /* 0.76v */ 2974 #define PMU_VREG5_LPLDO_VOLT_0_74 0x8 /* 0.74v */ 2975 #define PMU_VREG5_LPLDO_VOLT_0_72 0x7 /* 0.72v */ 2976 #define PMU_VREG5_LPLDO_VOLT_1_10 0x6 /* 1.10v */ 2977 #define PMU_VREG5_LPLDO_VOLT_1_00 0x5 /* 1.00v */ 2978 #define PMU_VREG5_LPLDO_VOLT_0_98 0x4 /* 0.98v */ 2979 #define PMU_VREG5_LPLDO_VOLT_0_96 0x3 /* 0.96v */ 2980 #define PMU_VREG5_LPLDO_VOLT_0_94 0x2 /* 0.94v */ 2981 #define PMU_VREG5_LPLDO_VOLT_0_92 0x1 /* 0.92v */ 2982 #define PMU_VREG5_LPLDO_VOLT_0_90 0x0 /* 0.90v */ 2983 2984 /* Save/Restore engine */ 2985 2986 #define BM_ADDR_TO_SR_ADDR(bmaddr) ((bmaddr) >> 9) 2987 2988 /* Txfifo is 512KB for main core and 128KB for aux core 2989 * We use first 12kB (0x3000) in BMC buffer for template in main core and 2990 * 6.5kB (0x1A00) in aux core, followed by ASM code 2991 */ 2992 #define SR_ASM_ADDR_MAIN_4347 (0x18) 2993 #define SR_ASM_ADDR_AUX_4347 (0xd) 2994 #define SR_ASM_ADDR_DIG_4347 (0x0) 2995 2996 #define SR_ASM_ADDR_MAIN_4369 BM_ADDR_TO_SR_ADDR(0xC00) 2997 #define SR_ASM_ADDR_AUX_4369 BM_ADDR_TO_SR_ADDR(0xC00) 2998 #define SR_ASM_ADDR_DIG_4369 (0x0) 2999 3000 /* 512 bytes block */ 3001 #define SR_ASM_ADDR_BLK_SIZE_SHIFT 9 3002 3003 /* SR Control0 bits */ 3004 #define SR0_SR_ENG_EN_MASK 0x1 3005 #define SR0_SR_ENG_EN_SHIFT 0 3006 #define SR0_SR_ENG_CLK_EN (1 << 1) 3007 #define SR0_RSRC_TRIGGER (0xC << 2) 3008 #define SR0_WD_MEM_MIN_DIV (0x3 << 6) 3009 #define SR0_INVERT_SR_CLK (1 << 11) 3010 #define SR0_MEM_STBY_ALLOW (1 << 16) 3011 #define SR0_ENABLE_SR_ILP (1 << 17) 3012 #define SR0_ENABLE_SR_ALP (1 << 18) 3013 #define SR0_ENABLE_SR_HT (1 << 19) 3014 #define SR0_ALLOW_PIC (3 << 20) 3015 #define SR0_ENB_PMU_MEM_DISABLE (1 << 30) 3016 3017 /* SR Control0 bits for 4369 */ 3018 #define SR0_4369_SR_ENG_EN_MASK 0x1 3019 #define SR0_4369_SR_ENG_EN_SHIFT 0 3020 #define SR0_4369_SR_ENG_CLK_EN (1 << 1) 3021 #define SR0_4369_RSRC_TRIGGER (0xC << 2) 3022 #define SR0_4369_WD_MEM_MIN_DIV (0x2 << 6) 3023 #define SR0_4369_INVERT_SR_CLK (1 << 11) 3024 #define SR0_4369_MEM_STBY_ALLOW (1 << 16) 3025 #define SR0_4369_ENABLE_SR_ILP (1 << 17) 3026 #define SR0_4369_ENABLE_SR_ALP (1 << 18) 3027 #define SR0_4369_ENABLE_SR_HT (1 << 19) 3028 #define SR0_4369_ALLOW_PIC (3 << 20) 3029 #define SR0_4369_ENB_PMU_MEM_DISABLE (1 << 30) 3030 /* =========== LHL regs =========== */ 3031 /* 4369 LHL register settings */ 3032 #define LHL4369_UP_CNT 0 3033 #define LHL4369_DN_CNT 2 3034 #define LHL4369_PWRSW_EN_DWN_CNT (LHL4369_DN_CNT + 2) 3035 #define LHL4369_ISO_EN_DWN_CNT (LHL4369_PWRSW_EN_DWN_CNT + 3) 3036 #define LHL4369_SLB_EN_DWN_CNT (LHL4369_ISO_EN_DWN_CNT + 1) 3037 #define LHL4369_ASR_CLK4M_DIS_DWN_CNT (LHL4369_DN_CNT) 3038 #define LHL4369_ASR_LPPFM_MODE_DWN_CNT (LHL4369_DN_CNT) 3039 #define LHL4369_ASR_MODE_SEL_DWN_CNT (LHL4369_DN_CNT) 3040 #define LHL4369_ASR_MANUAL_MODE_DWN_CNT (LHL4369_DN_CNT) 3041 #define LHL4369_ASR_ADJ_DWN_CNT (LHL4369_DN_CNT) 3042 #define LHL4369_ASR_OVERI_DIS_DWN_CNT (LHL4369_DN_CNT) 3043 #define LHL4369_ASR_TRIM_ADJ_DWN_CNT (LHL4369_DN_CNT) 3044 #define LHL4369_VDDC_SW_DIS_DWN_CNT (LHL4369_SLB_EN_DWN_CNT + 1) 3045 #define LHL4369_VMUX_ASR_SEL_DWN_CNT (LHL4369_VDDC_SW_DIS_DWN_CNT + 1) 3046 #define LHL4369_CSR_ADJ_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) 3047 #define LHL4369_CSR_MODE_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) 3048 #define LHL4369_CSR_OVERI_DIS_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) 3049 #define LHL4369_HPBG_CHOP_DIS_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) 3050 #define LHL4369_SRBG_REF_SEL_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) 3051 #define LHL4369_PFM_PWR_SLICE_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) 3052 #define LHL4369_CSR_TRIM_ADJ_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) 3053 #define LHL4369_CSR_VOLTAGE_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) 3054 #define LHL4369_HPBG_PU_EN_DWN_CNT (LHL4369_CSR_MODE_DWN_CNT + 1) 3055 3056 #define LHL4369_HPBG_PU_EN_UP_CNT (LHL4369_UP_CNT + 1) 3057 #define LHL4369_CSR_ADJ_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) 3058 #define LHL4369_CSR_MODE_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) 3059 #define LHL4369_CSR_OVERI_DIS_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) 3060 #define LHL4369_HPBG_CHOP_DIS_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) 3061 #define LHL4369_SRBG_REF_SEL_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) 3062 #define LHL4369_PFM_PWR_SLICE_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) 3063 #define LHL4369_CSR_TRIM_ADJ_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) 3064 #define LHL4369_CSR_VOLTAGE_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) 3065 #define LHL4369_VMUX_ASR_SEL_UP_CNT (LHL4369_CSR_MODE_UP_CNT + 1) 3066 #define LHL4369_VDDC_SW_DIS_UP_CNT (LHL4369_VMUX_ASR_SEL_UP_CNT + 1) 3067 #define LHL4369_SLB_EN_UP_CNT (LHL4369_VDDC_SW_DIS_UP_CNT + 8) 3068 #define LHL4369_ISO_EN_UP_CNT (LHL4369_SLB_EN_UP_CNT + 1) 3069 #define LHL4369_PWRSW_EN_UP_CNT (LHL4369_ISO_EN_UP_CNT + 3) 3070 #define LHL4369_ASR_ADJ_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) 3071 #define LHL4369_ASR_CLK4M_DIS_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) 3072 #define LHL4369_ASR_LPPFM_MODE_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) 3073 #define LHL4369_ASR_MODE_SEL_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) 3074 #define LHL4369_ASR_MANUAL_MODE_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) 3075 #define LHL4369_ASR_OVERI_DIS_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) 3076 #define LHL4369_ASR_TRIM_ADJ_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) 3077 3078 /* MacResourceReqTimer0/1 */ 3079 #define MAC_RSRC_REQ_TIMER_INT_ENAB_SHIFT 24 3080 #define MAC_RSRC_REQ_TIMER_FORCE_ALP_SHIFT 26 3081 #define MAC_RSRC_REQ_TIMER_FORCE_HT_SHIFT 27 3082 #define MAC_RSRC_REQ_TIMER_FORCE_HQ_SHIFT 28 3083 #define MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT 29 3084 3085 /* for pmu rev32 and higher */ 3086 #define PMU32_MAC_MAIN_RSRC_REQ_TIMER ((1 << MAC_RSRC_REQ_TIMER_INT_ENAB_SHIFT) | \ 3087 (1 << MAC_RSRC_REQ_TIMER_FORCE_ALP_SHIFT) | \ 3088 (1 << MAC_RSRC_REQ_TIMER_FORCE_HT_SHIFT) | \ 3089 (1 << MAC_RSRC_REQ_TIMER_FORCE_HQ_SHIFT) | \ 3090 (0 << MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT)) 3091 3092 #define PMU32_MAC_AUX_RSRC_REQ_TIMER ((1 << MAC_RSRC_REQ_TIMER_INT_ENAB_SHIFT) | \ 3093 (1 << MAC_RSRC_REQ_TIMER_FORCE_ALP_SHIFT) | \ 3094 (1 << MAC_RSRC_REQ_TIMER_FORCE_HT_SHIFT) | \ 3095 (1 << MAC_RSRC_REQ_TIMER_FORCE_HQ_SHIFT) | \ 3096 (0 << MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT)) 3097 3098 /* 4369 related: 4369 parameters 3099 * http://www.sj.broadcom.com/projects/BCM4369/gallery_backend.RC6.0/design/backplane/pmu_params.xls 3100 */ 3101 #define RES4369_DUMMY 0 3102 #define RES4369_ABUCK 1 3103 #define RES4369_PMU_SLEEP 2 3104 #define RES4369_MISCLDO_PU 3 3105 #define RES4369_LDO3P3_PU 4 3106 #define RES4369_FAST_LPO_AVAIL 5 3107 #define RES4369_XTAL_PU 6 3108 #define RES4369_XTAL_STABLE 7 3109 #define RES4369_PWRSW_DIG 8 3110 #define RES4369_SR_DIG 9 3111 #define RES4369_SLEEP_DIG 10 3112 #define RES4369_PWRSW_AUX 11 3113 #define RES4369_SR_AUX 12 3114 #define RES4369_SLEEP_AUX 13 3115 #define RES4369_PWRSW_MAIN 14 3116 #define RES4369_SR_MAIN 15 3117 #define RES4369_SLEEP_MAIN 16 3118 #define RES4369_DIG_CORE_RDY 17 3119 #define RES4369_CORE_RDY_AUX 18 3120 #define RES4369_ALP_AVAIL 19 3121 #define RES4369_RADIO_AUX_PU 20 3122 #define RES4369_MINIPMU_AUX_PU 21 3123 #define RES4369_CORE_RDY_MAIN 22 3124 #define RES4369_RADIO_MAIN_PU 23 3125 #define RES4369_MINIPMU_MAIN_PU 24 3126 #define RES4369_PCIE_EP_PU 25 3127 #define RES4369_COLD_START_WAIT 26 3128 #define RES4369_ARMHTAVAIL 27 3129 #define RES4369_HT_AVAIL 28 3130 #define RES4369_MACPHY_AUX_CLK_AVAIL 29 3131 #define RES4369_MACPHY_MAIN_CLK_AVAIL 30 3132 #define RES4369_RESERVED_31 31 3133 3134 #define CST4369_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */ 3135 #define CST4369_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */ 3136 #define CST4369_SPROM_PRESENT 0x00000010 3137 3138 #define PMU_4369_MACCORE_0_RES_REQ_MASK 0x3FCBF7FF 3139 #define PMU_4369_MACCORE_1_RES_REQ_MASK 0x7FFB3647 3140 3141 /* 43430 PMU resources based on pmu_params.xls */ 3142 #define RES43430_LPLDO_PU 0 3143 #define RES43430_BG_PU 1 3144 #define RES43430_PMU_SLEEP 2 3145 #define RES43430_RSVD_3 3 3146 #define RES43430_CBUCK_LPOM_PU 4 3147 #define RES43430_CBUCK_PFM_PU 5 3148 #define RES43430_COLD_START_WAIT 6 3149 #define RES43430_RSVD_7 7 3150 #define RES43430_LNLDO_PU 8 3151 #define RES43430_RSVD_9 9 3152 #define RES43430_LDO3P3_PU 10 3153 #define RES43430_OTP_PU 11 3154 #define RES43430_XTAL_PU 12 3155 #define RES43430_SR_CLK_START 13 3156 #define RES43430_LQ_AVAIL 14 3157 #define RES43430_LQ_START 15 3158 #define RES43430_RSVD_16 16 3159 #define RES43430_WL_CORE_RDY 17 3160 #define RES43430_ILP_REQ 18 3161 #define RES43430_ALP_AVAIL 19 3162 #define RES43430_MINI_PMU 20 3163 #define RES43430_RADIO_PU 21 3164 #define RES43430_SR_CLK_STABLE 22 3165 #define RES43430_SR_SAVE_RESTORE 23 3166 #define RES43430_SR_PHY_PWRSW 24 3167 #define RES43430_SR_VDDM_PWRSW 25 3168 #define RES43430_SR_SUBCORE_PWRSW 26 3169 #define RES43430_SR_SLEEP 27 3170 #define RES43430_HT_START 28 3171 #define RES43430_HT_AVAIL 29 3172 #define RES43430_MACPHY_CLK_AVAIL 30 3173 3174 /* 43430 chip status bits */ 3175 #define CST43430_SDIO_MODE 0x00000001 3176 #define CST43430_GSPI_MODE 0x00000002 3177 #define CST43430_RSRC_INIT_MODE_0 0x00000080 3178 #define CST43430_RSRC_INIT_MODE_1 0x00000100 3179 #define CST43430_SEL0_SDIO 0x00000200 3180 #define CST43430_SEL1_SDIO 0x00000400 3181 #define CST43430_SEL2_SDIO 0x00000800 3182 #define CST43430_BBPLL_LOCKED 0x00001000 3183 #define CST43430_DBG_INST_DETECT 0x00004000 3184 #define CST43430_CLB2WL_BT_READY 0x00020000 3185 #define CST43430_JTAG_MODE 0x00100000 3186 #define CST43430_HOST_IFACE 0x00400000 3187 #define CST43430_TRIM_EN 0x00800000 3188 #define CST43430_DIN_PACKAGE_OPTION 0x10000000 3189 3190 #define PMU43430_PLL0_PC2_P1DIV_MASK 0x0000000f 3191 #define PMU43430_PLL0_PC2_P1DIV_SHIFT 0 3192 #define PMU43430_PLL0_PC2_NDIV_INT_MASK 0x0000ff80 3193 #define PMU43430_PLL0_PC2_NDIV_INT_SHIFT 7 3194 #define PMU43430_PLL0_PC4_MDIV2_MASK 0x0000ff00 3195 #define PMU43430_PLL0_PC4_MDIV2_SHIFT 8 3196 3197 /* 43430 chip SR definitions */ 3198 #define SRAM_43430_SR_ASM_ADDR 0x7f800 3199 #define CC_SR1_43430_SR_ASM_ADDR ((SRAM_43430_SR_ASM_ADDR - 0x60000) >> 8) 3200 3201 /* 43430 PMU Chip Control bits */ 3202 #define CC2_43430_SDIO_AOS_WAKEUP_MASK (1 << 24) 3203 #define CC2_43430_SDIO_AOS_WAKEUP_SHIFT (24) 3204 3205 #define PMU_MACCORE_0_RES_REQ_TIMER 0x1d000000 3206 #define PMU_MACCORE_0_RES_REQ_MASK 0x5FF2364F 3207 3208 #define PMU43012_MAC_RES_REQ_TIMER 0x1D000000 3209 #define PMU43012_MAC_RES_REQ_MASK 0x3FBBF7FF 3210 3211 #define PMU_MACCORE_1_RES_REQ_TIMER 0x1d000000 3212 #define PMU_MACCORE_1_RES_REQ_MASK 0x5FF2364F 3213 3214 /* defines to detect active host interface in use */ 3215 #define CHIP_HOSTIF_PCIEMODE 0x1 3216 #define CHIP_HOSTIF_USBMODE 0x2 3217 #define CHIP_HOSTIF_SDIOMODE 0x4 3218 #define CHIP_HOSTIF_PCIE(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_PCIEMODE) 3219 #define CHIP_HOSTIF_USB(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_USBMODE) 3220 #define CHIP_HOSTIF_SDIO(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_SDIOMODE) 3221 3222 /* 4335 resources */ 3223 #define RES4335_LPLDO_PO 0 3224 #define RES4335_PMU_BG_PU 1 3225 #define RES4335_PMU_SLEEP 2 3226 #define RES4335_RSVD_3 3 3227 #define RES4335_CBUCK_LPOM_PU 4 3228 #define RES4335_CBUCK_PFM_PU 5 3229 #define RES4335_RSVD_6 6 3230 #define RES4335_RSVD_7 7 3231 #define RES4335_LNLDO_PU 8 3232 #define RES4335_XTALLDO_PU 9 3233 #define RES4335_LDO3P3_PU 10 3234 #define RES4335_OTP_PU 11 3235 #define RES4335_XTAL_PU 12 3236 #define RES4335_SR_CLK_START 13 3237 #define RES4335_LQ_AVAIL 14 3238 #define RES4335_LQ_START 15 3239 #define RES4335_RSVD_16 16 3240 #define RES4335_WL_CORE_RDY 17 3241 #define RES4335_ILP_REQ 18 3242 #define RES4335_ALP_AVAIL 19 3243 #define RES4335_MINI_PMU 20 3244 #define RES4335_RADIO_PU 21 3245 #define RES4335_SR_CLK_STABLE 22 3246 #define RES4335_SR_SAVE_RESTORE 23 3247 #define RES4335_SR_PHY_PWRSW 24 3248 #define RES4335_SR_VDDM_PWRSW 25 3249 #define RES4335_SR_SUBCORE_PWRSW 26 3250 #define RES4335_SR_SLEEP 27 3251 #define RES4335_HT_START 28 3252 #define RES4335_HT_AVAIL 29 3253 #define RES4335_MACPHY_CLKAVAIL 30 3254 3255 /* 4335 Chip specific ChipStatus register bits */ 3256 #define CST4335_SPROM_MASK 0x00000020 3257 #define CST4335_SFLASH_MASK 0x00000040 3258 #define CST4335_RES_INIT_MODE_SHIFT 7 3259 #define CST4335_RES_INIT_MODE_MASK 0x00000180 3260 #define CST4335_CHIPMODE_MASK 0xF 3261 #define CST4335_CHIPMODE_SDIOD(cs) (((cs) & (1 << 0)) != 0) /* SDIO */ 3262 #define CST4335_CHIPMODE_GSPI(cs) (((cs) & (1 << 1)) != 0) /* gSPI */ 3263 #define CST4335_CHIPMODE_USB20D(cs) (((cs) & (1 << 2)) != 0) /**< HSIC || USBDA */ 3264 #define CST4335_CHIPMODE_PCIE(cs) (((cs) & (1 << 3)) != 0) /* PCIE */ 3265 3266 /* 4335 Chip specific ChipControl1 register bits */ 3267 #define CCTRL1_4335_GPIO_SEL (1 << 0) /* 1=select GPIOs to be muxed out */ 3268 #define CCTRL1_4335_SDIO_HOST_WAKE (1 << 2) /* SDIO: 1=configure GPIO0 for host wake */ 3269 3270 /* 4335 Chip specific ChipControl2 register bits */ 3271 #define CCTRL2_4335_AOSBLOCK (1 << 30) 3272 #define CCTRL2_4335_PMUWAKE (1 << 31) 3273 #define PATCHTBL_SIZE (0x800) 3274 #define CR4_4335_RAM_BASE (0x180000) 3275 #define CR4_4345_LT_C0_RAM_BASE (0x1b0000) 3276 #define CR4_4345_GE_C0_RAM_BASE (0x198000) 3277 #define CR4_4349_RAM_BASE (0x180000) 3278 #define CR4_4349_RAM_BASE_FROM_REV_9 (0x160000) 3279 #define CR4_4350_RAM_BASE (0x180000) 3280 #define CR4_4360_RAM_BASE (0x0) 3281 #define CR4_43602_RAM_BASE (0x180000) 3282 #define CA7_4365_RAM_BASE (0x200000) 3283 3284 #define CR4_4347_RAM_BASE (0x170000) 3285 #define CR4_4362_RAM_BASE (0x170000) 3286 #define CR4_4369_RAM_BASE (0x170000) 3287 #define CR4_4377_RAM_BASE (0x170000) 3288 #define CR4_43751_RAM_BASE (0x170000) 3289 #define CR4_43752_RAM_BASE (0x170000) 3290 #define CA7_4367_RAM_BASE (0x200000) 3291 #define CR4_4378_RAM_BASE (0x352000) 3292 3293 /* 4335 chip OTP present & OTP select bits. */ 3294 #define SPROM4335_OTP_SELECT 0x00000010 3295 #define SPROM4335_OTP_PRESENT 0x00000020 3296 3297 /* 4335 GCI specific bits. */ 3298 #define CC4335_GCI_STRAP_OVERRIDE_SFLASH_PRESENT (1 << 24) 3299 #define CC4335_GCI_STRAP_OVERRIDE_SFLASH_TYPE 25 3300 #define CC4335_GCI_FUNC_SEL_PAD_SDIO 0x00707770 3301 3302 /* SFLASH clkdev specific bits. */ 3303 #define CC4335_SFLASH_CLKDIV_MASK 0x1F000000 3304 #define CC4335_SFLASH_CLKDIV_SHIFT 25 3305 3306 /* 4335 OTP bits for SFLASH. */ 3307 #define CC4335_SROM_OTP_SFLASH 40 3308 #define CC4335_SROM_OTP_SFLASH_PRESENT 0x1 3309 #define CC4335_SROM_OTP_SFLASH_TYPE 0x2 3310 #define CC4335_SROM_OTP_SFLASH_CLKDIV_MASK 0x003C 3311 #define CC4335_SROM_OTP_SFLASH_CLKDIV_SHIFT 2 3312 3313 /* 4335 chip OTP present & OTP select bits. */ 3314 #define SPROM4335_OTP_SELECT 0x00000010 3315 #define SPROM4335_OTP_PRESENT 0x00000020 3316 3317 /* 4335 GCI specific bits. */ 3318 #define CC4335_GCI_STRAP_OVERRIDE_SFLASH_PRESENT (1 << 24) 3319 #define CC4335_GCI_STRAP_OVERRIDE_SFLASH_TYPE 25 3320 #define CC4335_GCI_FUNC_SEL_PAD_SDIO 0x00707770 3321 3322 /* SFLASH clkdev specific bits. */ 3323 #define CC4335_SFLASH_CLKDIV_MASK 0x1F000000 3324 #define CC4335_SFLASH_CLKDIV_SHIFT 25 3325 3326 /* 4335 OTP bits for SFLASH. */ 3327 #define CC4335_SROM_OTP_SFLASH 40 3328 #define CC4335_SROM_OTP_SFLASH_PRESENT 0x1 3329 #define CC4335_SROM_OTP_SFLASH_TYPE 0x2 3330 #define CC4335_SROM_OTP_SFLASH_CLKDIV_MASK 0x003C 3331 #define CC4335_SROM_OTP_SFLASH_CLKDIV_SHIFT 2 3332 3333 /* 4335 resources--END */ 3334 3335 /* 43012 PMU resources based on pmu_params.xls - Start */ 3336 #define RES43012_MEMLPLDO_PU 0 3337 #define RES43012_PMU_SLEEP 1 3338 #define RES43012_FAST_LPO 2 3339 #define RES43012_BTLPO_3P3 3 3340 #define RES43012_SR_POK 4 3341 #define RES43012_DUMMY_PWRSW 5 3342 #define RES43012_DUMMY_LDO3P3 6 3343 #define RES43012_DUMMY_BT_LDO3P3 7 3344 #define RES43012_DUMMY_RADIO 8 3345 #define RES43012_VDDB_VDDRET 9 3346 #define RES43012_HV_LDO3P3 10 3347 #define RES43012_OTP_PU 11 3348 #define RES43012_XTAL_PU 12 3349 #define RES43012_SR_CLK_START 13 3350 #define RES43012_XTAL_STABLE 14 3351 #define RES43012_FCBS 15 3352 #define RES43012_CBUCK_MODE 16 3353 #define RES43012_CORE_READY 17 3354 #define RES43012_ILP_REQ 18 3355 #define RES43012_ALP_AVAIL 19 3356 #define RES43012_RADIOLDO_1P8 20 3357 #define RES43012_MINI_PMU 21 3358 #define RES43012_UNUSED 22 3359 #define RES43012_SR_SAVE_RESTORE 23 3360 #define RES43012_PHY_PWRSW 24 3361 #define RES43012_VDDB_CLDO 25 3362 #define RES43012_SUBCORE_PWRSW 26 3363 #define RES43012_SR_SLEEP 27 3364 #define RES43012_HT_START 28 3365 #define RES43012_HT_AVAIL 29 3366 #define RES43012_MACPHY_CLK_AVAIL 30 3367 #define CST43012_SPROM_PRESENT 0x00000010 3368 3369 /* SR Control0 bits */ 3370 #define SR0_43012_SR_ENG_EN_MASK 0x1 3371 #define SR0_43012_SR_ENG_EN_SHIFT 0 3372 #define SR0_43012_SR_ENG_CLK_EN (1 << 1) 3373 #define SR0_43012_SR_RSRC_TRIGGER (0xC << 2) 3374 #define SR0_43012_SR_WD_MEM_MIN_DIV (0x3 << 6) 3375 #define SR0_43012_SR_MEM_STBY_ALLOW_MSK (1 << 16) 3376 #define SR0_43012_SR_MEM_STBY_ALLOW_SHIFT 16 3377 #define SR0_43012_SR_ENABLE_ILP (1 << 17) 3378 #define SR0_43012_SR_ENABLE_ALP (1 << 18) 3379 #define SR0_43012_SR_ENABLE_HT (1 << 19) 3380 #define SR0_43012_SR_ALLOW_PIC (3 << 20) 3381 #define SR0_43012_SR_PMU_MEM_DISABLE (1 << 30) 3382 #define CC_43012_VDDM_PWRSW_EN_MASK (1 << 20) 3383 #define CC_43012_VDDM_PWRSW_EN_SHIFT (20) 3384 #define CC_43012_SDIO_AOS_WAKEUP_MASK (1 << 24) 3385 #define CC_43012_SDIO_AOS_WAKEUP_SHIFT (24) 3386 3387 /* 43012 - offset at 5K */ 3388 #define SR1_43012_SR_INIT_ADDR_MASK 0x3ff 3389 #define SR1_43012_SR_ASM_ADDR 0xA 3390 3391 /* PLL usage in 43012 */ 3392 #define PMU43012_PLL0_PC0_NDIV_INT_MASK 0x0000003f 3393 #define PMU43012_PLL0_PC0_NDIV_INT_SHIFT 0 3394 #define PMU43012_PLL0_PC0_NDIV_FRAC_MASK 0xfffffc00 3395 #define PMU43012_PLL0_PC0_NDIV_FRAC_SHIFT 10 3396 #define PMU43012_PLL0_PC3_PDIV_MASK 0x00003c00 3397 #define PMU43012_PLL0_PC3_PDIV_SHIFT 10 3398 #define PMU43012_PLL_NDIV_FRAC_BITS 20 3399 #define PMU43012_PLL_P_DIV_SCALE_BITS 10 3400 3401 #define CCTL_43012_ARM_OFFCOUNT_MASK 0x00000003 3402 #define CCTL_43012_ARM_OFFCOUNT_SHIFT 0 3403 #define CCTL_43012_ARM_ONCOUNT_MASK 0x0000000c 3404 #define CCTL_43012_ARM_ONCOUNT_SHIFT 2 3405 3406 /* PMU Rev >= 30 */ 3407 #define PMU30_ALPCLK_ONEMHZ_ENAB 0x80000000 3408 3409 #define BCM7271_PMU30_ALPCLK_ONEMHZ_ENAB 0x00010000 3410 3411 /* 43012 PMU Chip Control Registers */ 3412 #define PMUCCTL02_43012_SUBCORE_PWRSW_FORCE_ON 0x00000010 3413 #define PMUCCTL02_43012_PHY_PWRSW_FORCE_ON 0x00000040 3414 #define PMUCCTL02_43012_LHL_TIMER_SELECT 0x00000800 3415 #define PMUCCTL02_43012_RFLDO3P3_PU_FORCE_ON 0x00008000 3416 #define PMUCCTL02_43012_WL2CDIG_I_PMU_SLEEP_ENAB 0x00010000 3417 #define PMUCCTL02_43012_BTLDO3P3_PU_FORCE_OFF (1 << 12) 3418 3419 #define PMUCCTL04_43012_BBPLL_ENABLE_PWRDN 0x00100000 3420 #define PMUCCTL04_43012_BBPLL_ENABLE_PWROFF 0x00200000 3421 #define PMUCCTL04_43012_FORCE_BBPLL_ARESET 0x00400000 3422 #define PMUCCTL04_43012_FORCE_BBPLL_DRESET 0x00800000 3423 #define PMUCCTL04_43012_FORCE_BBPLL_PWRDN 0x01000000 3424 #define PMUCCTL04_43012_FORCE_BBPLL_ISOONHIGH 0x02000000 3425 #define PMUCCTL04_43012_FORCE_BBPLL_PWROFF 0x04000000 3426 #define PMUCCTL04_43012_DISABLE_LQ_AVAIL 0x08000000 3427 #define PMUCCTL04_43012_DISABLE_HT_AVAIL 0x10000000 3428 #define PMUCCTL04_43012_USE_LOCK 0x20000000 3429 #define PMUCCTL04_43012_OPEN_LOOP_ENABLE 0x40000000 3430 #define PMUCCTL04_43012_FORCE_OPEN_LOOP 0x80000000 3431 #define PMUCCTL05_43012_DISABLE_SPM_CLK (1 << 8) 3432 #define PMUCCTL05_43012_RADIO_DIG_CLK_GATING_EN (1 << 14) 3433 #define PMUCCTL06_43012_GCI2RDIG_USE_ASYNCAPB (1 << 31) 3434 #define PMUCCTL08_43012_XTAL_CORE_SIZE_PMOS_NORMAL_MASK 0x00000FC0 3435 #define PMUCCTL08_43012_XTAL_CORE_SIZE_PMOS_NORMAL_SHIFT 6 3436 #define PMUCCTL08_43012_XTAL_CORE_SIZE_NMOS_NORMAL_MASK 0x00FC0000 3437 #define PMUCCTL08_43012_XTAL_CORE_SIZE_NMOS_NORMAL_SHIFT 18 3438 #define PMUCCTL08_43012_XTAL_SEL_BIAS_RES_NORMAL_MASK 0x07000000 3439 #define PMUCCTL08_43012_XTAL_SEL_BIAS_RES_NORMAL_SHIFT 24 3440 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK 0x0003F000 3441 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_NORMAL_SHIFT 12 3442 #define PMUCCTL09_43012_XTAL_CORESIZE_RES_BYPASS_NORMAL_MASK 0x00000038 3443 #define PMUCCTL09_43012_XTAL_CORESIZE_RES_BYPASS_NORMAL_SHIFT 3 3444 3445 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_MASK 0x00000FC0 3446 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_SHIFT 6 3447 /* during normal operation normal value is reduced for optimized power */ 3448 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_VAL 0x1F 3449 3450 #define PMUCCTL13_43012_FCBS_UP_TRIG_EN 0x00000400 3451 3452 #define PMUCCTL14_43012_ARMCM3_RESET_INITVAL 0x00000001 3453 #define PMUCCTL14_43012_DOT11MAC_CLKEN_INITVAL 0x00000020 3454 #define PMUCCTL14_43012_DOT11MAC_PHY_CLK_EN_INITVAL 0x00000080 3455 #define PMUCCTL14_43012_DOT11MAC_PHY_CNTL_EN_INITVAL 0x00000200 3456 #define PMUCCTL14_43012_SDIOD_RESET_INIVAL 0x00000400 3457 #define PMUCCTL14_43012_SDIO_CLK_DMN_RESET_INITVAL 0x00001000 3458 #define PMUCCTL14_43012_SOCRAM_CLKEN_INITVAL 0x00004000 3459 #define PMUCCTL14_43012_M2MDMA_RESET_INITVAL 0x00008000 3460 #define PMUCCTL14_43012_DISABLE_LQ_AVAIL 0x08000000 3461 3462 #define VREG6_43012_MEMLPLDO_ADJ_MASK 0x0000F000 3463 #define VREG6_43012_MEMLPLDO_ADJ_SHIFT 12 3464 3465 #define VREG6_43012_LPLDO_ADJ_MASK 0x000000F0 3466 #define VREG6_43012_LPLDO_ADJ_SHIFT 4 3467 3468 #define VREG7_43012_PWRSW_1P8_PU_MASK 0x00400000 3469 #define VREG7_43012_PWRSW_1P8_PU_SHIFT 22 3470 3471 /* 4347 PMU Chip Control Registers */ 3472 #define PMUCCTL03_4347_XTAL_CORESIZE_PMOS_NORMAL_MASK 0x001F8000 3473 #define PMUCCTL03_4347_XTAL_CORESIZE_PMOS_NORMAL_SHIFT 15 3474 #define PMUCCTL03_4347_XTAL_CORESIZE_PMOS_NORMAL_VAL 0x3F 3475 3476 #define PMUCCTL03_4347_XTAL_CORESIZE_NMOS_NORMAL_MASK 0x07E00000 3477 #define PMUCCTL03_4347_XTAL_CORESIZE_NMOS_NORMAL_SHIFT 21 3478 #define PMUCCTL03_4347_XTAL_CORESIZE_NMOS_NORMAL_VAL 0x3F 3479 3480 #define PMUCCTL03_4347_XTAL_SEL_BIAS_RES_NORMAL_MASK 0x38000000 3481 #define PMUCCTL03_4347_XTAL_SEL_BIAS_RES_NORMAL_SHIFT 27 3482 #define PMUCCTL03_4347_XTAL_SEL_BIAS_RES_NORMAL_VAL 0x0 3483 3484 #define PMUCCTL00_4347_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK 0x00000FC0 3485 #define PMUCCTL00_4347_XTAL_CORESIZE_BIAS_ADJ_NORMAL_SHIFT 6 3486 #define PMUCCTL00_4347_XTAL_CORESIZE_BIAS_ADJ_NORMAL_VAL 0x5 3487 3488 #define PMUCCTL00_4347_XTAL_RES_BYPASS_NORMAL_MASK 0x00038000 3489 #define PMUCCTL00_4347_XTAL_RES_BYPASS_NORMAL_SHIFT 15 3490 #define PMUCCTL00_4347_XTAL_RES_BYPASS_NORMAL_VAL 0x7 3491 3492 /* 4345 Chip specific ChipStatus register bits */ 3493 #define CST4345_SPROM_MASK 0x00000020 3494 #define CST4345_SFLASH_MASK 0x00000040 3495 #define CST4345_RES_INIT_MODE_SHIFT 7 3496 #define CST4345_RES_INIT_MODE_MASK 0x00000180 3497 #define CST4345_CHIPMODE_MASK 0x4000F 3498 #define CST4345_CHIPMODE_SDIOD(cs) (((cs) & (1 << 0)) != 0) /* SDIO */ 3499 #define CST4345_CHIPMODE_GSPI(cs) (((cs) & (1 << 1)) != 0) /* gSPI */ 3500 #define CST4345_CHIPMODE_HSIC(cs) (((cs) & (1 << 2)) != 0) /* HSIC */ 3501 #define CST4345_CHIPMODE_PCIE(cs) (((cs) & (1 << 3)) != 0) /* PCIE */ 3502 #define CST4345_CHIPMODE_USB20D(cs) (((cs) & (1 << 18)) != 0) /* USBDA */ 3503 3504 /* 4350 Chipcommon ChipStatus bits */ 3505 #define CST4350_SDIO_MODE 0x00000001 3506 #define CST4350_HSIC20D_MODE 0x00000002 3507 #define CST4350_BP_ON_HSIC_CLK 0x00000004 3508 #define CST4350_PCIE_MODE 0x00000008 3509 #define CST4350_USB20D_MODE 0x00000010 3510 #define CST4350_USB30D_MODE 0x00000020 3511 #define CST4350_SPROM_PRESENT 0x00000040 3512 #define CST4350_RSRC_INIT_MODE_0 0x00000080 3513 #define CST4350_RSRC_INIT_MODE_1 0x00000100 3514 #define CST4350_SEL0_SDIO 0x00000200 3515 #define CST4350_SEL1_SDIO 0x00000400 3516 #define CST4350_SDIO_PAD_MODE 0x00000800 3517 #define CST4350_BBPLL_LOCKED 0x00001000 3518 #define CST4350_USBPLL_LOCKED 0x00002000 3519 #define CST4350_LINE_STATE 0x0000C000 3520 #define CST4350_SERDES_PIPE_PLLLOCK 0x00010000 3521 #define CST4350_BT_READY 0x00020000 3522 #define CST4350_SFLASH_PRESENT 0x00040000 3523 #define CST4350_CPULESS_ENABLE 0x00080000 3524 #define CST4350_STRAP_HOST_IFC_1 0x00100000 3525 #define CST4350_STRAP_HOST_IFC_2 0x00200000 3526 #define CST4350_STRAP_HOST_IFC_3 0x00400000 3527 #define CST4350_RAW_SPROM_PRESENT 0x00800000 3528 #define CST4350_APP_CLK_SWITCH_SEL_RDBACK 0x01000000 3529 #define CST4350_RAW_RSRC_INIT_MODE_0 0x02000000 3530 #define CST4350_SDIO_PAD_VDDIO 0x04000000 3531 #define CST4350_GSPI_MODE 0x08000000 3532 #define CST4350_PACKAGE_OPTION 0xF0000000 3533 #define CST4350_PACKAGE_SHIFT 28 3534 3535 /* package option for 4350 */ 3536 #define CST4350_PACKAGE_WLCSP 0x0 3537 #define CST4350_PACKAGE_PCIE 0x1 3538 #define CST4350_PACKAGE_WLBGA 0x2 3539 #define CST4350_PACKAGE_DBG 0x3 3540 #define CST4350_PACKAGE_USB 0x4 3541 #define CST4350_PACKAGE_USB_HSIC 0x4 3542 3543 #define CST4350_PKG_MODE(cs) ((cs & CST4350_PACKAGE_OPTION) >> CST4350_PACKAGE_SHIFT) 3544 3545 #define CST4350_PKG_WLCSP(cs) (CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_WLCSP)) 3546 #define CST4350_PKG_PCIE(cs) (CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_PCIE)) 3547 #define CST4350_PKG_WLBGA(cs) (CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_WLBGA)) 3548 #define CST4350_PKG_USB(cs) (CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_USB)) 3549 #define CST4350_PKG_USB_HSIC(cs) (CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_USB_HSIC)) 3550 3551 /* 4350C0 USB PACKAGE using raw_sprom_present to indicate 40mHz xtal */ 3552 #define CST4350_PKG_USB_40M(cs) (cs & CST4350_RAW_SPROM_PRESENT) 3553 3554 #define CST4350_CHIPMODE_SDIOD(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_SDIOD)) 3555 #define CST4350_CHIPMODE_USB20D(cs) ((CST4350_IFC_MODE(cs)) == (CST4350_IFC_MODE_USB20D)) 3556 #define CST4350_CHIPMODE_HSIC20D(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_HSIC20D)) 3557 #define CST4350_CHIPMODE_HSIC30D(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_HSIC30D)) 3558 #define CST4350_CHIPMODE_USB30D(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_USB30D)) 3559 #define CST4350_CHIPMODE_USB30D_WL(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_USB30D_WL)) 3560 #define CST4350_CHIPMODE_PCIE(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_PCIE)) 3561 3562 /* strap_host_ifc strap value */ 3563 #define CST4350_HOST_IFC_MASK 0x00700000 3564 #define CST4350_HOST_IFC_SHIFT 20 3565 3566 /* host_ifc raw mode */ 3567 #define CST4350_IFC_MODE_SDIOD 0x0 3568 #define CST4350_IFC_MODE_HSIC20D 0x1 3569 #define CST4350_IFC_MODE_HSIC30D 0x2 3570 #define CST4350_IFC_MODE_PCIE 0x3 3571 #define CST4350_IFC_MODE_USB20D 0x4 3572 #define CST4350_IFC_MODE_USB30D 0x5 3573 #define CST4350_IFC_MODE_USB30D_WL 0x6 3574 #define CST4350_IFC_MODE_USB30D_BT 0x7 3575 3576 #define CST4350_IFC_MODE(cs) ((cs & CST4350_HOST_IFC_MASK) >> CST4350_HOST_IFC_SHIFT) 3577 3578 /* 4350 PMU resources */ 3579 #define RES4350_LPLDO_PU 0 3580 #define RES4350_PMU_BG_PU 1 3581 #define RES4350_PMU_SLEEP 2 3582 #define RES4350_RSVD_3 3 3583 #define RES4350_CBUCK_LPOM_PU 4 3584 #define RES4350_CBUCK_PFM_PU 5 3585 #define RES4350_COLD_START_WAIT 6 3586 #define RES4350_RSVD_7 7 3587 #define RES4350_LNLDO_PU 8 3588 #define RES4350_XTALLDO_PU 9 3589 #define RES4350_LDO3P3_PU 10 3590 #define RES4350_OTP_PU 11 3591 #define RES4350_XTAL_PU 12 3592 #define RES4350_SR_CLK_START 13 3593 #define RES4350_LQ_AVAIL 14 3594 #define RES4350_LQ_START 15 3595 #define RES4350_PERST_OVR 16 3596 #define RES4350_WL_CORE_RDY 17 3597 #define RES4350_ILP_REQ 18 3598 #define RES4350_ALP_AVAIL 19 3599 #define RES4350_MINI_PMU 20 3600 #define RES4350_RADIO_PU 21 3601 #define RES4350_SR_CLK_STABLE 22 3602 #define RES4350_SR_SAVE_RESTORE 23 3603 #define RES4350_SR_PHY_PWRSW 24 3604 #define RES4350_SR_VDDM_PWRSW 25 3605 #define RES4350_SR_SUBCORE_PWRSW 26 3606 #define RES4350_SR_SLEEP 27 3607 #define RES4350_HT_START 28 3608 #define RES4350_HT_AVAIL 29 3609 #define RES4350_MACPHY_CLKAVAIL 30 3610 3611 #define MUXENAB4350_UART_MASK (0x0000000f) 3612 #define MUXENAB4350_UART_SHIFT 0 3613 #define MUXENAB4350_HOSTWAKE_MASK (0x000000f0) /**< configure GPIO for host_wake */ 3614 #define MUXENAB4350_HOSTWAKE_SHIFT 4 3615 #define MUXENAB4349_UART_MASK (0xf) 3616 3617 #define CC4350_GPIO_COUNT 16 3618 3619 /* 4350 GCI function sel values */ 3620 #define CC4350_FNSEL_HWDEF (0) 3621 #define CC4350_FNSEL_SAMEASPIN (1) 3622 #define CC4350_FNSEL_UART (2) 3623 #define CC4350_FNSEL_SFLASH (3) 3624 #define CC4350_FNSEL_SPROM (4) 3625 #define CC4350_FNSEL_I2C (5) 3626 #define CC4350_FNSEL_MISC0 (6) 3627 #define CC4350_FNSEL_GCI (7) 3628 #define CC4350_FNSEL_MISC1 (8) 3629 #define CC4350_FNSEL_MISC2 (9) 3630 #define CC4350_FNSEL_PWDOG (10) 3631 #define CC4350_FNSEL_IND (12) 3632 #define CC4350_FNSEL_PDN (13) 3633 #define CC4350_FNSEL_PUP (14) 3634 #define CC4350_FNSEL_TRISTATE (15) 3635 #define CC4350C_FNSEL_UART (3) 3636 3637 /* 4350 GPIO */ 3638 #define CC4350_PIN_GPIO_00 (0) 3639 #define CC4350_PIN_GPIO_01 (1) 3640 #define CC4350_PIN_GPIO_02 (2) 3641 #define CC4350_PIN_GPIO_03 (3) 3642 #define CC4350_PIN_GPIO_04 (4) 3643 #define CC4350_PIN_GPIO_05 (5) 3644 #define CC4350_PIN_GPIO_06 (6) 3645 #define CC4350_PIN_GPIO_07 (7) 3646 #define CC4350_PIN_GPIO_08 (8) 3647 #define CC4350_PIN_GPIO_09 (9) 3648 #define CC4350_PIN_GPIO_10 (10) 3649 #define CC4350_PIN_GPIO_11 (11) 3650 #define CC4350_PIN_GPIO_12 (12) 3651 #define CC4350_PIN_GPIO_13 (13) 3652 #define CC4350_PIN_GPIO_14 (14) 3653 #define CC4350_PIN_GPIO_15 (15) 3654 3655 #define CC4350_RSVD_16_SHIFT 16 3656 3657 #define CC2_4350_PHY_PWRSW_UPTIME_MASK (0xf << 0) 3658 #define CC2_4350_PHY_PWRSW_UPTIME_SHIFT (0) 3659 #define CC2_4350_VDDM_PWRSW_UPDELAY_MASK (0xf << 4) 3660 #define CC2_4350_VDDM_PWRSW_UPDELAY_SHIFT (4) 3661 #define CC2_4350_VDDM_PWRSW_UPTIME_MASK (0xf << 8) 3662 #define CC2_4350_VDDM_PWRSW_UPTIME_SHIFT (8) 3663 #define CC2_4350_SBC_PWRSW_DNDELAY_MASK (0x3 << 12) 3664 #define CC2_4350_SBC_PWRSW_DNDELAY_SHIFT (12) 3665 #define CC2_4350_PHY_PWRSW_DNDELAY_MASK (0x3 << 14) 3666 #define CC2_4350_PHY_PWRSW_DNDELAY_SHIFT (14) 3667 #define CC2_4350_VDDM_PWRSW_DNDELAY_MASK (0x3 << 16) 3668 #define CC2_4350_VDDM_PWRSW_DNDELAY_SHIFT (16) 3669 #define CC2_4350_VDDM_PWRSW_EN_MASK (1 << 20) 3670 #define CC2_4350_VDDM_PWRSW_EN_SHIFT (20) 3671 #define CC2_4350_MEMLPLDO_PWRSW_EN_MASK (1 << 21) 3672 #define CC2_4350_MEMLPLDO_PWRSW_EN_SHIFT (21) 3673 #define CC2_4350_SDIO_AOS_WAKEUP_MASK (1 << 24) 3674 #define CC2_4350_SDIO_AOS_WAKEUP_SHIFT (24) 3675 3676 /* Applies to 4335/4350/4345 */ 3677 #define CC3_SR_CLK_SR_MEM_MASK (1 << 0) 3678 #define CC3_SR_CLK_SR_MEM_SHIFT (0) 3679 #define CC3_SR_BIT1_TBD_MASK (1 << 1) 3680 #define CC3_SR_BIT1_TBD_SHIFT (1) 3681 #define CC3_SR_ENGINE_ENABLE_MASK (1 << 2) 3682 #define CC3_SR_ENGINE_ENABLE_SHIFT (2) 3683 #define CC3_SR_BIT3_TBD_MASK (1 << 3) 3684 #define CC3_SR_BIT3_TBD_SHIFT (3) 3685 #define CC3_SR_MINDIV_FAST_CLK_MASK (0xF << 4) 3686 #define CC3_SR_MINDIV_FAST_CLK_SHIFT (4) 3687 #define CC3_SR_R23_SR2_RISE_EDGE_TRIG_MASK (1 << 8) 3688 #define CC3_SR_R23_SR2_RISE_EDGE_TRIG_SHIFT (8) 3689 #define CC3_SR_R23_SR2_FALL_EDGE_TRIG_MASK (1 << 9) 3690 #define CC3_SR_R23_SR2_FALL_EDGE_TRIG_SHIFT (9) 3691 #define CC3_SR_R23_SR_RISE_EDGE_TRIG_MASK (1 << 10) 3692 #define CC3_SR_R23_SR_RISE_EDGE_TRIG_SHIFT (10) 3693 #define CC3_SR_R23_SR_FALL_EDGE_TRIG_MASK (1 << 11) 3694 #define CC3_SR_R23_SR_FALL_EDGE_TRIG_SHIFT (11) 3695 #define CC3_SR_NUM_CLK_HIGH_MASK (0x7 << 12) 3696 #define CC3_SR_NUM_CLK_HIGH_SHIFT (12) 3697 #define CC3_SR_BIT15_TBD_MASK (1 << 15) 3698 #define CC3_SR_BIT15_TBD_SHIFT (15) 3699 #define CC3_SR_PHY_FUNC_PIC_MASK (1 << 16) 3700 #define CC3_SR_PHY_FUNC_PIC_SHIFT (16) 3701 #define CC3_SR_BIT17_19_TBD_MASK (0x7 << 17) 3702 #define CC3_SR_BIT17_19_TBD_SHIFT (17) 3703 #define CC3_SR_CHIP_TRIGGER_1_MASK (1 << 20) 3704 #define CC3_SR_CHIP_TRIGGER_1_SHIFT (20) 3705 #define CC3_SR_CHIP_TRIGGER_2_MASK (1 << 21) 3706 #define CC3_SR_CHIP_TRIGGER_2_SHIFT (21) 3707 #define CC3_SR_CHIP_TRIGGER_3_MASK (1 << 22) 3708 #define CC3_SR_CHIP_TRIGGER_3_SHIFT (22) 3709 #define CC3_SR_CHIP_TRIGGER_4_MASK (1 << 23) 3710 #define CC3_SR_CHIP_TRIGGER_4_SHIFT (23) 3711 #define CC3_SR_ALLOW_SBC_FUNC_PIC_MASK (1 << 24) 3712 #define CC3_SR_ALLOW_SBC_FUNC_PIC_SHIFT (24) 3713 #define CC3_SR_BIT25_26_TBD_MASK (0x3 << 25) 3714 #define CC3_SR_BIT25_26_TBD_SHIFT (25) 3715 #define CC3_SR_ALLOW_SBC_STBY_MASK (1 << 27) 3716 #define CC3_SR_ALLOW_SBC_STBY_SHIFT (27) 3717 #define CC3_SR_GPIO_MUX_MASK (0xF << 28) 3718 #define CC3_SR_GPIO_MUX_SHIFT (28) 3719 3720 /* Applies to 4335/4350/4345 */ 3721 #define CC4_SR_INIT_ADDR_MASK (0x3FF0000) 3722 #define CC4_4350_SR_ASM_ADDR (0x30) 3723 #define CC4_4350_C0_SR_ASM_ADDR (0x0) 3724 #define CC4_4335_SR_ASM_ADDR (0x48) 3725 #define CC4_4345_SR_ASM_ADDR (0x48) 3726 #define CC4_SR_INIT_ADDR_SHIFT (16) 3727 3728 #define CC4_4350_EN_SR_CLK_ALP_MASK (1 << 30) 3729 #define CC4_4350_EN_SR_CLK_ALP_SHIFT (30) 3730 #define CC4_4350_EN_SR_CLK_HT_MASK (1 << 31) 3731 #define CC4_4350_EN_SR_CLK_HT_SHIFT (31) 3732 3733 #define VREG4_4350_MEMLPDO_PU_MASK (1 << 31) 3734 #define VREG4_4350_MEMLPDO_PU_SHIFT 31 3735 3736 #define VREG6_4350_SR_EXT_CLKDIR_MASK (1 << 20) 3737 #define VREG6_4350_SR_EXT_CLKDIR_SHIFT 20 3738 #define VREG6_4350_SR_EXT_CLKDIV_MASK (0x3 << 21) 3739 #define VREG6_4350_SR_EXT_CLKDIV_SHIFT 21 3740 #define VREG6_4350_SR_EXT_CLKEN_MASK (1 << 23) 3741 #define VREG6_4350_SR_EXT_CLKEN_SHIFT 23 3742 3743 #define CC5_4350_PMU_EN_ASSERT_MASK (1 << 13) 3744 #define CC5_4350_PMU_EN_ASSERT_SHIFT (13) 3745 3746 #define CC6_4350_PCIE_CLKREQ_WAKEUP_MASK (1 << 4) 3747 #define CC6_4350_PCIE_CLKREQ_WAKEUP_SHIFT (4) 3748 #define CC6_4350_PMU_WAKEUP_ALPAVAIL_MASK (1 << 6) 3749 #define CC6_4350_PMU_WAKEUP_ALPAVAIL_SHIFT (6) 3750 #define CC6_4350_PMU_EN_EXT_PERST_MASK (1 << 17) 3751 #define CC6_4350_PMU_EN_EXT_PERST_SHIFT (17) 3752 #define CC6_4350_PMU_EN_WAKEUP_MASK (1 << 18) 3753 #define CC6_4350_PMU_EN_WAKEUP_SHIFT (18) 3754 3755 #define CC7_4350_PMU_EN_ASSERT_L2_MASK (1 << 26) 3756 #define CC7_4350_PMU_EN_ASSERT_L2_SHIFT (26) 3757 #define CC7_4350_PMU_EN_MDIO_MASK (1 << 27) 3758 #define CC7_4350_PMU_EN_MDIO_SHIFT (27) 3759 3760 #define CC6_4345_PMU_EN_PERST_DEASSERT_MASK (1 << 13) 3761 #define CC6_4345_PMU_EN_PERST_DEASSERT_SHIF (13) 3762 #define CC6_4345_PMU_EN_L2_DEASSERT_MASK (1 << 14) 3763 #define CC6_4345_PMU_EN_L2_DEASSERT_SHIF (14) 3764 #define CC6_4345_PMU_EN_ASSERT_L2_MASK (1 << 15) 3765 #define CC6_4345_PMU_EN_ASSERT_L2_SHIFT (15) 3766 #define CC6_4345_PMU_EN_MDIO_MASK (1 << 24) 3767 #define CC6_4345_PMU_EN_MDIO_SHIFT (24) 3768 3769 /* 4347 GCI function sel values */ 3770 #define CC4347_FNSEL_HWDEF (0) 3771 #define CC4347_FNSEL_SAMEASPIN (1) 3772 #define CC4347_FNSEL_GPIO0 (2) 3773 #define CC4347_FNSEL_FUART (3) 3774 #define CC4347_FNSEL_GCI0 (4) 3775 #define CC4347_FNSEL_GCI1 (5) 3776 #define CC4347_FNSEL_DBG_UART (6) 3777 #define CC4347_FNSEL_SPI (7) 3778 #define CC4347_FNSEL_SPROM (8) 3779 #define CC4347_FNSEL_MISC0 (9) 3780 #define CC4347_FNSEL_MISC1 (10) 3781 #define CC4347_FNSEL_MISC2 (11) 3782 #define CC4347_FNSEL_IND (12) 3783 #define CC4347_FNSEL_PDN (13) 3784 #define CC4347_FNSEL_PUP (14) 3785 #define CC4347_FNSEL_TRISTATE (15) 3786 3787 /* 4347 GPIO */ 3788 #define CC4347_PIN_GPIO_02 (2) 3789 #define CC4347_PIN_GPIO_03 (3) 3790 #define CC4347_PIN_GPIO_04 (4) 3791 #define CC4347_PIN_GPIO_05 (5) 3792 #define CC4347_PIN_GPIO_06 (6) 3793 #define CC4347_PIN_GPIO_07 (7) 3794 #define CC4347_PIN_GPIO_08 (8) 3795 #define CC4347_PIN_GPIO_09 (9) 3796 #define CC4347_PIN_GPIO_10 (10) 3797 #define CC4347_PIN_GPIO_11 (11) 3798 #define CC4347_PIN_GPIO_12 (12) 3799 #define CC4347_PIN_GPIO_13 (13) 3800 /* GCI chipcontrol register indices */ 3801 #define CC_GCI_CHIPCTRL_00 (0) 3802 #define CC_GCI_CHIPCTRL_01 (1) 3803 #define CC_GCI_CHIPCTRL_02 (2) 3804 #define CC_GCI_CHIPCTRL_03 (3) 3805 #define CC_GCI_CHIPCTRL_04 (4) 3806 #define CC_GCI_CHIPCTRL_05 (5) 3807 #define CC_GCI_CHIPCTRL_06 (6) 3808 #define CC_GCI_CHIPCTRL_07 (7) 3809 #define CC_GCI_CHIPCTRL_08 (8) 3810 #define CC_GCI_CHIPCTRL_09 (9) 3811 #define CC_GCI_CHIPCTRL_10 (10) 3812 #define CC_GCI_CHIPCTRL_10 (10) 3813 #define CC_GCI_CHIPCTRL_11 (11) 3814 #define CC_GCI_XTAL_BUFSTRG_NFC (0xff << 12) 3815 3816 #define CC_GCI_04_SDIO_DRVSTR_SHIFT 15 3817 #define CC_GCI_04_SDIO_DRVSTR_MASK (0x0f << CC_GCI_04_SDIO_DRVSTR_SHIFT) /* 0x00078000 */ 3818 #define CC_GCI_04_SDIO_DRVSTR_OVERRIDE_BIT (1 << 18) 3819 #define CC_GCI_04_SDIO_DRVSTR_DEFAULT_MA 14 3820 #define CC_GCI_04_SDIO_DRVSTR_MIN_MA 2 3821 #define CC_GCI_04_SDIO_DRVSTR_MAX_MA 16 3822 3823 #define CC_GCI_06_JTAG_SEL_SHIFT 4 3824 #define CC_GCI_06_JTAG_SEL_MASK (1 << 4) 3825 3826 #define CC_GCI_NUMCHIPCTRLREGS(cap1) ((cap1 & 0xF00) >> 8) 3827 3828 #define CC_GCI_03_LPFLAGS_SFLASH_MASK (0xFFFFFF << 8) 3829 #define CC_GCI_03_LPFLAGS_SFLASH_VAL (0xCCCCCC << 8) 3830 #define GPIO_CTRL_REG_DISABLE_INTERRUPT (3 << 9) 3831 #define GPIO_CTRL_REG_COUNT 40 3832 3833 /* GCI chipstatus register indices */ 3834 #define GCI_CHIPSTATUS_00 (0) 3835 #define GCI_CHIPSTATUS_01 (1) 3836 #define GCI_CHIPSTATUS_02 (2) 3837 #define GCI_CHIPSTATUS_03 (3) 3838 #define GCI_CHIPSTATUS_04 (4) 3839 #define GCI_CHIPSTATUS_05 (5) 3840 #define GCI_CHIPSTATUS_06 (6) 3841 #define GCI_CHIPSTATUS_07 (7) 3842 #define GCI_CHIPSTATUS_08 (8) 3843 #define GCI_CHIPSTATUS_09 (9) 3844 #define GCI_CHIPSTATUS_10 (10) 3845 #define GCI_CHIPSTATUS_11 (11) 3846 #define GCI_CHIPSTATUS_12 (12) 3847 #define GCI_CHIPSTATUS_13 (13) 3848 3849 /* 43021 GCI chipstatus registers */ 3850 #define GCI43012_CHIPSTATUS_07_BBPLL_LOCK_MASK (1 << 3) 3851 3852 /* 4345 PMU resources */ 3853 #define RES4345_LPLDO_PU 0 3854 #define RES4345_PMU_BG_PU 1 3855 #define RES4345_PMU_SLEEP 2 3856 #define RES4345_HSICLDO_PU 3 3857 #define RES4345_CBUCK_LPOM_PU 4 3858 #define RES4345_CBUCK_PFM_PU 5 3859 #define RES4345_COLD_START_WAIT 6 3860 #define RES4345_RSVD_7 7 3861 #define RES4345_LNLDO_PU 8 3862 #define RES4345_XTALLDO_PU 9 3863 #define RES4345_LDO3P3_PU 10 3864 #define RES4345_OTP_PU 11 3865 #define RES4345_XTAL_PU 12 3866 #define RES4345_SR_CLK_START 13 3867 #define RES4345_LQ_AVAIL 14 3868 #define RES4345_LQ_START 15 3869 #define RES4345_PERST_OVR 16 3870 #define RES4345_WL_CORE_RDY 17 3871 #define RES4345_ILP_REQ 18 3872 #define RES4345_ALP_AVAIL 19 3873 #define RES4345_MINI_PMU 20 3874 #define RES4345_RADIO_PU 21 3875 #define RES4345_SR_CLK_STABLE 22 3876 #define RES4345_SR_SAVE_RESTORE 23 3877 #define RES4345_SR_PHY_PWRSW 24 3878 #define RES4345_SR_VDDM_PWRSW 25 3879 #define RES4345_SR_SUBCORE_PWRSW 26 3880 #define RES4345_SR_SLEEP 27 3881 #define RES4345_HT_START 28 3882 #define RES4345_HT_AVAIL 29 3883 #define RES4345_MACPHY_CLK_AVAIL 30 3884 3885 /* 43012 pins 3886 * note: only the values set as default/used are added here. 3887 */ 3888 #define CC43012_PIN_GPIO_00 (0) 3889 #define CC43012_PIN_GPIO_01 (1) 3890 #define CC43012_PIN_GPIO_02 (2) 3891 #define CC43012_PIN_GPIO_03 (3) 3892 #define CC43012_PIN_GPIO_04 (4) 3893 #define CC43012_PIN_GPIO_05 (5) 3894 #define CC43012_PIN_GPIO_06 (6) 3895 #define CC43012_PIN_GPIO_07 (7) 3896 #define CC43012_PIN_GPIO_08 (8) 3897 #define CC43012_PIN_GPIO_09 (9) 3898 #define CC43012_PIN_GPIO_10 (10) 3899 #define CC43012_PIN_GPIO_11 (11) 3900 #define CC43012_PIN_GPIO_12 (12) 3901 #define CC43012_PIN_GPIO_13 (13) 3902 #define CC43012_PIN_GPIO_14 (14) 3903 #define CC43012_PIN_GPIO_15 (15) 3904 3905 /* 43012 GCI function sel values */ 3906 #define CC43012_FNSEL_HWDEF (0) 3907 #define CC43012_FNSEL_SAMEASPIN (1) 3908 #define CC43012_FNSEL_GPIO0 (2) 3909 #define CC43012_FNSEL_GPIO1 (3) 3910 #define CC43012_FNSEL_GCI0 (4) 3911 #define CC43012_FNSEL_GCI1 (5) 3912 #define CC43012_FNSEL_DBG_UART (6) 3913 #define CC43012_FNSEL_I2C (7) 3914 #define CC43012_FNSEL_BT_SFLASH (8) 3915 #define CC43012_FNSEL_MISC0 (9) 3916 #define CC43012_FNSEL_MISC1 (10) 3917 #define CC43012_FNSEL_MISC2 (11) 3918 #define CC43012_FNSEL_IND (12) 3919 #define CC43012_FNSEL_PDN (13) 3920 #define CC43012_FNSEL_PUP (14) 3921 #define CC43012_FNSEL_TRI (15) 3922 3923 /* 4335 pins 3924 * note: only the values set as default/used are added here. 3925 */ 3926 #define CC4335_PIN_GPIO_00 (0) 3927 #define CC4335_PIN_GPIO_01 (1) 3928 #define CC4335_PIN_GPIO_02 (2) 3929 #define CC4335_PIN_GPIO_03 (3) 3930 #define CC4335_PIN_GPIO_04 (4) 3931 #define CC4335_PIN_GPIO_05 (5) 3932 #define CC4335_PIN_GPIO_06 (6) 3933 #define CC4335_PIN_GPIO_07 (7) 3934 #define CC4335_PIN_GPIO_08 (8) 3935 #define CC4335_PIN_GPIO_09 (9) 3936 #define CC4335_PIN_GPIO_10 (10) 3937 #define CC4335_PIN_GPIO_11 (11) 3938 #define CC4335_PIN_GPIO_12 (12) 3939 #define CC4335_PIN_GPIO_13 (13) 3940 #define CC4335_PIN_GPIO_14 (14) 3941 #define CC4335_PIN_GPIO_15 (15) 3942 #define CC4335_PIN_SDIO_CLK (16) 3943 #define CC4335_PIN_SDIO_CMD (17) 3944 #define CC4335_PIN_SDIO_DATA0 (18) 3945 #define CC4335_PIN_SDIO_DATA1 (19) 3946 #define CC4335_PIN_SDIO_DATA2 (20) 3947 #define CC4335_PIN_SDIO_DATA3 (21) 3948 #define CC4335_PIN_RF_SW_CTRL_6 (22) 3949 #define CC4335_PIN_RF_SW_CTRL_7 (23) 3950 #define CC4335_PIN_RF_SW_CTRL_8 (24) 3951 #define CC4335_PIN_RF_SW_CTRL_9 (25) 3952 /* Last GPIO Pad */ 3953 #define CC4335_PIN_GPIO_LAST (31) 3954 3955 /* 4335 GCI function sel values 3956 */ 3957 #define CC4335_FNSEL_HWDEF (0) 3958 #define CC4335_FNSEL_SAMEASPIN (1) 3959 #define CC4335_FNSEL_GPIO0 (2) 3960 #define CC4335_FNSEL_GPIO1 (3) 3961 #define CC4335_FNSEL_GCI0 (4) 3962 #define CC4335_FNSEL_GCI1 (5) 3963 #define CC4335_FNSEL_UART (6) 3964 #define CC4335_FNSEL_SFLASH (7) 3965 #define CC4335_FNSEL_SPROM (8) 3966 #define CC4335_FNSEL_MISC0 (9) 3967 #define CC4335_FNSEL_MISC1 (10) 3968 #define CC4335_FNSEL_MISC2 (11) 3969 #define CC4335_FNSEL_IND (12) 3970 #define CC4335_FNSEL_PDN (13) 3971 #define CC4335_FNSEL_PUP (14) 3972 #define CC4335_FNSEL_TRI (15) 3973 3974 /* GCI Core Control Reg */ 3975 #define GCI_CORECTRL_SR_MASK (1 << 0) /**< SECI block Reset */ 3976 #define GCI_CORECTRL_RSL_MASK (1 << 1) /**< ResetSECILogic */ 3977 #define GCI_CORECTRL_ES_MASK (1 << 2) /**< EnableSECI */ 3978 #define GCI_CORECTRL_FSL_MASK (1 << 3) /**< Force SECI Out Low */ 3979 #define GCI_CORECTRL_SOM_MASK (7 << 4) /**< SECI Op Mode */ 3980 #define GCI_CORECTRL_US_MASK (1 << 7) /**< Update SECI */ 3981 #define GCI_CORECTRL_BOS_MASK (1 << 8) /**< Break On Sleep */ 3982 #define GCI_CORECTRL_FORCEREGCLK_MASK (1 << 18) /* ForceRegClk */ 3983 3984 /* 4345 pins 3985 * note: only the values set as default/used are added here. 3986 */ 3987 #define CC4345_PIN_GPIO_00 (0) 3988 #define CC4345_PIN_GPIO_01 (1) 3989 #define CC4345_PIN_GPIO_02 (2) 3990 #define CC4345_PIN_GPIO_03 (3) 3991 #define CC4345_PIN_GPIO_04 (4) 3992 #define CC4345_PIN_GPIO_05 (5) 3993 #define CC4345_PIN_GPIO_06 (6) 3994 #define CC4345_PIN_GPIO_07 (7) 3995 #define CC4345_PIN_GPIO_08 (8) 3996 #define CC4345_PIN_GPIO_09 (9) 3997 #define CC4345_PIN_GPIO_10 (10) 3998 #define CC4345_PIN_GPIO_11 (11) 3999 #define CC4345_PIN_GPIO_12 (12) 4000 #define CC4345_PIN_GPIO_13 (13) 4001 #define CC4345_PIN_GPIO_14 (14) 4002 #define CC4345_PIN_GPIO_15 (15) 4003 #define CC4345_PIN_GPIO_16 (16) 4004 #define CC4345_PIN_SDIO_CLK (17) 4005 #define CC4345_PIN_SDIO_CMD (18) 4006 #define CC4345_PIN_SDIO_DATA0 (19) 4007 #define CC4345_PIN_SDIO_DATA1 (20) 4008 #define CC4345_PIN_SDIO_DATA2 (21) 4009 #define CC4345_PIN_SDIO_DATA3 (22) 4010 #define CC4345_PIN_RF_SW_CTRL_0 (23) 4011 #define CC4345_PIN_RF_SW_CTRL_1 (24) 4012 #define CC4345_PIN_RF_SW_CTRL_2 (25) 4013 #define CC4345_PIN_RF_SW_CTRL_3 (26) 4014 #define CC4345_PIN_RF_SW_CTRL_4 (27) 4015 #define CC4345_PIN_RF_SW_CTRL_5 (28) 4016 #define CC4345_PIN_RF_SW_CTRL_6 (29) 4017 #define CC4345_PIN_RF_SW_CTRL_7 (30) 4018 #define CC4345_PIN_RF_SW_CTRL_8 (31) 4019 #define CC4345_PIN_RF_SW_CTRL_9 (32) 4020 4021 /* 4345 GCI function sel values 4022 */ 4023 #define CC4345_FNSEL_HWDEF (0) 4024 #define CC4345_FNSEL_SAMEASPIN (1) 4025 #define CC4345_FNSEL_GPIO0 (2) 4026 #define CC4345_FNSEL_GPIO1 (3) 4027 #define CC4345_FNSEL_GCI0 (4) 4028 #define CC4345_FNSEL_GCI1 (5) 4029 #define CC4345_FNSEL_UART (6) 4030 #define CC4345_FNSEL_SFLASH (7) 4031 #define CC4345_FNSEL_SPROM (8) 4032 #define CC4345_FNSEL_MISC0 (9) 4033 #define CC4345_FNSEL_MISC1 (10) 4034 #define CC4345_FNSEL_MISC2 (11) 4035 #define CC4345_FNSEL_IND (12) 4036 #define CC4345_FNSEL_PDN (13) 4037 #define CC4345_FNSEL_PUP (14) 4038 #define CC4345_FNSEL_TRI (15) 4039 4040 #define MUXENAB4345_UART_MASK (0x0000000f) 4041 #define MUXENAB4345_UART_SHIFT 0 4042 #define MUXENAB4345_HOSTWAKE_MASK (0x000000f0) 4043 #define MUXENAB4345_HOSTWAKE_SHIFT 4 4044 4045 /* 4349 Group (4349, 4355, 4359) GCI AVS function sel values */ 4046 #define CC4349_GRP_GCI_AVS_CTRL_MASK (0xffe00000) 4047 #define CC4349_GRP_GCI_AVS_CTRL_SHIFT (21) 4048 #define CC4349_GRP_GCI_AVS_CTRL_ENAB (1 << 5) 4049 4050 /* 4345 GCI AVS function sel values */ 4051 #define CC4345_GCI_AVS_CTRL_MASK (0xfc) 4052 #define CC4345_GCI_AVS_CTRL_SHIFT (2) 4053 #define CC4345_GCI_AVS_CTRL_ENAB (1 << 5) 4054 4055 /* 43430 Pin */ 4056 #define CC43430_PIN_GPIO_00 (0) 4057 #define CC43430_PIN_GPIO_01 (1) 4058 #define CC43430_PIN_GPIO_02 (2) 4059 #define CC43430_PIN_GPIO_07 (7) 4060 #define CC43430_PIN_GPIO_08 (8) 4061 #define CC43430_PIN_GPIO_09 (9) 4062 #define CC43430_PIN_GPIO_10 (10) 4063 4064 #define CC43430_FNSEL_SDIO_INT (2) 4065 #define CC43430_FNSEL_6_FAST_UART (6) 4066 #define CC43430_FNSEL_10_FAST_UART (10) 4067 4068 #define MUXENAB43430_UART_MASK (0x0000000f) 4069 #define MUXENAB43430_UART_SHIFT 0 4070 #define MUXENAB43430_HOSTWAKE_MASK (0x000000f0) /* configure GPIO for SDIO host_wake */ 4071 #define MUXENAB43430_HOSTWAKE_SHIFT 4 4072 4073 #define CC43430_FNSEL_SAMEASPIN (1) 4074 #define CC43430_RFSWCTRL_EN_MASK (0x7f8) 4075 #define CC43430_RFSWCTRL_EN_SHIFT (3) 4076 4077 /* GCI GPIO for function sel GCI-0/GCI-1 */ 4078 #define CC_GCI_GPIO_0 (0) 4079 #define CC_GCI_GPIO_1 (1) 4080 #define CC_GCI_GPIO_2 (2) 4081 #define CC_GCI_GPIO_3 (3) 4082 #define CC_GCI_GPIO_4 (4) 4083 #define CC_GCI_GPIO_5 (5) 4084 #define CC_GCI_GPIO_6 (6) 4085 #define CC_GCI_GPIO_7 (7) 4086 #define CC_GCI_GPIO_8 (8) 4087 #define CC_GCI_GPIO_9 (9) 4088 #define CC_GCI_GPIO_10 (10) 4089 #define CC_GCI_GPIO_11 (11) 4090 #define CC_GCI_GPIO_12 (12) 4091 #define CC_GCI_GPIO_13 (13) 4092 #define CC_GCI_GPIO_14 (14) 4093 #define CC_GCI_GPIO_15 (15) 4094 4095 /* indicates Invalid GPIO, e.g. when PAD GPIO doesn't map to GCI GPIO */ 4096 #define CC_GCI_GPIO_INVALID 0xFF 4097 4098 /* find the 4 bit mask given the bit position */ 4099 #define GCIMASK(pos) (((uint32)0xF) << pos) 4100 /* get the value which can be used to directly OR with chipcontrol reg */ 4101 #define GCIPOSVAL(val, pos) ((((uint32)val) << pos) & GCIMASK(pos)) 4102 /* Extract nibble from a given position */ 4103 #define GCIGETNBL(val, pos) ((val >> pos) & 0xF) 4104 4105 /* find the 8 bit mask given the bit position */ 4106 #define GCIMASK_8B(pos) (((uint32)0xFF) << pos) 4107 /* get the value which can be used to directly OR with chipcontrol reg */ 4108 #define GCIPOSVAL_8B(val, pos) ((((uint32)val) << pos) & GCIMASK_8B(pos)) 4109 /* Extract nibble from a given position */ 4110 #define GCIGETNBL_8B(val, pos) ((val >> pos) & 0xFF) 4111 4112 /* find the 4 bit mask given the bit position */ 4113 #define GCIMASK_4B(pos) (((uint32)0xF) << pos) 4114 /* get the value which can be used to directly OR with chipcontrol reg */ 4115 #define GCIPOSVAL_4B(val, pos) ((((uint32)val) << pos) & GCIMASK_4B(pos)) 4116 /* Extract nibble from a given position */ 4117 #define GCIGETNBL_4B(val, pos) ((val >> pos) & 0xF) 4118 4119 /* 4335 GCI Intstatus(Mask)/WakeMask Register bits. */ 4120 #define GCI_INTSTATUS_RBI (1 << 0) /**< Rx Break Interrupt */ 4121 #define GCI_INTSTATUS_UB (1 << 1) /**< UART Break Interrupt */ 4122 #define GCI_INTSTATUS_SPE (1 << 2) /**< SECI Parity Error Interrupt */ 4123 #define GCI_INTSTATUS_SFE (1 << 3) /**< SECI Framing Error Interrupt */ 4124 #define GCI_INTSTATUS_SRITI (1 << 9) /**< SECI Rx Idle Timer Interrupt */ 4125 #define GCI_INTSTATUS_STFF (1 << 10) /**< SECI Tx FIFO Full Interrupt */ 4126 #define GCI_INTSTATUS_STFAE (1 << 11) /**< SECI Tx FIFO Almost Empty Intr */ 4127 #define GCI_INTSTATUS_SRFAF (1 << 12) /**< SECI Rx FIFO Almost Full */ 4128 #define GCI_INTSTATUS_SRFNE (1 << 14) /**< SECI Rx FIFO Not Empty */ 4129 #define GCI_INTSTATUS_SRFOF (1 << 15) /**< SECI Rx FIFO Not Empty Timeout */ 4130 #define GCI_INTSTATUS_EVENT (1 << 21) /* GCI Event Interrupt */ 4131 #define GCI_INTSTATUS_LEVELWAKE (1 << 22) /* GCI Wake Level Interrupt */ 4132 #define GCI_INTSTATUS_EVENTWAKE (1 << 23) /* GCI Wake Event Interrupt */ 4133 #define GCI_INTSTATUS_GPIOINT (1 << 25) /**< GCIGpioInt */ 4134 #define GCI_INTSTATUS_GPIOWAKE (1 << 26) /**< GCIGpioWake */ 4135 #define GCI_INTSTATUS_LHLWLWAKE (1 << 30) /* LHL WL wake */ 4136 4137 /* 4335 GCI IntMask Register bits. */ 4138 #define GCI_INTMASK_RBI (1 << 0) /**< Rx Break Interrupt */ 4139 #define GCI_INTMASK_UB (1 << 1) /**< UART Break Interrupt */ 4140 #define GCI_INTMASK_SPE (1 << 2) /**< SECI Parity Error Interrupt */ 4141 #define GCI_INTMASK_SFE (1 << 3) /**< SECI Framing Error Interrupt */ 4142 #define GCI_INTMASK_SRITI (1 << 9) /**< SECI Rx Idle Timer Interrupt */ 4143 #define GCI_INTMASK_STFF (1 << 10) /**< SECI Tx FIFO Full Interrupt */ 4144 #define GCI_INTMASK_STFAE (1 << 11) /**< SECI Tx FIFO Almost Empty Intr */ 4145 #define GCI_INTMASK_SRFAF (1 << 12) /**< SECI Rx FIFO Almost Full */ 4146 #define GCI_INTMASK_SRFNE (1 << 14) /**< SECI Rx FIFO Not Empty */ 4147 #define GCI_INTMASK_SRFOF (1 << 15) /**< SECI Rx FIFO Not Empty Timeout */ 4148 #define GCI_INTMASK_EVENT (1 << 21) /* GCI Event Interrupt */ 4149 #define GCI_INTMASK_LEVELWAKE (1 << 22) /* GCI Wake Level Interrupt */ 4150 #define GCI_INTMASK_EVENTWAKE (1 << 23) /* GCI Wake Event Interrupt */ 4151 #define GCI_INTMASK_GPIOINT (1 << 25) /**< GCIGpioInt */ 4152 #define GCI_INTMASK_GPIOWAKE (1 << 26) /**< GCIGpioWake */ 4153 #define GCI_INTMASK_LHLWLWAKE (1 << 30) /* LHL WL wake */ 4154 4155 /* 4335 GCI WakeMask Register bits. */ 4156 #define GCI_WAKEMASK_RBI (1 << 0) /**< Rx Break Interrupt */ 4157 #define GCI_WAKEMASK_UB (1 << 1) /**< UART Break Interrupt */ 4158 #define GCI_WAKEMASK_SPE (1 << 2) /**< SECI Parity Error Interrupt */ 4159 #define GCI_WAKEMASK_SFE (1 << 3) /**< SECI Framing Error Interrupt */ 4160 #define GCI_WAKE_SRITI (1 << 9) /**< SECI Rx Idle Timer Interrupt */ 4161 #define GCI_WAKEMASK_STFF (1 << 10) /**< SECI Tx FIFO Full Interrupt */ 4162 #define GCI_WAKEMASK_STFAE (1 << 11) /**< SECI Tx FIFO Almost Empty Intr */ 4163 #define GCI_WAKEMASK_SRFAF (1 << 12) /**< SECI Rx FIFO Almost Full */ 4164 #define GCI_WAKEMASK_SRFNE (1 << 14) /**< SECI Rx FIFO Not Empty */ 4165 #define GCI_WAKEMASK_SRFOF (1 << 15) /**< SECI Rx FIFO Not Empty Timeout */ 4166 #define GCI_WAKEMASK_EVENT (1 << 21) /* GCI Event Interrupt */ 4167 #define GCI_WAKEMASK_LEVELWAKE (1 << 22) /* GCI Wake Level Interrupt */ 4168 #define GCI_WAKEMASK_EVENTWAKE (1 << 23) /* GCI Wake Event Interrupt */ 4169 #define GCI_WAKEMASK_GPIOINT (1 << 25) /**< GCIGpioInt */ 4170 #define GCI_WAKEMASK_GPIOWAKE (1 << 26) /**< GCIGpioWake */ 4171 #define GCI_WAKEMASK_LHLWLWAKE (1 << 30) /* LHL WL wake */ 4172 4173 #define GCI_WAKE_ON_GCI_GPIO1 1 4174 #define GCI_WAKE_ON_GCI_GPIO2 2 4175 #define GCI_WAKE_ON_GCI_GPIO3 3 4176 #define GCI_WAKE_ON_GCI_GPIO4 4 4177 #define GCI_WAKE_ON_GCI_GPIO5 5 4178 #define GCI_WAKE_ON_GCI_GPIO6 6 4179 #define GCI_WAKE_ON_GCI_GPIO7 7 4180 #define GCI_WAKE_ON_GCI_GPIO8 8 4181 #define GCI_WAKE_ON_GCI_SECI_IN 9 4182 4183 #define PMU_EXT_WAKE_MASK_0_SDIO (1 << 2) 4184 4185 /* =========== LHL regs =========== */ 4186 #define LHL_PWRSEQCTL_SLEEP_EN (1 << 0) 4187 #define LHL_PWRSEQCTL_PMU_SLEEP_MODE (1 << 1) 4188 #define LHL_PWRSEQCTL_PMU_FINAL_PMU_SLEEP_EN (1 << 2) 4189 #define LHL_PWRSEQCTL_PMU_TOP_ISO_EN (1 << 3) 4190 #define LHL_PWRSEQCTL_PMU_TOP_SLB_EN (1 << 4) 4191 #define LHL_PWRSEQCTL_PMU_TOP_PWRSW_EN (1 << 5) 4192 #define LHL_PWRSEQCTL_PMU_CLDO_PD (1 << 6) 4193 #define LHL_PWRSEQCTL_PMU_LPLDO_PD (1 << 7) 4194 #define LHL_PWRSEQCTL_PMU_RSRC6_EN (1 << 8) 4195 4196 #define PMU_SLEEP_MODE_0 (LHL_PWRSEQCTL_SLEEP_EN |\ 4197 LHL_PWRSEQCTL_PMU_FINAL_PMU_SLEEP_EN) 4198 4199 #define PMU_SLEEP_MODE_1 (LHL_PWRSEQCTL_SLEEP_EN |\ 4200 LHL_PWRSEQCTL_PMU_SLEEP_MODE |\ 4201 LHL_PWRSEQCTL_PMU_FINAL_PMU_SLEEP_EN |\ 4202 LHL_PWRSEQCTL_PMU_TOP_ISO_EN |\ 4203 LHL_PWRSEQCTL_PMU_TOP_SLB_EN |\ 4204 LHL_PWRSEQCTL_PMU_TOP_PWRSW_EN |\ 4205 LHL_PWRSEQCTL_PMU_CLDO_PD |\ 4206 LHL_PWRSEQCTL_PMU_RSRC6_EN) 4207 4208 #define PMU_SLEEP_MODE_2 (LHL_PWRSEQCTL_SLEEP_EN |\ 4209 LHL_PWRSEQCTL_PMU_SLEEP_MODE |\ 4210 LHL_PWRSEQCTL_PMU_FINAL_PMU_SLEEP_EN |\ 4211 LHL_PWRSEQCTL_PMU_TOP_ISO_EN |\ 4212 LHL_PWRSEQCTL_PMU_TOP_SLB_EN |\ 4213 LHL_PWRSEQCTL_PMU_TOP_PWRSW_EN |\ 4214 LHL_PWRSEQCTL_PMU_CLDO_PD |\ 4215 LHL_PWRSEQCTL_PMU_LPLDO_PD |\ 4216 LHL_PWRSEQCTL_PMU_RSRC6_EN) 4217 4218 #define LHL_PWRSEQ_CTL (0x000000ff) 4219 4220 /* LHL Top Level Power Up Control Register (lhl_top_pwrup_ctl_adr, Offset 0xE78) 4221 * Top Level Counter values for isolation, retention, Power Switch control 4222 */ 4223 #define LHL_PWRUP_ISOLATION_CNT (0x6 << 8) 4224 #define LHL_PWRUP_RETENTION_CNT (0x5 << 16) 4225 #define LHL_PWRUP_PWRSW_CNT (0x7 << 24) 4226 /* Mask is taken only for isolation 8:13 , Retention 16:21 , 4227 * Power Switch control 24:29 4228 */ 4229 #define LHL_PWRUP_CTL_MASK (0x3F3F3F00) 4230 #define LHL_PWRUP_CTL (LHL_PWRUP_ISOLATION_CNT |\ 4231 LHL_PWRUP_RETENTION_CNT |\ 4232 LHL_PWRUP_PWRSW_CNT) 4233 4234 #define LHL_PWRUP_ISOLATION_CNT_4347 (0x7 << 8) 4235 #define LHL_PWRUP_RETENTION_CNT_4347 (0x5 << 16) 4236 #define LHL_PWRUP_PWRSW_CNT_4347 (0x7 << 24) 4237 4238 #define LHL_PWRUP_CTL_4347 (LHL_PWRUP_ISOLATION_CNT_4347 |\ 4239 LHL_PWRUP_RETENTION_CNT_4347 |\ 4240 LHL_PWRUP_PWRSW_CNT_4347) 4241 4242 #define LHL_PWRUP2_CLDO_DN_CNT (0x0) 4243 #define LHL_PWRUP2_LPLDO_DN_CNT (0x0 << 8) 4244 #define LHL_PWRUP2_RSRC6_DN_CN (0x4 << 16) 4245 #define LHL_PWRUP2_RSRC7_DN_CN (0x0 << 24) 4246 #define LHL_PWRUP2_CTL_MASK (0x3F3F3F3F) 4247 #define LHL_PWRUP2_CTL (LHL_PWRUP2_CLDO_DN_CNT |\ 4248 LHL_PWRUP2_LPLDO_DN_CNT |\ 4249 LHL_PWRUP2_RSRC6_DN_CN |\ 4250 LHL_PWRUP2_RSRC7_DN_CN) 4251 4252 /* LHL Top Level Power Down Control Register (lhl_top_pwrdn_ctl_adr, Offset 0xE74) */ 4253 #define LHL_PWRDN_SLEEP_CNT (0x4) 4254 #define LHL_PWRDN_CTL_MASK (0x3F) 4255 4256 /* LHL Top Level Power Down Control 2 Register (lhl_top_pwrdn2_ctl_adr, Offset 0xE80) */ 4257 #define LHL_PWRDN2_CLDO_DN_CNT (0x4) 4258 #define LHL_PWRDN2_LPLDO_DN_CNT (0x4 << 8) 4259 #define LHL_PWRDN2_RSRC6_DN_CN (0x3 << 16) 4260 #define LHL_PWRDN2_RSRC7_DN_CN (0x0 << 24) 4261 #define LHL_PWRDN2_CTL (LHL_PWRDN2_CLDO_DN_CNT |\ 4262 LHL_PWRDN2_LPLDO_DN_CNT |\ 4263 LHL_PWRDN2_RSRC6_DN_CN |\ 4264 LHL_PWRDN2_RSRC7_DN_CN) 4265 #define LHL_PWRDN2_CTL_MASK (0x3F3F3F3F) 4266 4267 #define LHL_FAST_WRITE_EN (1 << 14) 4268 4269 /* WL ARM Timer0 Interrupt Mask (lhl_wl_armtim0_intrp_adr) */ 4270 #define LHL_WL_ARMTIM0_INTRP_EN 0x00000001 4271 #define LHL_WL_ARMTIM0_INTRP_EDGE_TRIGGER 0x00000002 4272 4273 /* WL MAC Timer0 Interrupt Mask (lhl_wl_mactim0_intrp_adr) */ 4274 #define LHL_WL_MACTIM0_INTRP_EN 0x00000001 4275 #define LHL_WL_MACTIM0_INTRP_EDGE_TRIGGER 0x00000002 4276 4277 /* LHL Wakeup Status (lhl_wkup_status_adr) */ 4278 #define LHL_WKUP_STATUS_WR_PENDING_ARMTIM0 0x00100000 4279 4280 /* WL ARM Timer0 Interrupt Status (lhl_wl_armtim0_st_adr) */ 4281 #define LHL_WL_ARMTIM0_ST_WL_ARMTIM_INT_ST 0x00000001 4282 4283 #define LHL_PS_MODE_0 0 4284 #define LHL_PS_MODE_1 1 4285 4286 /* GCI EventIntMask Register SW bits */ 4287 #define GCI_MAILBOXDATA_TOWLAN (1 << 0) 4288 #define GCI_MAILBOXDATA_TOBT (1 << 1) 4289 #define GCI_MAILBOXDATA_TONFC (1 << 2) 4290 #define GCI_MAILBOXDATA_TOGPS (1 << 3) 4291 #define GCI_MAILBOXDATA_TOLTE (1 << 4) 4292 #define GCI_MAILBOXACK_TOWLAN (1 << 8) 4293 #define GCI_MAILBOXACK_TOBT (1 << 9) 4294 #define GCI_MAILBOXACK_TONFC (1 << 10) 4295 #define GCI_MAILBOXACK_TOGPS (1 << 11) 4296 #define GCI_MAILBOXACK_TOLTE (1 << 12) 4297 #define GCI_WAKE_TOWLAN (1 << 16) 4298 #define GCI_WAKE_TOBT (1 << 17) 4299 #define GCI_WAKE_TONFC (1 << 18) 4300 #define GCI_WAKE_TOGPS (1 << 19) 4301 #define GCI_WAKE_TOLTE (1 << 20) 4302 #define GCI_SWREADY (1 << 24) 4303 4304 /* 4349 Group (4349, 4355, 4359) GCI SECI_OUT TX Status Regiser bits */ 4305 #define GCI_SECIOUT_TXSTATUS_TXHALT (1 << 0) 4306 #define GCI_SECIOUT_TXSTATUS_TI (1 << 16) 4307 4308 /* 4335 MUX options. each nibble belongs to a setting. Non-zero value specifies a logic 4309 * for now only UART for bootloader. 4310 */ 4311 #define MUXENAB4335_UART_MASK (0x0000000f) 4312 4313 #define MUXENAB4335_UART_SHIFT 0 4314 #define MUXENAB4335_HOSTWAKE_MASK (0x000000f0) /**< configure GPIO for SDIO host_wake */ 4315 #define MUXENAB4335_HOSTWAKE_SHIFT 4 4316 #define MUXENAB4335_GETIX(val, name) \ 4317 ((((val) & MUXENAB4335_ ## name ## _MASK) >> MUXENAB4335_ ## name ## _SHIFT) - 1) 4318 4319 /* 43012 MUX options */ 4320 #define MUXENAB43012_HOSTWAKE_MASK (0x00000001) 4321 #define MUXENAB43012_GETIX(val, name) (val - 1) 4322 4323 /* 4324 * Maximum delay for the PMU state transition in us. 4325 * This is an upper bound intended for spinwaits etc. 4326 */ 4327 #define PMU_MAX_TRANSITION_DLY 15000 4328 4329 /* PMU resource up transition time in ILP cycles */ 4330 #define PMURES_UP_TRANSITION 2 4331 4332 /* 53573 PMU Resource */ 4333 #define RES53573_REGULATOR_PU 0 4334 #define RES53573_XTALLDO_PU 1 4335 #define RES53573_XTAL_PU 2 4336 #define RES53573_MINI_PMU 3 4337 #define RES53573_RADIO_PU 4 4338 #define RES53573_ILP_REQ 5 4339 #define RES53573_ALP_AVAIL 6 4340 #define RES53573_CPUPLL_LDO_PU 7 4341 #define RES53573_CPU_PLL_PU 8 4342 #define RES53573_WLAN_BB_PLL_PU 9 4343 #define RES53573_MISCPLL_LDO_PU 10 4344 #define RES53573_MISCPLL_PU 11 4345 #define RES53573_AUDIOPLL_PU 12 4346 #define RES53573_PCIEPLL_LDO_PU 13 4347 #define RES53573_PCIEPLL_PU 14 4348 #define RES53573_DDRPLL_LDO_PU 15 4349 #define RES53573_DDRPLL_PU 16 4350 #define RES53573_HT_AVAIL 17 4351 #define RES53573_MACPHY_CLK_AVAIL 18 4352 #define RES53573_OTP_PU 19 4353 #define RES53573_RSVD20 20 4354 4355 /* 53573 Chip status registers */ 4356 #define CST53573_LOCK_CPUPLL 0x00000001 4357 #define CST53573_LOCK_MISCPLL 0x00000002 4358 #define CST53573_LOCK_DDRPLL 0x00000004 4359 #define CST53573_LOCK_PCIEPLL 0x00000008 4360 #define CST53573_EPHY_ENERGY_DET 0x00001f00 4361 #define CST53573_RAW_ENERGY 0x0003e000 4362 #define CST53573_BBPLL_LOCKED_O 0x00040000 4363 #define CST53573_SERDES_PIPE_PLLLOCK 0x00080000 4364 #define CST53573_STRAP_PCIE_EP_MODE 0x00100000 4365 #define CST53573_EPHY_PLL_LOCK 0x00200000 4366 #define CST53573_AUDIO_PLL_LOCKED_O 0x00400000 4367 #define CST53573_PCIE_LINK_IN_L11 0x01000000 4368 #define CST53573_PCIE_LINK_IN_L12 0x02000000 4369 #define CST53573_DIN_PACKAGEOPTION 0xf0000000 4370 4371 /* 53573 Chip control registers macro definitions */ 4372 #define PMU_53573_CHIPCTL1 1 4373 #define PMU_53573_CC1_HT_CLK_REQ_CTRL_MASK 0x00000010 4374 #define PMU_53573_CC1_HT_CLK_REQ_CTRL 0x00000010 4375 4376 #define PMU_53573_CHIPCTL3 3 4377 #define PMU_53573_CC3_ENABLE_CLOSED_LOOP_MASK 0x00000010 4378 #define PMU_53573_CC3_ENABLE_CLOSED_LOOP 0x00000000 4379 #define PMU_53573_CC3_ENABLE_BBPLL_PWRDOWN_MASK 0x00000002 4380 #define PMU_53573_CC3_ENABLE_BBPLL_PWRDOWN 0x00000002 4381 4382 #define CST53573_CHIPMODE_PCIE(cs) FALSE 4383 4384 /* SECI Status (0x134) & Mask (0x138) bits - Rev 35 */ 4385 #define SECI_STAT_BI (1 << 0) /* Break Interrupt */ 4386 #define SECI_STAT_SPE (1 << 1) /* Parity Error */ 4387 #define SECI_STAT_SFE (1 << 2) /* Parity Error */ 4388 #define SECI_STAT_SDU (1 << 3) /* Data Updated */ 4389 #define SECI_STAT_SADU (1 << 4) /* Auxiliary Data Updated */ 4390 #define SECI_STAT_SAS (1 << 6) /* AUX State */ 4391 #define SECI_STAT_SAS2 (1 << 7) /* AUX2 State */ 4392 #define SECI_STAT_SRITI (1 << 8) /* Idle Timer Interrupt */ 4393 #define SECI_STAT_STFF (1 << 9) /* Tx FIFO Full */ 4394 #define SECI_STAT_STFAE (1 << 10) /* Tx FIFO Almost Empty */ 4395 #define SECI_STAT_SRFE (1 << 11) /* Rx FIFO Empty */ 4396 #define SECI_STAT_SRFAF (1 << 12) /* Rx FIFO Almost Full */ 4397 #define SECI_STAT_SFCE (1 << 13) /* Flow Control Event */ 4398 4399 /* SECI configuration */ 4400 #define SECI_MODE_UART 0x0 4401 #define SECI_MODE_SECI 0x1 4402 #define SECI_MODE_LEGACY_3WIRE_BT 0x2 4403 #define SECI_MODE_LEGACY_3WIRE_WLAN 0x3 4404 #define SECI_MODE_HALF_SECI 0x4 4405 4406 #define SECI_RESET (1 << 0) 4407 #define SECI_RESET_BAR_UART (1 << 1) 4408 #define SECI_ENAB_SECI_ECI (1 << 2) 4409 #define SECI_ENAB_SECIOUT_DIS (1 << 3) 4410 #define SECI_MODE_MASK 0x7 4411 #define SECI_MODE_SHIFT 4 /* (bits 5, 6, 7) */ 4412 #define SECI_UPD_SECI (1 << 7) 4413 4414 #define SECI_AUX_TX_START (1 << 31) 4415 #define SECI_SLIP_ESC_CHAR 0xDB 4416 #define SECI_SIGNOFF_0 SECI_SLIP_ESC_CHAR 4417 #define SECI_SIGNOFF_1 0 4418 #define SECI_REFRESH_REQ 0xDA 4419 4420 /* seci clk_ctl_st bits */ 4421 #define CLKCTL_STS_HT_AVAIL_REQ (1 << 4) 4422 #define CLKCTL_STS_SECI_CLK_REQ (1 << 8) 4423 #define CLKCTL_STS_SECI_CLK_AVAIL (1 << 24) 4424 4425 #define SECI_UART_MSR_CTS_STATE (1 << 0) 4426 #define SECI_UART_MSR_RTS_STATE (1 << 1) 4427 #define SECI_UART_SECI_IN_STATE (1 << 2) 4428 #define SECI_UART_SECI_IN2_STATE (1 << 3) 4429 4430 /* GCI RX FIFO Control Register */ 4431 #define GCI_RXF_LVL_MASK (0xFF << 0) 4432 #define GCI_RXF_TIMEOUT_MASK (0xFF << 8) 4433 4434 /* GCI UART Registers' Bit definitions */ 4435 /* Seci Fifo Level Register */ 4436 #define SECI_TXF_LVL_MASK (0x3F << 8) 4437 #define TXF_AE_LVL_DEFAULT 0x4 4438 #define SECI_RXF_LVL_FC_MASK (0x3F << 16) 4439 4440 /* SeciUARTFCR Bit definitions */ 4441 #define SECI_UART_FCR_RFR (1 << 0) 4442 #define SECI_UART_FCR_TFR (1 << 1) 4443 #define SECI_UART_FCR_SR (1 << 2) 4444 #define SECI_UART_FCR_THP (1 << 3) 4445 #define SECI_UART_FCR_AB (1 << 4) 4446 #define SECI_UART_FCR_ATOE (1 << 5) 4447 #define SECI_UART_FCR_ARTSOE (1 << 6) 4448 #define SECI_UART_FCR_ABV (1 << 7) 4449 #define SECI_UART_FCR_ALM (1 << 8) 4450 4451 /* SECI UART LCR register bits */ 4452 #define SECI_UART_LCR_STOP_BITS (1 << 0) /* 0 - 1bit, 1 - 2bits */ 4453 #define SECI_UART_LCR_PARITY_EN (1 << 1) 4454 #define SECI_UART_LCR_PARITY (1 << 2) /* 0 - odd, 1 - even */ 4455 #define SECI_UART_LCR_RX_EN (1 << 3) 4456 #define SECI_UART_LCR_LBRK_CTRL (1 << 4) /* 1 => SECI_OUT held low */ 4457 #define SECI_UART_LCR_TXO_EN (1 << 5) 4458 #define SECI_UART_LCR_RTSO_EN (1 << 6) 4459 #define SECI_UART_LCR_SLIPMODE_EN (1 << 7) 4460 #define SECI_UART_LCR_RXCRC_CHK (1 << 8) 4461 #define SECI_UART_LCR_TXCRC_INV (1 << 9) 4462 #define SECI_UART_LCR_TXCRC_LSBF (1 << 10) 4463 #define SECI_UART_LCR_TXCRC_EN (1 << 11) 4464 #define SECI_UART_LCR_RXSYNC_EN (1 << 12) 4465 4466 #define SECI_UART_MCR_TX_EN (1 << 0) 4467 #define SECI_UART_MCR_PRTS (1 << 1) 4468 #define SECI_UART_MCR_SWFLCTRL_EN (1 << 2) 4469 #define SECI_UART_MCR_HIGHRATE_EN (1 << 3) 4470 #define SECI_UART_MCR_LOOPBK_EN (1 << 4) 4471 #define SECI_UART_MCR_AUTO_RTS (1 << 5) 4472 #define SECI_UART_MCR_AUTO_TX_DIS (1 << 6) 4473 #define SECI_UART_MCR_BAUD_ADJ_EN (1 << 7) 4474 #define SECI_UART_MCR_XONOFF_RPT (1 << 9) 4475 4476 /* SeciUARTLSR Bit Mask */ 4477 #define SECI_UART_LSR_RXOVR_MASK (1 << 0) 4478 #define SECI_UART_LSR_RFF_MASK (1 << 1) 4479 #define SECI_UART_LSR_TFNE_MASK (1 << 2) 4480 #define SECI_UART_LSR_TI_MASK (1 << 3) 4481 #define SECI_UART_LSR_TPR_MASK (1 << 4) 4482 #define SECI_UART_LSR_TXHALT_MASK (1 << 5) 4483 4484 /* SeciUARTMSR Bit Mask */ 4485 #define SECI_UART_MSR_CTSS_MASK (1 << 0) 4486 #define SECI_UART_MSR_RTSS_MASK (1 << 1) 4487 #define SECI_UART_MSR_SIS_MASK (1 << 2) 4488 #define SECI_UART_MSR_SIS2_MASK (1 << 3) 4489 4490 /* SeciUARTData Bits */ 4491 #define SECI_UART_DATA_RF_NOT_EMPTY_BIT (1 << 12) 4492 #define SECI_UART_DATA_RF_FULL_BIT (1 << 13) 4493 #define SECI_UART_DATA_RF_OVRFLOW_BIT (1 << 14) 4494 #define SECI_UART_DATA_FIFO_PTR_MASK 0xFF 4495 #define SECI_UART_DATA_RF_RD_PTR_SHIFT 16 4496 #define SECI_UART_DATA_RF_WR_PTR_SHIFT 24 4497 4498 /* LTECX: ltecxmux */ 4499 #define LTECX_EXTRACT_MUX(val, idx) (getbit4(&(val), (idx))) 4500 4501 /* LTECX: ltecxmux MODE */ 4502 #define LTECX_MUX_MODE_IDX 0 4503 #define LTECX_MUX_MODE_WCI2 0x0 4504 #define LTECX_MUX_MODE_GPIO 0x1 4505 4506 /* LTECX GPIO Information Index */ 4507 #define LTECX_NVRAM_FSYNC_IDX 0 4508 #define LTECX_NVRAM_LTERX_IDX 1 4509 #define LTECX_NVRAM_LTETX_IDX 2 4510 #define LTECX_NVRAM_WLPRIO_IDX 3 4511 4512 /* LTECX WCI2 Information Index */ 4513 #define LTECX_NVRAM_WCI2IN_IDX 0 4514 #define LTECX_NVRAM_WCI2OUT_IDX 1 4515 4516 /* LTECX: Macros to get GPIO/FNSEL/GCIGPIO */ 4517 #define LTECX_EXTRACT_PADNUM(val, idx) (getbit8(&(val), (idx))) 4518 #define LTECX_EXTRACT_FNSEL(val, idx) (getbit4(&(val), (idx))) 4519 #define LTECX_EXTRACT_GCIGPIO(val, idx) (getbit4(&(val), (idx))) 4520 4521 /* WLAN channel numbers - used from wifi.h */ 4522 4523 /* WLAN BW */ 4524 #define ECI_BW_20 0x0 4525 #define ECI_BW_25 0x1 4526 #define ECI_BW_30 0x2 4527 #define ECI_BW_35 0x3 4528 #define ECI_BW_40 0x4 4529 #define ECI_BW_45 0x5 4530 #define ECI_BW_50 0x6 4531 #define ECI_BW_ALL 0x7 4532 4533 /* WLAN - number of antenna */ 4534 #define WLAN_NUM_ANT1 TXANT_0 4535 #define WLAN_NUM_ANT2 TXANT_1 4536 4537 /* otpctrl1 0xF4 */ 4538 #define OTPC_FORCE_PWR_OFF 0x02000000 4539 /* chipcommon s/r registers introduced with cc rev >= 48 */ 4540 #define CC_SR_CTL0_ENABLE_MASK 0x1 4541 #define CC_SR_CTL0_ENABLE_SHIFT 0 4542 #define CC_SR_CTL0_EN_SR_ENG_CLK_SHIFT 1 /* sr_clk to sr_memory enable */ 4543 #define CC_SR_CTL0_RSRC_TRIGGER_SHIFT 2 /* Rising edge resource trigger 0 to sr_engine */ 4544 #define CC_SR_CTL0_MIN_DIV_SHIFT 6 /* Min division value for fast clk in sr_engine */ 4545 #define CC_SR_CTL0_EN_SBC_STBY_SHIFT 16 /* Allow Subcore mem StandBy? */ 4546 #define CC_SR_CTL0_EN_SR_ALP_CLK_MASK_SHIFT 18 4547 #define CC_SR_CTL0_EN_SR_HT_CLK_SHIFT 19 4548 #define CC_SR_CTL0_ALLOW_PIC_SHIFT 20 /* Allow pic to separate power domains */ 4549 #define CC_SR_CTL0_MAX_SR_LQ_CLK_CNT_SHIFT 25 4550 #define CC_SR_CTL0_EN_MEM_DISABLE_FOR_SLEEP 30 4551 4552 #define CC_SR_CTL1_SR_INIT_MASK 0x3FF 4553 #define CC_SR_CTL1_SR_INIT_SHIFT 0 4554 4555 #define ECI_INLO_PKTDUR_MASK 0x000000f0 /* [7:4] - 4 bits */ 4556 #define ECI_INLO_PKTDUR_SHIFT 4 4557 4558 /* gci chip control bits */ 4559 #define GCI_GPIO_CHIPCTRL_ENAB_IN_BIT 0 4560 #define GCI_GPIO_CHIPCTRL_ENAB_OP_BIT 1 4561 #define GCI_GPIO_CHIPCTRL_INVERT_BIT 2 4562 #define GCI_GPIO_CHIPCTRL_PULLUP_BIT 3 4563 #define GCI_GPIO_CHIPCTRL_PULLDN_BIT 4 4564 #define GCI_GPIO_CHIPCTRL_ENAB_BTSIG_BIT 5 4565 #define GCI_GPIO_CHIPCTRL_ENAB_OD_OP_BIT 6 4566 #define GCI_GPIO_CHIPCTRL_ENAB_EXT_GPIO_BIT 7 4567 4568 /* gci GPIO input status bits */ 4569 #define GCI_GPIO_STS_VALUE_BIT 0 4570 #define GCI_GPIO_STS_POS_EDGE_BIT 1 4571 #define GCI_GPIO_STS_NEG_EDGE_BIT 2 4572 #define GCI_GPIO_STS_FAST_EDGE_BIT 3 4573 #define GCI_GPIO_STS_CLEAR 0xF 4574 4575 #define GCI_GPIO_STS_EDGE_TRIG_BIT 0 4576 #define GCI_GPIO_STS_NEG_EDGE_TRIG_BIT 1 4577 #define GCI_GPIO_STS_DUAL_EDGE_TRIG_BIT 2 4578 #define GCI_GPIO_STS_WL_DIN_SELECT 6 4579 4580 #define GCI_GPIO_STS_VALUE (1 << GCI_GPIO_STS_VALUE_BIT) 4581 4582 /* SR Power Control */ 4583 #define SRPWR_DMN0_PCIE (0) /* PCIE */ 4584 #define SRPWR_DMN0_PCIE_SHIFT (SRPWR_DMN0_PCIE) /* PCIE */ 4585 #define SRPWR_DMN0_PCIE_MASK (1 << SRPWR_DMN0_PCIE_SHIFT) /* PCIE */ 4586 #define SRPWR_DMN1_ARMBPSD (1) /* ARM/BP/SDIO */ 4587 #define SRPWR_DMN1_ARMBPSD_SHIFT (SRPWR_DMN1_ARMBPSD) /* ARM/BP/SDIO */ 4588 #define SRPWR_DMN1_ARMBPSD_MASK (1 << SRPWR_DMN1_ARMBPSD_SHIFT) /* ARM/BP/SDIO */ 4589 #define SRPWR_DMN2_MACAUX (2) /* MAC/Phy Aux */ 4590 #define SRPWR_DMN2_MACAUX_SHIFT (SRPWR_DMN2_MACAUX) /* MAC/Phy Aux */ 4591 #define SRPWR_DMN2_MACAUX_MASK (1 << SRPWR_DMN2_MACAUX_SHIFT) /* MAC/Phy Aux */ 4592 #define SRPWR_DMN3_MACMAIN (3) /* MAC/Phy Main */ 4593 #define SRPWR_DMN3_MACMAIN_SHIFT (SRPWR_DMN3_MACMAIN) /* MAC/Phy Main */ 4594 #define SRPWR_DMN3_MACMAIN_MASK (1 << SRPWR_DMN3_MACMAIN_SHIFT) /* MAC/Phy Main */ 4595 4596 #define SRPWR_DMN4_MACSCAN (4) /* MAC/Phy Scan */ 4597 #define SRPWR_DMN4_MACSCAN_SHIFT (SRPWR_DMN4_MACSCAN) /* MAC/Phy Scan */ 4598 #define SRPWR_DMN4_MACSCAN_MASK (1 << SRPWR_DMN4_MACSCAN_SHIFT) /* MAC/Phy Scan */ 4599 4600 /* all power domain mask */ 4601 #define SRPWR_DMN_ALL_MASK(sih) si_srpwr_domain_all_mask(sih) 4602 4603 #define SRPWR_REQON_SHIFT (8) /* PowerOnRequest[11:8] */ 4604 #define SRPWR_REQON_MASK(sih) (SRPWR_DMN_ALL_MASK(sih) << SRPWR_REQON_SHIFT) 4605 4606 #define SRPWR_STATUS_SHIFT (16) /* ExtPwrStatus[19:16], RO */ 4607 #define SRPWR_STATUS_MASK(sih) (SRPWR_DMN_ALL_MASK(sih) << SRPWR_STATUS_SHIFT) 4608 4609 #define SRPWR_DMN_ID_SHIFT (28) /* PowerDomain[31:28], RO */ 4610 #define SRPWR_DMN_ID_MASK (0xF) 4611 4612 /* PMU Precision Usec Timer */ 4613 #define PMU_PREC_USEC_TIMER_ENABLE 0x1 4614 4615 /* FISCtrlStatus */ 4616 #define PMU_CLEAR_FIS_DONE_SHIFT 1u 4617 #define PMU_CLEAR_FIS_DONE_MASK (1u << PMU_CLEAR_FIS_DONE_SHIFT) 4618 4619 #endif /* _SBCHIPC_H */ 4620