1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Broadcom SiliconBackplane hardware register definitions. 4 * 5 * Copyright (C) 1999-2019, Broadcom. 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * 26 * <<Broadcom-WL-IPTag/Open:>> 27 * 28 * $Id: sbconfig.h 654158 2016-08-11 09:30:01Z $ 29 */ 30 31 #ifndef _SBCONFIG_H 32 #define _SBCONFIG_H 33 34 /* cpp contortions to concatenate w/arg prescan */ 35 #ifndef PAD 36 #define _PADLINE(line) pad ## line 37 #define _XSTR(line) _PADLINE(line) 38 #define PAD _XSTR(__LINE__) 39 #endif // endif 40 41 /* enumeration in SB is based on the premise that cores are contiguous in the 42 * enumeration space. 43 */ 44 #define SB_BUS_SIZE 0x10000 /**< Each bus gets 64Kbytes for cores */ 45 #define SB_BUS_BASE(sih, b) (SI_ENUM_BASE(sih) + (b) * SB_BUS_SIZE) 46 #define SB_BUS_MAXCORES (SB_BUS_SIZE / SI_CORE_SIZE) /**< Max cores per bus */ 47 48 /* 49 * Sonics Configuration Space Registers. 50 */ 51 #define SBCONFIGOFF 0xf00 /**< core sbconfig regs are top 256bytes of regs */ 52 #define SBCONFIGSIZE 256 /**< sizeof (sbconfig_t) */ 53 54 #define SBIPSFLAG 0x08 55 #define SBTPSFLAG 0x18 56 #define SBTMERRLOGA 0x48 /**< sonics >= 2.3 */ 57 #define SBTMERRLOG 0x50 /**< sonics >= 2.3 */ 58 #define SBADMATCH3 0x60 59 #define SBADMATCH2 0x68 60 #define SBADMATCH1 0x70 61 #define SBIMSTATE 0x90 62 #define SBINTVEC 0x94 63 #define SBTMSTATELOW 0x98 64 #define SBTMSTATEHIGH 0x9c 65 #define SBBWA0 0xa0 66 #define SBIMCONFIGLOW 0xa8 67 #define SBIMCONFIGHIGH 0xac 68 #define SBADMATCH0 0xb0 69 #define SBTMCONFIGLOW 0xb8 70 #define SBTMCONFIGHIGH 0xbc 71 #define SBBCONFIG 0xc0 72 #define SBBSTATE 0xc8 73 #define SBACTCNFG 0xd8 74 #define SBFLAGST 0xe8 75 #define SBIDLOW 0xf8 76 #define SBIDHIGH 0xfc 77 78 /* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have 79 * a few registers *below* that line. I think it would be very confusing to try 80 * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here, 81 */ 82 83 #define SBIMERRLOGA 0xea8 84 #define SBIMERRLOG 0xeb0 85 #define SBTMPORTCONNID0 0xed8 86 #define SBTMPORTLOCK0 0xef8 87 88 #if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) 89 90 typedef volatile struct _sbconfig { 91 uint32 PAD[2]; 92 uint32 sbipsflag; /**< initiator port ocp slave flag */ 93 uint32 PAD[3]; 94 uint32 sbtpsflag; /**< target port ocp slave flag */ 95 uint32 PAD[11]; 96 uint32 sbtmerrloga; /**< (sonics >= 2.3) */ 97 uint32 PAD; 98 uint32 sbtmerrlog; /**< (sonics >= 2.3) */ 99 uint32 PAD[3]; 100 uint32 sbadmatch3; /**< address match3 */ 101 uint32 PAD; 102 uint32 sbadmatch2; /**< address match2 */ 103 uint32 PAD; 104 uint32 sbadmatch1; /**< address match1 */ 105 uint32 PAD[7]; 106 uint32 sbimstate; /**< initiator agent state */ 107 uint32 sbintvec; /**< interrupt mask */ 108 uint32 sbtmstatelow; /**< target state */ 109 uint32 sbtmstatehigh; /**< target state */ 110 uint32 sbbwa0; /**< bandwidth allocation table0 */ 111 uint32 PAD; 112 uint32 sbimconfiglow; /**< initiator configuration */ 113 uint32 sbimconfighigh; /**< initiator configuration */ 114 uint32 sbadmatch0; /**< address match0 */ 115 uint32 PAD; 116 uint32 sbtmconfiglow; /**< target configuration */ 117 uint32 sbtmconfighigh; /**< target configuration */ 118 uint32 sbbconfig; /**< broadcast configuration */ 119 uint32 PAD; 120 uint32 sbbstate; /**< broadcast state */ 121 uint32 PAD[3]; 122 uint32 sbactcnfg; /**< activate configuration */ 123 uint32 PAD[3]; 124 uint32 sbflagst; /**< current sbflags */ 125 uint32 PAD[3]; 126 uint32 sbidlow; /**< identification */ 127 uint32 sbidhigh; /**< identification */ 128 } sbconfig_t; 129 130 #endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */ 131 132 /* sbipsflag */ 133 #define SBIPS_INT1_MASK 0x3f /**< which sbflags get routed to mips interrupt 1 */ 134 #define SBIPS_INT1_SHIFT 0 135 #define SBIPS_INT2_MASK 0x3f00 /**< which sbflags get routed to mips interrupt 2 */ 136 #define SBIPS_INT2_SHIFT 8 137 #define SBIPS_INT3_MASK 0x3f0000 /**< which sbflags get routed to mips interrupt 3 */ 138 #define SBIPS_INT3_SHIFT 16 139 #define SBIPS_INT4_MASK 0x3f000000 /**< which sbflags get routed to mips interrupt 4 */ 140 #define SBIPS_INT4_SHIFT 24 141 142 /* sbtpsflag */ 143 #define SBTPS_NUM0_MASK 0x3f /**< interrupt sbFlag # generated by this core */ 144 #define SBTPS_F0EN0 0x40 /**< interrupt is always sent on the backplane */ 145 146 /* sbtmerrlog */ 147 #define SBTMEL_CM 0x00000007 /**< command */ 148 #define SBTMEL_CI 0x0000ff00 /**< connection id */ 149 #define SBTMEL_EC 0x0f000000 /**< error code */ 150 #define SBTMEL_ME 0x80000000 /**< multiple error */ 151 152 /* sbimstate */ 153 #define SBIM_PC 0xf /**< pipecount */ 154 #define SBIM_AP_MASK 0x30 /**< arbitration policy */ 155 #define SBIM_AP_BOTH 0x00 /**< use both timeslaces and token */ 156 #define SBIM_AP_TS 0x10 /**< use timesliaces only */ 157 #define SBIM_AP_TK 0x20 /**< use token only */ 158 #define SBIM_AP_RSV 0x30 /**< reserved */ 159 #define SBIM_IBE 0x20000 /**< inbanderror */ 160 #define SBIM_TO 0x40000 /**< timeout */ 161 #define SBIM_BY 0x01800000 /**< busy (sonics >= 2.3) */ 162 #define SBIM_RJ 0x02000000 /**< reject (sonics >= 2.3) */ 163 164 /* sbtmstatelow */ 165 #define SBTML_RESET 0x0001 /**< reset */ 166 #define SBTML_REJ_MASK 0x0006 /**< reject field */ 167 #define SBTML_REJ 0x0002 /**< reject */ 168 #define SBTML_TMPREJ 0x0004 /**< temporary reject, for error recovery */ 169 170 #define SBTML_SICF_SHIFT 16 /**< Shift to locate the SI control flags in sbtml */ 171 172 /* sbtmstatehigh */ 173 #define SBTMH_SERR 0x0001 /**< serror */ 174 #define SBTMH_INT 0x0002 /**< interrupt */ 175 #define SBTMH_BUSY 0x0004 /**< busy */ 176 #define SBTMH_TO 0x0020 /**< timeout (sonics >= 2.3) */ 177 178 #define SBTMH_SISF_SHIFT 16 /**< Shift to locate the SI status flags in sbtmh */ 179 180 /* sbbwa0 */ 181 #define SBBWA_TAB0_MASK 0xffff /**< lookup table 0 */ 182 #define SBBWA_TAB1_MASK 0xffff /**< lookup table 1 */ 183 #define SBBWA_TAB1_SHIFT 16 184 185 /* sbimconfiglow */ 186 #define SBIMCL_STO_MASK 0x7 /**< service timeout */ 187 #define SBIMCL_RTO_MASK 0x70 /**< request timeout */ 188 #define SBIMCL_RTO_SHIFT 4 189 #define SBIMCL_CID_MASK 0xff0000 /**< connection id */ 190 #define SBIMCL_CID_SHIFT 16 191 192 /* sbimconfighigh */ 193 #define SBIMCH_IEM_MASK 0xc /**< inband error mode */ 194 #define SBIMCH_TEM_MASK 0x30 /**< timeout error mode */ 195 #define SBIMCH_TEM_SHIFT 4 196 #define SBIMCH_BEM_MASK 0xc0 /**< bus error mode */ 197 #define SBIMCH_BEM_SHIFT 6 198 199 /* sbadmatch0 */ 200 #define SBAM_TYPE_MASK 0x3 /**< address type */ 201 #define SBAM_AD64 0x4 /**< reserved */ 202 #define SBAM_ADINT0_MASK 0xf8 /**< type0 size */ 203 #define SBAM_ADINT0_SHIFT 3 204 #define SBAM_ADINT1_MASK 0x1f8 /**< type1 size */ 205 #define SBAM_ADINT1_SHIFT 3 206 #define SBAM_ADINT2_MASK 0x1f8 /**< type2 size */ 207 #define SBAM_ADINT2_SHIFT 3 208 #define SBAM_ADEN 0x400 /**< enable */ 209 #define SBAM_ADNEG 0x800 /**< negative decode */ 210 #define SBAM_BASE0_MASK 0xffffff00 /**< type0 base address */ 211 #define SBAM_BASE0_SHIFT 8 212 #define SBAM_BASE1_MASK 0xfffff000 /**< type1 base address for the core */ 213 #define SBAM_BASE1_SHIFT 12 214 #define SBAM_BASE2_MASK 0xffff0000 /**< type2 base address for the core */ 215 #define SBAM_BASE2_SHIFT 16 216 217 /* sbtmconfiglow */ 218 #define SBTMCL_CD_MASK 0xff /**< clock divide */ 219 #define SBTMCL_CO_MASK 0xf800 /**< clock offset */ 220 #define SBTMCL_CO_SHIFT 11 221 #define SBTMCL_IF_MASK 0xfc0000 /**< interrupt flags */ 222 #define SBTMCL_IF_SHIFT 18 223 #define SBTMCL_IM_MASK 0x3000000 /**< interrupt mode */ 224 #define SBTMCL_IM_SHIFT 24 225 226 /* sbtmconfighigh */ 227 #define SBTMCH_BM_MASK 0x3 /**< busy mode */ 228 #define SBTMCH_RM_MASK 0x3 /**< retry mode */ 229 #define SBTMCH_RM_SHIFT 2 230 #define SBTMCH_SM_MASK 0x30 /**< stop mode */ 231 #define SBTMCH_SM_SHIFT 4 232 #define SBTMCH_EM_MASK 0x300 /**< sb error mode */ 233 #define SBTMCH_EM_SHIFT 8 234 #define SBTMCH_IM_MASK 0xc00 /**< int mode */ 235 #define SBTMCH_IM_SHIFT 10 236 237 /* sbbconfig */ 238 #define SBBC_LAT_MASK 0x3 /**< sb latency */ 239 #define SBBC_MAX0_MASK 0xf0000 /**< maxccntr0 */ 240 #define SBBC_MAX0_SHIFT 16 241 #define SBBC_MAX1_MASK 0xf00000 /**< maxccntr1 */ 242 #define SBBC_MAX1_SHIFT 20 243 244 /* sbbstate */ 245 #define SBBS_SRD 0x1 /**< st reg disable */ 246 #define SBBS_HRD 0x2 /**< hold reg disable */ 247 248 /* sbidlow */ 249 #define SBIDL_CS_MASK 0x3 /**< config space */ 250 #define SBIDL_AR_MASK 0x38 /**< # address ranges supported */ 251 #define SBIDL_AR_SHIFT 3 252 #define SBIDL_SYNCH 0x40 /**< sync */ 253 #define SBIDL_INIT 0x80 /**< initiator */ 254 #define SBIDL_MINLAT_MASK 0xf00 /**< minimum backplane latency */ 255 #define SBIDL_MINLAT_SHIFT 8 256 #define SBIDL_MAXLAT 0xf000 /**< maximum backplane latency */ 257 #define SBIDL_MAXLAT_SHIFT 12 258 #define SBIDL_FIRST 0x10000 /**< this initiator is first */ 259 #define SBIDL_CW_MASK 0xc0000 /**< cycle counter width */ 260 #define SBIDL_CW_SHIFT 18 261 #define SBIDL_TP_MASK 0xf00000 /**< target ports */ 262 #define SBIDL_TP_SHIFT 20 263 #define SBIDL_IP_MASK 0xf000000 /**< initiator ports */ 264 #define SBIDL_IP_SHIFT 24 265 #define SBIDL_RV_MASK 0xf0000000 /**< sonics backplane revision code */ 266 #define SBIDL_RV_SHIFT 28 267 #define SBIDL_RV_2_2 0x00000000 /**< version 2.2 or earlier */ 268 #define SBIDL_RV_2_3 0x10000000 /**< version 2.3 */ 269 270 /* sbidhigh */ 271 #define SBIDH_RC_MASK 0x000f /**< revision code */ 272 #define SBIDH_RCE_MASK 0x7000 /**< revision code extension field */ 273 #define SBIDH_RCE_SHIFT 8 274 #define SBCOREREV(sbidh) \ 275 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK)) 276 #define SBIDH_CC_MASK 0x8ff0 /**< core code */ 277 #define SBIDH_CC_SHIFT 4 278 #define SBIDH_VC_MASK 0xffff0000 /**< vendor code */ 279 #define SBIDH_VC_SHIFT 16 280 281 #define SB_COMMIT 0xfd8 /**< update buffered registers value */ 282 283 /* vendor codes */ 284 #define SB_VEND_BCM 0x4243 /**< Broadcom's SB vendor code */ 285 286 #endif /* _SBCONFIG_H */ 287