1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Broadcom SiliconBackplane ARM definitions 4 * 5 * Copyright (C) 1999-2019, Broadcom. 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * 26 * <<Broadcom-WL-IPTag/Open:>> 27 * 28 * $Id: sbhndarm.h 799498 2019-01-16 06:02:27Z $ 29 */ 30 31 #ifndef _sbhndarm_h_ 32 #define _sbhndarm_h_ 33 34 #ifndef _LANGUAGE_ASSEMBLY 35 36 /* cpp contortions to concatenate w/arg prescan */ 37 #ifndef PAD 38 #define _PADLINE(line) pad ## line 39 #define _XSTR(line) _PADLINE(line) 40 #define PAD _XSTR(__LINE__) 41 #endif /* PAD */ 42 43 /* cortex-m3 */ 44 typedef volatile struct { 45 uint32 corecontrol; /* 0x0 */ 46 uint32 corestatus; /* 0x4 */ 47 uint32 PAD[1]; 48 uint32 biststatus; /* 0xc */ 49 uint32 nmiisrst; /* 0x10 */ 50 uint32 nmimask; /* 0x14 */ 51 uint32 isrmask; /* 0x18 */ 52 uint32 PAD[1]; 53 uint32 resetlog; /* 0x20 */ 54 uint32 gpioselect; /* 0x24 */ 55 uint32 gpioenable; /* 0x28 */ 56 uint32 PAD[1]; 57 uint32 bpaddrlo; /* 0x30 */ 58 uint32 bpaddrhi; /* 0x34 */ 59 uint32 bpdata; /* 0x38 */ 60 uint32 bpindaccess; /* 0x3c */ 61 uint32 ovlidx; /* 0x40 */ 62 uint32 ovlmatch; /* 0x44 */ 63 uint32 ovladdr; /* 0x48 */ 64 uint32 PAD[13]; 65 uint32 bwalloc; /* 0x80 */ 66 uint32 PAD[3]; 67 uint32 cyclecnt; /* 0x90 */ 68 uint32 inttimer; /* 0x94 */ 69 uint32 intmask; /* 0x98 */ 70 uint32 intstatus; /* 0x9c */ 71 uint32 PAD[80]; 72 uint32 clk_ctl_st; /* 0x1e0 */ 73 uint32 PAD[1]; 74 uint32 powerctl; /* 0x1e8 */ 75 } cm3regs_t; 76 #define ARM_CM3_REG(regs, reg) (&((cm3regs_t *)regs)->reg) 77 78 /* cortex-R4 */ 79 typedef volatile struct { 80 uint32 corecontrol; /* 0x0 */ 81 uint32 corecapabilities; /* 0x4 */ 82 uint32 corestatus; /* 0x8 */ 83 uint32 biststatus; /* 0xc */ 84 uint32 nmiisrst; /* 0x10 */ 85 uint32 nmimask; /* 0x14 */ 86 uint32 isrmask; /* 0x18 */ 87 uint32 swintreg; /* 0x1C */ 88 uint32 intstatus; /* 0x20 */ 89 uint32 intmask; /* 0x24 */ 90 uint32 cyclecnt; /* 0x28 */ 91 uint32 inttimer; /* 0x2c */ 92 uint32 gpioselect; /* 0x30 */ 93 uint32 gpioenable; /* 0x34 */ 94 uint32 PAD[2]; 95 uint32 bankidx; /* 0x40 */ 96 uint32 bankinfo; /* 0x44 */ 97 uint32 bankstbyctl; /* 0x48 */ 98 uint32 bankpda; /* 0x4c */ 99 uint32 PAD[6]; 100 uint32 tcampatchctrl; /* 0x68 */ 101 uint32 tcampatchtblbaseaddr; /* 0x6c */ 102 uint32 tcamcmdreg; /* 0x70 */ 103 uint32 tcamdatareg; /* 0x74 */ 104 uint32 tcambankxmaskreg; /* 0x78 */ 105 uint32 PAD[89]; 106 uint32 clk_ctl_st; /* 0x1e0 */ 107 uint32 PAD[1]; 108 uint32 powerctl; /* 0x1e8 */ 109 } cr4regs_t; 110 #define ARM_CR4_REG(regs, reg) (&((cr4regs_t *)regs)->reg) 111 112 /* cortex-A7 */ 113 typedef volatile struct { 114 uint32 corecontrol; /* 0x0 */ 115 uint32 corecapabilities; /* 0x4 */ 116 uint32 corestatus; /* 0x8 */ 117 uint32 tracecontrol; /* 0xc */ 118 uint32 PAD[8]; 119 uint32 gpioselect; /* 0x30 */ 120 uint32 gpioenable; /* 0x34 */ 121 uint32 PAD[106]; 122 uint32 clk_ctl_st; /* 0x1e0 */ 123 uint32 PAD[1]; 124 uint32 powerctl; /* 0x1e8 */ 125 } ca7regs_t; 126 #define ARM_CA7_REG(regs, reg) (&((ca7regs_t *)regs)->reg) 127 128 #if defined(__ARM_ARCH_7M__) 129 #define ARMREG(regs, reg) ARM_CM3_REG(regs, reg) 130 #endif /* __ARM_ARCH_7M__ */ 131 132 #if defined(__ARM_ARCH_7R__) 133 #define ARMREG(regs, reg) ARM_CR4_REG(regs, reg) 134 #endif /* __ARM_ARCH_7R__ */ 135 136 #if defined(__ARM_ARCH_7A__) 137 #define ARMREG(regs, reg) ARM_CA7_REG(regs, reg) 138 #endif /* __ARM_ARCH_7A__ */ 139 140 #endif /* _LANGUAGE_ASSEMBLY */ 141 142 #endif /* _sbhndarm_h_ */ 143