1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Misc utility routines for accessing the SOC Interconnects
4 * of Broadcom HNBU chips.
5 *
6 * Copyright (C) 1999-2019, Broadcom.
7 *
8 * Unless you and Broadcom execute a separate written software license
9 * agreement governing use of this software, this software is licensed to you
10 * under the terms of the GNU General Public License version 2 (the "GPL"),
11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
12 * following added to such license:
13 *
14 * As a special exception, the copyright holders of this software give you
15 * permission to link this software with independent modules, and to copy and
16 * distribute the resulting executable under terms of your choice, provided that
17 * you also meet, for each linked independent module, the terms and conditions of
18 * the license of that module. An independent module is a module which is not
19 * derived from this software. The special exception does not apply to any
20 * modifications of the software.
21 *
22 * Notwithstanding the above, under no circumstances may you combine this
23 * software in any way with any other Broadcom software provided under a license
24 * other than the GPL, without Broadcom's express prior written consent.
25 *
26 *
27 * <<Broadcom-WL-IPTag/Open:>>
28 *
29 * $Id: siutils.h 798061 2019-01-04 23:27:15Z $
30 */
31
32 #ifndef _siutils_h_
33 #define _siutils_h_
34
35 #ifdef SR_DEBUG
36 #include "wlioctl.h"
37 #endif /* SR_DEBUG */
38
39 #define WARM_BOOT 0xA0B0C0D0
40
41 #ifdef BCM_BACKPLANE_TIMEOUT
42
43 #define SI_MAX_ERRLOG_SIZE 4
44 typedef struct si_axi_error
45 {
46 uint32 error;
47 uint32 coreid;
48 uint32 errlog_lo;
49 uint32 errlog_hi;
50 uint32 errlog_id;
51 uint32 errlog_flags;
52 uint32 errlog_status;
53 } si_axi_error_t;
54
55 typedef struct si_axi_error_info
56 {
57 uint32 count;
58 si_axi_error_t axi_error[SI_MAX_ERRLOG_SIZE];
59 } si_axi_error_info_t;
60 #endif /* BCM_BACKPLANE_TIMEOUT */
61
62 /**
63 * Data structure to export all chip specific common variables
64 * public (read-only) portion of siutils handle returned by si_attach()/si_kattach()
65 */
66 struct si_pub {
67 uint socitype; /**< SOCI_SB, SOCI_AI */
68
69 uint bustype; /**< SI_BUS, PCI_BUS */
70 uint buscoretype; /**< PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
71 uint buscorerev; /**< buscore rev */
72 uint buscoreidx; /**< buscore index */
73 int ccrev; /**< chip common core rev */
74 uint32 cccaps; /**< chip common capabilities */
75 uint32 cccaps_ext; /**< chip common capabilities extension */
76 int pmurev; /**< pmu core rev */
77 uint32 pmucaps; /**< pmu capabilities */
78 uint boardtype; /**< board type */
79 uint boardrev; /* board rev */
80 uint boardvendor; /**< board vendor */
81 uint boardflags; /**< board flags */
82 uint boardflags2; /**< board flags2 */
83 uint boardflags4; /**< board flags4 */
84 uint chip; /**< chip number */
85 uint chiprev; /**< chip revision */
86 uint chippkg; /**< chip package option */
87 uint32 chipst; /**< chip status */
88 bool issim; /**< chip is in simulation or emulation */
89 uint socirev; /**< SOC interconnect rev */
90 bool pci_pr32414;
91 int gcirev; /**< gci core rev */
92 int lpflags; /**< low power flags */
93 uint32 enum_base; /**< backplane address where the chipcommon core resides */
94
95 #ifdef BCM_BACKPLANE_TIMEOUT
96 si_axi_error_info_t * err_info;
97 #endif /* BCM_BACKPLANE_TIMEOUT */
98
99 bool _multibp_enable;
100 };
101
102 /* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
103 * for monolithic driver, it is readonly to prevent accident change
104 */
105 typedef struct si_pub si_t;
106
107 /*
108 * Many of the routines below take an 'sih' handle as their first arg.
109 * Allocate this by calling si_attach(). Free it by calling si_detach().
110 * At any one time, the sih is logically focused on one particular si core
111 * (the "current core").
112 * Use si_setcore() or si_setcoreidx() to change the association to another core.
113 */
114 #define SI_OSH NULL /**< Use for si_kattach when no osh is available */
115
116 #define BADIDX (SI_MAXCORES + 1)
117
118 /* clkctl xtal what flags */
119 #define XTAL 0x1 /**< primary crystal oscillator (2050) */
120 #define PLL 0x2 /**< main chip pll */
121
122 /* clkctl clk mode */
123 #define CLK_FAST 0 /**< force fast (pll) clock */
124 #define CLK_DYNAMIC 2 /**< enable dynamic clock control */
125
126 /* GPIO usage priorities */
127 #define GPIO_DRV_PRIORITY 0 /**< Driver */
128 #define GPIO_APP_PRIORITY 1 /**< Application */
129 #define GPIO_HI_PRIORITY 2 /**< Highest priority. Ignore GPIO reservation */
130
131 /* GPIO pull up/down */
132 #define GPIO_PULLUP 0
133 #define GPIO_PULLDN 1
134
135 /* GPIO event regtype */
136 #define GPIO_REGEVT 0 /**< GPIO register event */
137 #define GPIO_REGEVT_INTMSK 1 /**< GPIO register event int mask */
138 #define GPIO_REGEVT_INTPOL 2 /**< GPIO register event int polarity */
139
140 /* device path */
141 #define SI_DEVPATH_BUFSZ 16 /**< min buffer size in bytes */
142
143 /* SI routine enumeration: to be used by update function with multiple hooks */
144 #define SI_DOATTACH 1
145 #define SI_PCIDOWN 2 /**< wireless interface is down */
146 #define SI_PCIUP 3 /**< wireless interface is up */
147
148 #ifdef SR_DEBUG
149 #define PMU_RES 31
150 #endif /* SR_DEBUG */
151
152 /* "access" param defines for si_seci_access() below */
153 #define SECI_ACCESS_STATUSMASK_SET 0
154 #define SECI_ACCESS_INTRS 1
155 #define SECI_ACCESS_UART_CTS 2
156 #define SECI_ACCESS_UART_RTS 3
157 #define SECI_ACCESS_UART_RXEMPTY 4
158 #define SECI_ACCESS_UART_GETC 5
159 #define SECI_ACCESS_UART_TXFULL 6
160 #define SECI_ACCESS_UART_PUTC 7
161 #define SECI_ACCESS_STATUSMASK_GET 8
162
163 #define ISSIM_ENAB(sih) FALSE
164
165 #define INVALID_ADDR (~0)
166
167 /* PMU clock/power control */
168 #if defined(BCMPMUCTL)
169 #define PMUCTL_ENAB(sih) (BCMPMUCTL)
170 #else
171 #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
172 #endif // endif
173
174 #if defined(BCMAOBENAB)
175 #define AOB_ENAB(sih) (BCMAOBENAB)
176 #else
177 #define AOB_ENAB(sih) ((sih)->ccrev >= 35 ? \
178 ((sih)->cccaps_ext & CC_CAP_EXT_AOB_PRESENT) : 0)
179 #endif /* BCMAOBENAB */
180
181 /* chipcommon clock/power control (exclusive with PMU's) */
182 #if defined(BCMPMUCTL) && BCMPMUCTL
183 #define CCCTL_ENAB(sih) (0)
184 #define CCPLL_ENAB(sih) (0)
185 #else
186 #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
187 #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
188 #endif // endif
189
190 typedef void (*gci_gpio_handler_t)(uint32 stat, void *arg);
191
192 /* External BT Coex enable mask */
193 #define CC_BTCOEX_EN_MASK 0x01
194 /* External PA enable mask */
195 #define GPIO_CTRL_EPA_EN_MASK 0x40
196 /* WL/BT control enable mask */
197 #define GPIO_CTRL_5_6_EN_MASK 0x60
198 #define GPIO_CTRL_7_6_EN_MASK 0xC0
199 #define GPIO_OUT_7_EN_MASK 0x80
200
201 /* CR4 specific defines used by the host driver */
202 #define SI_CR4_CAP (0x04)
203 #define SI_CR4_BANKIDX (0x40)
204 #define SI_CR4_BANKINFO (0x44)
205 #define SI_CR4_BANKPDA (0x4C)
206
207 #define ARMCR4_TCBBNB_MASK 0xf0
208 #define ARMCR4_TCBBNB_SHIFT 4
209 #define ARMCR4_TCBANB_MASK 0xf
210 #define ARMCR4_TCBANB_SHIFT 0
211
212 #define SICF_CPUHALT (0x0020)
213 #define ARMCR4_BSZ_MASK 0x7f
214 #define ARMCR4_BUNITSZ_MASK 0x200
215 #define ARMCR4_BSZ_8K 8192
216 #define ARMCR4_BSZ_1K 1024
217 #define SI_BPIND_1BYTE 0x1
218 #define SI_BPIND_2BYTE 0x3
219 #define SI_BPIND_4BYTE 0xF
220
221 #define GET_GCI_OFFSET(sih, gci_reg) \
222 (AOB_ENAB(sih)? OFFSETOF(gciregs_t, gci_reg) : OFFSETOF(chipcregs_t, gci_reg))
223
224 #define GET_GCI_CORE(sih) \
225 (AOB_ENAB(sih)? si_findcoreidx(sih, GCI_CORE_ID, 0) : SI_CC_IDX)
226
227 #include <osl_decl.h>
228 /* === exported functions === */
229 extern si_t *si_attach(uint pcidev, osl_t *osh, volatile void *regs, uint bustype,
230 void *sdh, char **vars, uint *varsz);
231 extern si_t *si_kattach(osl_t *osh);
232 extern void si_detach(si_t *sih);
233 extern volatile void *
234 si_d11_switch_addrbase(si_t *sih, uint coreunit);
235 extern uint si_corelist(si_t *sih, uint coreid[]);
236 extern uint si_coreid(si_t *sih);
237 extern uint si_flag(si_t *sih);
238 extern uint si_flag_alt(si_t *sih);
239 extern uint si_intflag(si_t *sih);
240 extern uint si_coreidx(si_t *sih);
241 extern uint si_coreunit(si_t *sih);
242 extern uint si_corevendor(si_t *sih);
243 extern uint si_corerev(si_t *sih);
244 extern uint si_corerev_minor(si_t *sih);
245 extern void *si_osh(si_t *sih);
246 extern void si_setosh(si_t *sih, osl_t *osh);
247 extern int si_backplane_access(si_t *sih, uint addr, uint size,
248 uint *val, bool read);
249 extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
250 extern uint si_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
251 extern uint si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask, uint val);
252 extern volatile uint32 *si_corereg_addr(si_t *sih, uint coreidx, uint regoff);
253 extern volatile void *si_coreregs(si_t *sih);
254 extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
255 extern uint si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val);
256 extern void *si_wrapperregs(si_t *sih);
257 extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val);
258 extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
259 extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val);
260 extern void si_commit(si_t *sih);
261 extern bool si_iscoreup(si_t *sih);
262 extern uint si_numcoreunits(si_t *sih, uint coreid);
263 extern uint si_numd11coreunits(si_t *sih);
264 extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
265 extern volatile void *si_setcoreidx(si_t *sih, uint coreidx);
266 extern volatile void *si_setcore(si_t *sih, uint coreid, uint coreunit);
267 extern uint32 si_oobr_baseaddr(si_t *sih, bool second);
268 extern volatile void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val);
269 extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
270 extern int si_numaddrspaces(si_t *sih);
271 extern uint32 si_addrspace(si_t *sih, uint spidx, uint baidx);
272 extern uint32 si_addrspacesize(si_t *sih, uint spidx, uint baidx);
273 extern void si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
274 extern int si_corebist(si_t *sih);
275 extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
276 extern void si_core_disable(si_t *sih, uint32 bits);
277 extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m);
278 extern uint si_chip_hostif(si_t *sih);
279 extern uint32 si_clock(si_t *sih);
280 extern uint32 si_alp_clock(si_t *sih); /* returns [Hz] units */
281 extern uint32 si_ilp_clock(si_t *sih); /* returns [Hz] units */
282 extern void si_pci_setup(si_t *sih, uint coremask);
283 extern void si_pcmcia_init(si_t *sih);
284 extern void si_setint(si_t *sih, int siflag);
285 extern bool si_backplane64(si_t *sih);
286 extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
287 void *intrsenabled_fn, void *intr_arg);
288 extern void si_deregister_intr_callback(si_t *sih);
289 extern void si_clkctl_init(si_t *sih);
290 extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih);
291 extern bool si_clkctl_cc(si_t *sih, uint mode);
292 extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
293 extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val);
294 extern void si_btcgpiowar(si_t *sih);
295 extern bool si_deviceremoved(si_t *sih);
296 extern void si_set_device_removed(si_t *sih, bool status);
297 extern uint32 si_sysmem_size(si_t *sih);
298 extern uint32 si_socram_size(si_t *sih);
299 extern uint32 si_socdevram_size(si_t *sih);
300 extern uint32 si_socram_srmem_size(si_t *sih);
301 extern void si_socram_set_bankpda(si_t *sih, uint32 bankidx, uint32 bankpda);
302 extern void si_socdevram(si_t *sih, bool set, uint8 *ennable, uint8 *protect, uint8 *remap);
303 extern bool si_socdevram_pkg(si_t *sih);
304 extern bool si_socdevram_remap_isenb(si_t *sih);
305 extern uint32 si_socdevram_remap_size(si_t *sih);
306
307 extern void si_watchdog(si_t *sih, uint ticks);
308 extern void si_watchdog_ms(si_t *sih, uint32 ms);
309 extern uint32 si_watchdog_msticks(void);
310 extern volatile void *si_gpiosetcore(si_t *sih);
311 extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority);
312 extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority);
313 extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority);
314 extern uint32 si_gpioin(si_t *sih);
315 extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority);
316 extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
317 extern uint32 si_gpioeventintmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
318 extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val);
319 extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority);
320 extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority);
321 extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val);
322 extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val);
323 extern uint32 si_gpio_int_enable(si_t *sih, bool enable);
324 extern void si_gci_uart_init(si_t *sih, osl_t *osh, uint8 seci_mode);
325 extern void si_gci_enable_gpio(si_t *sih, uint8 gpio, uint32 mask, uint32 value);
326 extern uint8 si_gci_host_wake_gpio_init(si_t *sih);
327 extern uint8 si_gci_time_sync_gpio_init(si_t *sih);
328 extern void si_gci_host_wake_gpio_enable(si_t *sih, uint8 gpio, bool state);
329 extern void si_gci_time_sync_gpio_enable(si_t *sih, uint8 gpio, bool state);
330
331 extern void si_invalidate_second_bar0win(si_t *sih);
332
333 extern void si_gci_shif_config_wake_pin(si_t *sih, uint8 gpio_n,
334 uint8 wake_events, bool gci_gpio);
335 extern void si_shif_int_enable(si_t *sih, uint8 gpio_n, uint8 wake_events, bool enable);
336
337 /* GCI interrupt handlers */
338 extern void si_gci_handler_process(si_t *sih);
339
340 extern void si_enable_gpio_wake(si_t *sih, uint8 *wake_mask, uint8 *cur_status, uint8 gci_gpio,
341 uint32 pmu_cc2_mask, uint32 pmu_cc2_value);
342
343 /* GCI GPIO event handlers */
344 extern void *si_gci_gpioint_handler_register(si_t *sih, uint8 gpio, uint8 sts,
345 gci_gpio_handler_t cb, void *arg);
346 extern void si_gci_gpioint_handler_unregister(si_t *sih, void* gci_i);
347
348 extern uint8 si_gci_gpio_status(si_t *sih, uint8 gci_gpio, uint8 mask, uint8 value);
349 extern void si_gci_config_wake_pin(si_t *sih, uint8 gpio_n, uint8 wake_events,
350 bool gci_gpio);
351 extern void si_gci_free_wake_pin(si_t *sih, uint8 gpio_n);
352
353 /* Wake-on-wireless-LAN (WOWL) */
354 extern bool si_pci_pmecap(si_t *sih);
355 extern bool si_pci_fastpmecap(struct osl_info *osh);
356 extern bool si_pci_pmestat(si_t *sih);
357 extern void si_pci_pmeclr(si_t *sih);
358 extern void si_pci_pmeen(si_t *sih);
359 extern void si_pci_pmestatclr(si_t *sih);
360 extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset);
361 extern uint si_pcie_writereg(void *sih, uint addrtype, uint offset, uint val);
362 extern void si_deepsleep_count(si_t *sih, bool arm_wakeup);
363
364 #ifdef BCMSDIO
365 extern void si_sdio_init(si_t *sih);
366 #endif // endif
367
368 extern uint16 si_d11_devid(si_t *sih);
369 extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice,
370 uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader);
371
372 extern uint32 si_seci_access(si_t *sih, uint32 val, int access);
373 extern volatile void* si_seci_init(si_t *sih, uint8 seci_mode);
374 extern void si_seci_clk_force(si_t *sih, bool val);
375 extern bool si_seci_clk_force_status(si_t *sih);
376
377 #define si_eci(sih) 0
si_eci_init(si_t * sih)378 static INLINE void * si_eci_init(si_t *sih) {return NULL;}
379 #define si_eci_notify_bt(sih, type, val) (0)
380 #define si_seci(sih) 0
381 #define si_seci_upd(sih, a) do {} while (0)
si_gci_init(si_t * sih)382 static INLINE void * si_gci_init(si_t *sih) {return NULL;}
383 #define si_seci_down(sih) do {} while (0)
384 #define si_gci(sih) 0
385
386 /* OTP status */
387 extern bool si_is_otp_disabled(si_t *sih);
388 extern bool si_is_otp_powered(si_t *sih);
389 extern void si_otp_power(si_t *sih, bool on, uint32* min_res_mask);
390
391 /* SPROM availability */
392 extern bool si_is_sprom_available(si_t *sih);
393
394 /* OTP/SROM CIS stuff */
395 extern int si_cis_source(si_t *sih);
396 #define CIS_DEFAULT 0
397 #define CIS_SROM 1
398 #define CIS_OTP 2
399
400 /* Fab-id information */
401 #define DEFAULT_FAB 0x0 /**< Original/first fab used for this chip */
402 #define CSM_FAB7 0x1 /**< CSM Fab7 chip */
403 #define TSMC_FAB12 0x2 /**< TSMC Fab12/Fab14 chip */
404 #define SMIC_FAB4 0x3 /**< SMIC Fab4 chip */
405
406 extern uint16 si_fabid(si_t *sih);
407 extern uint16 si_chipid(si_t *sih);
408
409 /*
410 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
411 * The returned path is NULL terminated and has trailing '/'.
412 * Return 0 on success, nonzero otherwise.
413 */
414 extern int si_devpath(si_t *sih, char *path, int size);
415 extern int si_devpath_pcie(si_t *sih, char *path, int size);
416 /* Read variable with prepending the devpath to the name */
417 extern char *si_getdevpathvar(si_t *sih, const char *name);
418 extern int si_getdevpathintvar(si_t *sih, const char *name);
419 extern char *si_coded_devpathvar(si_t *sih, char *varname, int var_len, const char *name);
420
421 extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val);
422 extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val);
423 extern uint8 si_pcieltrenable(si_t *sih, uint32 mask, uint32 val);
424 extern uint8 si_pcieobffenable(si_t *sih, uint32 mask, uint32 val);
425 extern uint32 si_pcieltr_reg(si_t *sih, uint32 reg, uint32 mask, uint32 val);
426 extern uint32 si_pcieltrspacing_reg(si_t *sih, uint32 mask, uint32 val);
427 extern uint32 si_pcieltrhysteresiscnt_reg(si_t *sih, uint32 mask, uint32 val);
428 extern void si_pcie_set_error_injection(si_t *sih, uint32 mode);
429 extern void si_pcie_set_L1substate(si_t *sih, uint32 substate);
430 extern uint32 si_pcie_get_L1substate(si_t *sih);
431 extern void si_war42780_clkreq(si_t *sih, bool clkreq);
432 extern void si_pci_down(si_t *sih);
433 extern void si_pci_up(si_t *sih);
434 extern void si_pci_sleep(si_t *sih);
435 extern void si_pcie_war_ovr_update(si_t *sih, uint8 aspm);
436 extern void si_pcie_power_save_enable(si_t *sih, bool enable);
437 extern void si_pcie_extendL1timer(si_t *sih, bool extend);
438 extern int si_pci_fixcfg(si_t *sih);
439 extern void si_chippkg_set(si_t *sih, uint);
440 extern bool si_is_warmboot(void);
441
442 extern void si_chipcontrl_restore(si_t *sih, uint32 val);
443 extern uint32 si_chipcontrl_read(si_t *sih);
444 extern void si_chipcontrl_srom4360(si_t *sih, bool on);
445 extern void si_srom_clk_set(si_t *sih); /**< for chips with fast BP clock */
446 extern void si_btc_enable_chipcontrol(si_t *sih);
447 extern void si_pmu_avb_clk_set(si_t *sih, osl_t *osh, bool set_flag);
448 /* === debug routines === */
449
450 extern bool si_taclear(si_t *sih, bool details);
451
452 #if defined(BCMDBG_PHYDUMP)
453 struct bcmstrbuf;
454 extern int si_dump_pcieinfo(si_t *sih, struct bcmstrbuf *b);
455 extern void si_dump_pmuregs(si_t *sih, struct bcmstrbuf *b);
456 extern int si_dump_pcieregs(si_t *sih, struct bcmstrbuf *b);
457 #endif // endif
458
459 #if defined(BCMDBG_PHYDUMP)
460 extern void si_dumpregs(si_t *sih, struct bcmstrbuf *b);
461 #endif // endif
462
463 extern uint32 si_ccreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
464 extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type);
465 extern int si_bpind_access(si_t *sih, uint32 addr_high, uint32 addr_low,
466 int32* data, bool read);
467 #ifdef SR_DEBUG
468 extern void si_dump_pmu(si_t *sih, void *pmu_var);
469 extern void si_pmu_keep_on(si_t *sih, int32 int_val);
470 extern uint32 si_pmu_keep_on_get(si_t *sih);
471 extern uint32 si_power_island_set(si_t *sih, uint32 int_val);
472 extern uint32 si_power_island_get(si_t *sih);
473 #endif /* SR_DEBUG */
474 extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val);
475 extern void si_pcie_set_request_size(si_t *sih, uint16 size);
476 extern uint16 si_pcie_get_request_size(si_t *sih);
477 extern void si_pcie_set_maxpayload_size(si_t *sih, uint16 size);
478 extern uint16 si_pcie_get_maxpayload_size(si_t *sih);
479 extern uint16 si_pcie_get_ssid(si_t *sih);
480 extern uint32 si_pcie_get_bar0(si_t *sih);
481 extern int si_pcie_configspace_cache(si_t *sih);
482 extern int si_pcie_configspace_restore(si_t *sih);
483 extern int si_pcie_configspace_get(si_t *sih, uint8 *buf, uint size);
484
485 #ifdef BCM_BACKPLANE_TIMEOUT
486 extern const si_axi_error_info_t * si_get_axi_errlog_info(si_t *sih);
487 extern void si_reset_axi_errlog_info(si_t * sih);
488 #endif /* BCM_BACKPLANE_TIMEOUT */
489
490 extern void si_update_backplane_timeouts(si_t *sih, bool enable, uint32 timeout, uint32 cid);
491
492 extern uint32 si_tcm_size(si_t *sih);
493 extern bool si_has_flops(si_t *sih);
494
495 extern int si_set_sromctl(si_t *sih, uint32 value);
496 extern uint32 si_get_sromctl(si_t *sih);
497
498 extern uint32 si_gci_direct(si_t *sih, uint offset, uint32 mask, uint32 val);
499 extern uint32 si_gci_indirect(si_t *sih, uint regidx, uint offset, uint32 mask, uint32 val);
500 extern uint32 si_gci_output(si_t *sih, uint reg, uint32 mask, uint32 val);
501 extern uint32 si_gci_input(si_t *sih, uint reg);
502 extern uint32 si_gci_int_enable(si_t *sih, bool enable);
503 extern void si_gci_reset(si_t *sih);
504 #ifdef BCMLTECOEX
505 extern void si_ercx_init(si_t *sih, uint32 ltecx_mux, uint32 ltecx_padnum,
506 uint32 ltecx_fnsel, uint32 ltecx_gcigpio);
507 #endif /* BCMLTECOEX */
508 extern void si_gci_seci_init(si_t *sih);
509 extern void si_wci2_init(si_t *sih, uint8 baudrate, uint32 ltecx_mux, uint32 ltecx_padnum,
510 uint32 ltecx_fnsel, uint32 ltecx_gcigpio, uint32 xtalfreq);
511
512 extern bool si_btcx_wci2_init(si_t *sih);
513
514 extern void si_gci_set_functionsel(si_t *sih, uint32 pin, uint8 fnsel);
515 extern uint32 si_gci_get_functionsel(si_t *sih, uint32 pin);
516 extern void si_gci_clear_functionsel(si_t *sih, uint8 fnsel);
517 extern uint8 si_gci_get_chipctrlreg_idx(uint32 pin, uint32 *regidx, uint32 *pos);
518 extern uint32 si_gci_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val);
519 extern uint32 si_gci_chipstatus(si_t *sih, uint reg);
520 extern uint8 si_enable_device_wake(si_t *sih, uint8 *wake_status, uint8 *cur_status);
521 extern uint8 si_get_device_wake_opt(si_t *sih);
522 extern void si_swdenable(si_t *sih, uint32 swdflag);
523 extern uint8 si_enable_perst_wake(si_t *sih, uint8 *perst_wake_mask, uint8 *perst_cur_status);
524
525 extern uint32 si_get_pmu_reg_addr(si_t *sih, uint32 offset);
526 #define CHIPCTRLREG1 0x1
527 #define CHIPCTRLREG2 0x2
528 #define CHIPCTRLREG3 0x3
529 #define CHIPCTRLREG4 0x4
530 #define CHIPCTRLREG5 0x5
531 #define MINRESMASKREG 0x618
532 #define MAXRESMASKREG 0x61c
533 #define CHIPCTRLADDR 0x650
534 #define CHIPCTRLDATA 0x654
535 #define RSRCTABLEADDR 0x620
536 #define RSRCUPDWNTIME 0x628
537 #define PMUREG_RESREQ_MASK 0x68c
538
539 void si_update_masks(si_t *sih);
540 void si_force_islanding(si_t *sih, bool enable);
541 extern uint32 si_pmu_res_req_timer_clr(si_t *sih);
542 extern void si_pmu_rfldo(si_t *sih, bool on);
543 extern uint32 si_pcie_set_ctrlreg(si_t *sih, uint32 sperst_mask, uint32 spert_val);
544 extern void si_pcie_ltr_war(si_t *sih);
545 extern void si_pcie_hw_LTR_war(si_t *sih);
546 extern void si_pcie_hw_L1SS_war(si_t *sih);
547 extern void si_pciedev_crwlpciegen2(si_t *sih);
548 extern void si_pcie_prep_D3(si_t *sih, bool enter_D3);
549 extern void si_pciedev_reg_pm_clk_period(si_t *sih);
550 extern void si_d11rsdb_core1_alt_reg_clk_dis(si_t *sih);
551 extern void si_d11rsdb_core1_alt_reg_clk_en(si_t *sih);
552 extern void si_pcie_disable_oobselltr(si_t *sih);
553 extern uint32 si_raw_reg(si_t *sih, uint32 reg, uint32 val, uint32 wrire_req);
554
555 #ifdef WLRSDB
556 extern void si_d11rsdb_core_disable(si_t *sih, uint32 bits);
557 extern void si_d11rsdb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
558 extern void set_secondary_d11_core(si_t *sih, volatile void **secmap, volatile void **secwrap);
559 #endif // endif
560
561 /* Macro to enable clock gating changes in different cores */
562 #define MEM_CLK_GATE_BIT 5
563 #define GCI_CLK_GATE_BIT 18
564
565 #define USBAPP_CLK_BIT 0
566 #define PCIE_CLK_BIT 3
567 #define ARMCR4_DBG_CLK_BIT 4
568 #define SAMPLE_SYNC_CLK_BIT 17
569 #define PCIE_TL_CLK_BIT 18
570 #define HQ_REQ_BIT 24
571 #define PLL_DIV2_BIT_START 9
572 #define PLL_DIV2_MASK (0x37 << PLL_DIV2_BIT_START)
573 #define PLL_DIV2_DIS_OP (0x37 << PLL_DIV2_BIT_START)
574
575 #define pmu_corereg(si, cc_idx, member, mask, val) \
576 (AOB_ENAB(si) ? \
577 si_pmu_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
578 OFFSETOF(pmuregs_t, member), mask, val): \
579 si_pmu_corereg(si, cc_idx, OFFSETOF(chipcregs_t, member), mask, val))
580
581 /* Used only for the regs present in the pmu core and not present in the old cc core */
582 #define PMU_REG_NEW(si, member, mask, val) \
583 si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
584 OFFSETOF(pmuregs_t, member), mask, val)
585
586 #define PMU_REG(si, member, mask, val) \
587 (AOB_ENAB(si) ? \
588 si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
589 OFFSETOF(pmuregs_t, member), mask, val): \
590 si_corereg(si, SI_CC_IDX, OFFSETOF(chipcregs_t, member), mask, val))
591
592 /* Used only for the regs present in the pmu core and not present in the old cc core */
593 #define PMU_REG_NEW(si, member, mask, val) \
594 si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
595 OFFSETOF(pmuregs_t, member), mask, val)
596
597 #define GCI_REG(si, offset, mask, val) \
598 (AOB_ENAB(si) ? \
599 si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
600 offset, mask, val): \
601 si_corereg(si, SI_CC_IDX, offset, mask, val))
602
603 /* Used only for the regs present in the gci core and not present in the old cc core */
604 #define GCI_REG_NEW(si, member, mask, val) \
605 si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
606 OFFSETOF(gciregs_t, member), mask, val)
607
608 #define LHL_REG(si, member, mask, val) \
609 si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
610 OFFSETOF(gciregs_t, member), mask, val)
611
612 #define CHIPC_REG(si, member, mask, val) \
613 si_corereg(si, SI_CC_IDX, OFFSETOF(chipcregs_t, member), mask, val)
614
615 /* GCI Macros */
616 #define ALLONES_32 0xFFFFFFFF
617 #define GCI_CCTL_SECIRST_OFFSET 0 /**< SeciReset */
618 #define GCI_CCTL_RSTSL_OFFSET 1 /**< ResetSeciLogic */
619 #define GCI_CCTL_SECIEN_OFFSET 2 /**< EnableSeci */
620 #define GCI_CCTL_FSL_OFFSET 3 /**< ForceSeciOutLow */
621 #define GCI_CCTL_SMODE_OFFSET 4 /**< SeciOpMode, 6:4 */
622 #define GCI_CCTL_US_OFFSET 7 /**< UpdateSeci */
623 #define GCI_CCTL_BRKONSLP_OFFSET 8 /**< BreakOnSleep */
624 #define GCI_CCTL_SILOWTOUT_OFFSET 9 /**< SeciInLowTimeout, 10:9 */
625 #define GCI_CCTL_RSTOCC_OFFSET 11 /**< ResetOffChipCoex */
626 #define GCI_CCTL_ARESEND_OFFSET 12 /**< AutoBTSigResend */
627 #define GCI_CCTL_FGCR_OFFSET 16 /**< ForceGciClkReq */
628 #define GCI_CCTL_FHCRO_OFFSET 17 /**< ForceHWClockReqOff */
629 #define GCI_CCTL_FREGCLK_OFFSET 18 /**< ForceRegClk */
630 #define GCI_CCTL_FSECICLK_OFFSET 19 /**< ForceSeciClk */
631 #define GCI_CCTL_FGCA_OFFSET 20 /**< ForceGciClkAvail */
632 #define GCI_CCTL_FGCAV_OFFSET 21 /**< ForceGciClkAvailValue */
633 #define GCI_CCTL_SCS_OFFSET 24 /**< SeciClkStretch, 31:24 */
634 #define GCI_CCTL_SCS 25 /* SeciClkStretch */
635
636 #define GCI_MODE_UART 0x0
637 #define GCI_MODE_SECI 0x1
638 #define GCI_MODE_BTSIG 0x2
639 #define GCI_MODE_GPIO 0x3
640 #define GCI_MODE_MASK 0x7
641
642 #define GCI_CCTL_LOWTOUT_DIS 0x0
643 #define GCI_CCTL_LOWTOUT_10BIT 0x1
644 #define GCI_CCTL_LOWTOUT_20BIT 0x2
645 #define GCI_CCTL_LOWTOUT_30BIT 0x3
646 #define GCI_CCTL_LOWTOUT_MASK 0x3
647
648 #define GCI_CCTL_SCS_DEF 0x19
649 #define GCI_CCTL_SCS_MASK 0xFF
650
651 #define GCI_SECIIN_MODE_OFFSET 0
652 #define GCI_SECIIN_GCIGPIO_OFFSET 4
653 #define GCI_SECIIN_RXID2IP_OFFSET 8
654
655 #define GCI_SECIIN_MODE_MASK 0x7
656 #define GCI_SECIIN_GCIGPIO_MASK 0xF
657
658 #define GCI_SECIOUT_MODE_OFFSET 0
659 #define GCI_SECIOUT_GCIGPIO_OFFSET 4
660 #define GCI_SECIOUT_LOOPBACK_OFFSET 8
661 #define GCI_SECIOUT_SECIINRELATED_OFFSET 16
662
663 #define GCI_SECIOUT_MODE_MASK 0x7
664 #define GCI_SECIOUT_GCIGPIO_MASK 0xF
665 #define GCI_SECIOUT_SECIINRELATED_MASK 0x1
666
667 #define GCI_SECIOUT_SECIINRELATED 0x1
668
669 #define GCI_SECIAUX_RXENABLE_OFFSET 0
670 #define GCI_SECIFIFO_RXENABLE_OFFSET 16
671
672 #define GCI_SECITX_ENABLE_OFFSET 0
673
674 #define GCI_GPIOCTL_INEN_OFFSET 0
675 #define GCI_GPIOCTL_OUTEN_OFFSET 1
676 #define GCI_GPIOCTL_PDN_OFFSET 4
677
678 #define GCI_GPIOIDX_OFFSET 16
679
680 #define GCI_LTECX_SECI_ID 0 /**< SECI port for LTECX */
681 #define GCI_LTECX_TXCONF_EN_OFFSET 2
682 #define GCI_LTECX_PRISEL_EN_OFFSET 3
683
684 /* To access per GCI bit registers */
685 #define GCI_REG_WIDTH 32
686
687 /* number of event summary bits */
688 #define GCI_EVENT_NUM_BITS 32
689
690 /* gci event bits per core */
691 #define GCI_EVENT_BITS_PER_CORE 4
692 #define GCI_EVENT_HWBIT_1 1
693 #define GCI_EVENT_HWBIT_2 2
694 #define GCI_EVENT_SWBIT_1 3
695 #define GCI_EVENT_SWBIT_2 4
696
697 #define GCI_MBDATA_TOWLAN_POS 96
698 #define GCI_MBACK_TOWLAN_POS 104
699 #define GCI_WAKE_TOWLAN_PO 112
700 #define GCI_SWREADY_POS 120
701
702 /* GCI bit positions */
703 /* GCI [127:000] = WLAN [127:0] */
704 #define GCI_WLAN_IP_ID 0
705 #define GCI_WLAN_BEGIN 0
706 #define GCI_WLAN_PRIO_POS (GCI_WLAN_BEGIN + 4)
707 #define GCI_WLAN_PERST_POS (GCI_WLAN_BEGIN + 15)
708
709 /* GCI [255:128] = BT [127:0] */
710 #define GCI_BT_IP_ID 1
711 #define GCI_BT_BEGIN 128
712 #define GCI_BT_MBDATA_TOWLAN_POS (GCI_BT_BEGIN + GCI_MBDATA_TOWLAN_POS)
713 #define GCI_BT_MBACK_TOWLAN_POS (GCI_BT_BEGIN + GCI_MBACK_TOWLAN_POS)
714 #define GCI_BT_WAKE_TOWLAN_POS (GCI_BT_BEGIN + GCI_WAKE_TOWLAN_PO)
715 #define GCI_BT_SWREADY_POS (GCI_BT_BEGIN + GCI_SWREADY_POS)
716
717 /* GCI [639:512] = LTE [127:0] */
718 #define GCI_LTE_IP_ID 4
719 #define GCI_LTE_BEGIN 512
720 #define GCI_LTE_FRAMESYNC_POS (GCI_LTE_BEGIN + 0)
721 #define GCI_LTE_RX_POS (GCI_LTE_BEGIN + 1)
722 #define GCI_LTE_TX_POS (GCI_LTE_BEGIN + 2)
723 #define GCI_LTE_WCI2TYPE_POS (GCI_LTE_BEGIN + 48)
724 #define GCI_LTE_WCI2TYPE_MASK 7
725 #define GCI_LTE_AUXRXDVALID_POS (GCI_LTE_BEGIN + 56)
726
727 /* Reg Index corresponding to ECI bit no x of ECI space */
728 #define GCI_REGIDX(x) ((x)/GCI_REG_WIDTH)
729 /* Bit offset of ECI bit no x in 32-bit words */
730 #define GCI_BITOFFSET(x) ((x)%GCI_REG_WIDTH)
731
732 /* BT SMEM Control Register 0 */
733 #define GCI_BT_SMEM_CTRL0_SUBCORE_ENABLE_PKILL (1 << 28)
734
735 /* End - GCI Macros */
736
737 #define AXI_OOB 0x7
738
739 extern void si_pll_sr_reinit(si_t *sih);
740 extern void si_pll_closeloop(si_t *sih);
741 void si_config_4364_d11_oob(si_t *sih, uint coreid);
742 extern void si_gci_set_femctrl(si_t *sih, osl_t *osh, bool set);
743 extern void si_gci_set_femctrl_mask_ant01(si_t *sih, osl_t *osh, bool set);
744 extern uint si_num_slaveports(si_t *sih, uint coreid);
745 extern uint32 si_get_slaveport_addr(si_t *sih, uint spidx, uint baidx,
746 uint core_id, uint coreunit);
747 extern uint32 si_get_d11_slaveport_addr(si_t *sih, uint spidx,
748 uint baidx, uint coreunit);
749 uint si_introff(si_t *sih);
750 void si_intrrestore(si_t *sih, uint intr_val);
751 void si_nvram_res_masks(si_t *sih, uint32 *min_mask, uint32 *max_mask);
752 extern uint32 si_xtalfreq(si_t *sih);
753 extern uint8 si_getspurmode(si_t *sih);
754 extern uint32 si_get_openloop_dco_code(si_t *sih);
755 extern void si_set_openloop_dco_code(si_t *sih, uint32 openloop_dco_code);
756 extern uint32 si_wrapper_dump_buf_size(si_t *sih);
757 extern uint32 si_wrapper_dump_binary(si_t *sih, uchar *p);
758 extern uint32 si_wrapper_dump_last_timeout(si_t *sih, uint32 *error, uint32 *core, uint32 *ba,
759 uchar *p);
760
761 /* SR Power Control */
762 extern uint32 si_srpwr_request(si_t *sih, uint32 mask, uint32 val);
763 extern uint32 si_srpwr_stat_spinwait(si_t *sih, uint32 mask, uint32 val);
764 extern uint32 si_srpwr_stat(si_t *sih);
765 extern uint32 si_srpwr_domain(si_t *sih);
766 extern uint32 si_srpwr_domain_all_mask(si_t *sih);
767
768 /* SR Power Control */
769 /* No capabilities bit so using chipid for now */
770 #define SRPWR_CAP(sih) (BCM4347_CHIP(sih->chip) || BCM4369_CHIP(sih->chip))
771
772 #ifdef BCMSRPWR
773 extern bool _bcmsrpwr;
774 #if defined(ROM_ENAB_RUNTIME_CHECK) || !defined(DONGLEBUILD)
775 #define SRPWR_ENAB() (_bcmsrpwr)
776 #elif defined(BCMSRPWR_DISABLED)
777 #define SRPWR_ENAB() (0)
778 #else
779 #define SRPWR_ENAB() (1)
780 #endif
781 #else
782 #define SRPWR_ENAB() (0)
783 #endif /* BCMSRPWR */
784
785 /*
786 * Multi-BackPlane architecture. Each can power up/down independently.
787 * Common backplane: shared between BT and WL
788 * ChipC, PCIe, GCI, PMU, SRs
789 * HW powers up as needed
790 * WL BackPlane (WLBP):
791 * ARM, TCM, Main, Aux
792 * Host needs to power up
793 */
794 #define MULTIBP_CAP(sih) (FALSE)
795 #define MULTIBP_ENAB(sih) ((sih) && (sih)->_multibp_enable)
796
797 uint32 si_enum_base(uint devid);
798
799 extern uint8 si_lhl_ps_mode(si_t *sih);
800
801 #ifdef UART_TRAP_DBG
802 void ai_dump_APB_Bridge_registers(si_t *sih);
803 #endif /* UART_TRAP_DBG */
804
805 void si_clrirq_idx(si_t *sih, uint core_idx);
806
807 /* return if scan core is present */
808 bool si_scan_core_present(si_t *sih);
809
810 #endif /* _siutils_h_ */
811