1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2024 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 10 /** 11 ************************************************************************************************************************ 12 * @file addrlib2.h 13 * @brief Contains the Addr::V2::Lib class definition. 14 ************************************************************************************************************************ 15 */ 16 17 #ifndef __ADDR2_LIB2_H__ 18 #define __ADDR2_LIB2_H__ 19 20 #include "addrlib.h" 21 22 namespace Addr 23 { 24 namespace V2 25 { 26 27 /** 28 ************************************************************************************************************************ 29 * @brief Flags for SwizzleModeTable 30 ************************************************************************************************************************ 31 */ 32 union SwizzleModeFlags 33 { 34 struct 35 { 36 // Swizzle mode 37 UINT_32 isLinear : 1; // Linear 38 39 // Block size 40 UINT_32 is256b : 1; // Block size is 256B 41 UINT_32 is4kb : 1; // Block size is 4KB 42 UINT_32 is64kb : 1; // Block size is 64KB 43 UINT_32 isVar : 1; // Block size is variable 44 45 UINT_32 isZ : 1; // Z order swizzle mode 46 UINT_32 isStd : 1; // Standard swizzle mode 47 UINT_32 isDisp : 1; // Display swizzle mode 48 UINT_32 isRot : 1; // Rotate swizzle mode 49 50 // XOR mode 51 UINT_32 isXor : 1; // XOR after swizzle if set 52 53 UINT_32 isT : 1; // T mode 54 55 // GFX10 56 UINT_32 isRtOpt : 1; // mode opt for render target 57 58 UINT_32 reserved : 20; // Reserved bits 59 }; 60 61 UINT_32 u32All; 62 }; 63 64 struct Dim2d 65 { 66 UINT_32 w; 67 UINT_32 h; 68 }; 69 70 struct Dim3d 71 { 72 UINT_32 w; 73 UINT_32 h; 74 UINT_32 d; 75 }; 76 77 enum AddrSwSet 78 { 79 AddrSwSetZ = 1 << ADDR_SW_Z, 80 AddrSwSetS = 1 << ADDR_SW_S, 81 AddrSwSetD = 1 << ADDR_SW_D, 82 AddrSwSetR = 1 << ADDR_SW_R, 83 84 AddrSwSetAll = AddrSwSetZ | AddrSwSetS | AddrSwSetD | AddrSwSetR, 85 }; 86 87 const UINT_32 Size256 = 256u; 88 const UINT_32 Size4K = 4096u; 89 const UINT_32 Size64K = 65536u; 90 91 const UINT_32 Log2Size256 = 8u; 92 const UINT_32 Log2Size4K = 12u; 93 const UINT_32 Log2Size64K = 16u; 94 95 /** 96 ************************************************************************************************************************ 97 * @brief Swizzle pattern information 98 ************************************************************************************************************************ 99 */ 100 // Accessed by index representing the logbase2 of (8bpp/16bpp/32bpp/64bpp/128bpp) 101 // contains the indices which map to 2D arrays SW_PATTERN_NIBBLE[0-9] which contain sections of an index equation. They are dependant on pipe# and bpe # 102 struct ADDR_SW_PATINFO 103 { 104 UINT_8 maxItemCount; 105 UINT_8 nibble01Idx; 106 UINT_16 nibble2Idx; 107 UINT_16 nibble3Idx; 108 UINT_8 nibble4Idx; 109 }; 110 111 112 /** 113 ************************************************************************************************************************ 114 * @brief This class contains asic independent address lib functionalities 115 ************************************************************************************************************************ 116 */ 117 class Lib : public Addr::Lib 118 { 119 public: 120 virtual ~Lib(); 121 122 static Lib* GetLib( 123 ADDR_HANDLE hLib); 124 GetInterfaceVersion()125 virtual UINT_32 GetInterfaceVersion() const 126 { 127 return 2; 128 } 129 // 130 // Interface stubs 131 // 132 133 // For data surface 134 ADDR_E_RETURNCODE ComputeSurfaceInfo( 135 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 136 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 137 138 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoord( 139 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 140 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 141 142 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddr( 143 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 144 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 145 146 ADDR_E_RETURNCODE CopyMemToSurface( 147 const ADDR2_COPY_MEMSURFACE_INPUT* pIn, 148 const ADDR2_COPY_MEMSURFACE_REGION* pRegions, 149 UINT_32 regionCount) const; 150 151 ADDR_E_RETURNCODE CopySurfaceToMem( 152 const ADDR2_COPY_MEMSURFACE_INPUT* pIn, 153 const ADDR2_COPY_MEMSURFACE_REGION* pRegions, 154 UINT_32 regionCount) const; 155 156 // For HTile 157 ADDR_E_RETURNCODE ComputeHtileInfo( 158 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 159 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; 160 161 ADDR_E_RETURNCODE ComputeHtileAddrFromCoord( 162 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 163 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 164 165 ADDR_E_RETURNCODE ComputeHtileCoordFromAddr( 166 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 167 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 168 169 // For CMask 170 ADDR_E_RETURNCODE ComputeCmaskInfo( 171 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 172 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const; 173 174 ADDR_E_RETURNCODE ComputeCmaskAddrFromCoord( 175 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 176 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 177 178 ADDR_E_RETURNCODE ComputeCmaskCoordFromAddr( 179 const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 180 ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut) const; 181 182 // For FMask 183 ADDR_E_RETURNCODE ComputeFmaskInfo( 184 const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn, 185 ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut); 186 187 ADDR_E_RETURNCODE ComputeFmaskAddrFromCoord( 188 const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 189 ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const; 190 191 ADDR_E_RETURNCODE ComputeFmaskCoordFromAddr( 192 const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 193 ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const; 194 195 // For DCC key 196 ADDR_E_RETURNCODE ComputeDccInfo( 197 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 198 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; 199 200 ADDR_E_RETURNCODE ComputeDccAddrFromCoord( 201 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 202 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 203 204 // Misc 205 ADDR_E_RETURNCODE ComputePipeBankXor( 206 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 207 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut); 208 209 ADDR_E_RETURNCODE ComputeSlicePipeBankXor( 210 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 211 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut); 212 213 ADDR_E_RETURNCODE ComputeSubResourceOffsetForSwizzlePattern( 214 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 215 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut); 216 217 ADDR_E_RETURNCODE ComputeNonBlockCompressedView( 218 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 219 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut); 220 221 ADDR_E_RETURNCODE Addr2GetPreferredSurfaceSetting( 222 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 223 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 224 225 ADDR_E_RETURNCODE GetPossibleSwizzleModes( 226 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 227 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 228 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn)229 virtual BOOL_32 IsValidDisplaySwizzleMode( 230 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const 231 { 232 ADDR_NOT_IMPLEMENTED(); 233 return ADDR_NOTIMPLEMENTED; 234 } 235 236 ADDR_E_RETURNCODE GetAllowedBlockSet( 237 ADDR2_SWMODE_SET allowedSwModeSet, 238 AddrResourceType rsrcType, 239 ADDR2_BLOCK_SET* pAllowedBlockSet) const; 240 241 ADDR_E_RETURNCODE GetAllowedSwSet( 242 ADDR2_SWMODE_SET allowedSwModeSet, 243 ADDR2_SWTYPE_SET* pAllowedSwSet) const; 244 245 protected: 246 Lib(); // Constructor is protected 247 Lib(const Client* pClient); 248 249 static const UINT_32 MaxNumOfBpp = 5; 250 static const UINT_32 MaxNumOfBppCMask = 4; 251 static const UINT_32 MaxNumOfAA = 4; 252 253 static const Dim2d Block256_2d[MaxNumOfBpp]; 254 static const Dim3d Block1K_3d[MaxNumOfBpp]; 255 256 static const UINT_32 PrtAlignment = 64 * 1024; 257 static const UINT_32 MaxMacroBits = 20; 258 259 static const UINT_32 MaxMipLevels = 16; 260 IsValidSwMode(AddrSwizzleMode swizzleMode)261 BOOL_32 IsValidSwMode(AddrSwizzleMode swizzleMode) const 262 { 263 return (m_swizzleModeTable[swizzleMode].u32All != 0); 264 } 265 266 // Checking block size IsBlock256b(AddrSwizzleMode swizzleMode)267 BOOL_32 IsBlock256b(AddrSwizzleMode swizzleMode) const 268 { 269 return m_swizzleModeTable[swizzleMode].is256b; 270 } 271 IsBlock4kb(AddrSwizzleMode swizzleMode)272 BOOL_32 IsBlock4kb(AddrSwizzleMode swizzleMode) const 273 { 274 return m_swizzleModeTable[swizzleMode].is4kb; 275 } 276 IsBlock64kb(AddrSwizzleMode swizzleMode)277 BOOL_32 IsBlock64kb(AddrSwizzleMode swizzleMode) const 278 { 279 return m_swizzleModeTable[swizzleMode].is64kb; 280 } 281 IsBlockVariable(AddrSwizzleMode swizzleMode)282 BOOL_32 IsBlockVariable(AddrSwizzleMode swizzleMode) const 283 { 284 return m_swizzleModeTable[swizzleMode].isVar; 285 } 286 287 // Checking swizzle mode IsLinear(AddrSwizzleMode swizzleMode)288 BOOL_32 IsLinear(AddrSwizzleMode swizzleMode) const 289 { 290 return m_swizzleModeTable[swizzleMode].isLinear; 291 } 292 IsRtOptSwizzle(AddrSwizzleMode swizzleMode)293 BOOL_32 IsRtOptSwizzle(AddrSwizzleMode swizzleMode) const 294 { 295 return m_swizzleModeTable[swizzleMode].isRtOpt; 296 } 297 IsZOrderSwizzle(AddrSwizzleMode swizzleMode)298 BOOL_32 IsZOrderSwizzle(AddrSwizzleMode swizzleMode) const 299 { 300 return m_swizzleModeTable[swizzleMode].isZ; 301 } 302 IsStandardSwizzle(AddrSwizzleMode swizzleMode)303 BOOL_32 IsStandardSwizzle(AddrSwizzleMode swizzleMode) const 304 { 305 return m_swizzleModeTable[swizzleMode].isStd; 306 } 307 IsDisplaySwizzle(AddrSwizzleMode swizzleMode)308 BOOL_32 IsDisplaySwizzle(AddrSwizzleMode swizzleMode) const 309 { 310 return m_swizzleModeTable[swizzleMode].isDisp; 311 } 312 IsRotateSwizzle(AddrSwizzleMode swizzleMode)313 BOOL_32 IsRotateSwizzle(AddrSwizzleMode swizzleMode) const 314 { 315 return m_swizzleModeTable[swizzleMode].isRot; 316 } 317 IsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)318 BOOL_32 IsStandardSwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 319 { 320 return HwlIsStandardSwizzle(resourceType, swizzleMode); 321 } 322 IsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)323 BOOL_32 IsDisplaySwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 324 { 325 return HwlIsDisplaySwizzle(resourceType, swizzleMode); 326 } 327 IsXor(AddrSwizzleMode swizzleMode)328 BOOL_32 IsXor(AddrSwizzleMode swizzleMode) const 329 { 330 return m_swizzleModeTable[swizzleMode].isXor; 331 } 332 IsPrt(AddrSwizzleMode swizzleMode)333 BOOL_32 IsPrt(AddrSwizzleMode swizzleMode) const 334 { 335 return m_swizzleModeTable[swizzleMode].isT; 336 } 337 IsNonPrtXor(AddrSwizzleMode swizzleMode)338 BOOL_32 IsNonPrtXor(AddrSwizzleMode swizzleMode) const 339 { 340 return (IsXor(swizzleMode) && (IsPrt(swizzleMode) == FALSE)); 341 } 342 343 // Checking resource type IsTex1d(AddrResourceType resourceType)344 static BOOL_32 IsTex1d(AddrResourceType resourceType) 345 { 346 return (resourceType == ADDR_RSRC_TEX_1D); 347 } 348 IsTex2d(AddrResourceType resourceType)349 static BOOL_32 IsTex2d(AddrResourceType resourceType) 350 { 351 return (resourceType == ADDR_RSRC_TEX_2D); 352 } 353 IsTex3d(AddrResourceType resourceType)354 static BOOL_32 IsTex3d(AddrResourceType resourceType) 355 { 356 return (resourceType == ADDR_RSRC_TEX_3D); 357 } 358 IsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)359 BOOL_32 IsThick(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 360 { 361 return HwlIsThick(resourceType, swizzleMode); 362 } 363 IsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)364 BOOL_32 IsThin(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 365 { 366 return HwlIsThin(resourceType, swizzleMode); 367 } 368 GetBlockSizeLog2(AddrSwizzleMode swizzleMode)369 UINT_32 GetBlockSizeLog2(AddrSwizzleMode swizzleMode) const 370 { 371 UINT_32 blockSizeLog2 = 0; 372 373 if (IsBlock256b(swizzleMode) || IsLinear(swizzleMode)) 374 { 375 blockSizeLog2 = 8; 376 } 377 else if (IsBlock4kb(swizzleMode)) 378 { 379 blockSizeLog2 = 12; 380 } 381 else if (IsBlock64kb(swizzleMode)) 382 { 383 blockSizeLog2 = 16; 384 } 385 else if (IsBlockVariable(swizzleMode) && (m_blockVarSizeLog2 != 0)) 386 { 387 blockSizeLog2 = m_blockVarSizeLog2; 388 } 389 else 390 { 391 ADDR_ASSERT_ALWAYS(); 392 } 393 394 return blockSizeLog2; 395 } 396 GetBlockSize(AddrSwizzleMode swizzleMode)397 UINT_32 GetBlockSize(AddrSwizzleMode swizzleMode) const 398 { 399 return (1 << GetBlockSizeLog2(swizzleMode)); 400 } 401 GetFmaskBpp(UINT_32 sample,UINT_32 frag)402 static UINT_32 GetFmaskBpp(UINT_32 sample, UINT_32 frag) 403 { 404 sample = (sample == 0) ? 1 : sample; 405 frag = (frag == 0) ? sample : frag; 406 407 UINT_32 fmaskBpp = Log2(frag); 408 409 if (sample > frag) 410 { 411 fmaskBpp++; 412 } 413 414 if (fmaskBpp == 3) 415 { 416 fmaskBpp = 4; 417 } 418 419 fmaskBpp = Max(8u, fmaskBpp * sample); 420 421 return fmaskBpp; 422 } 423 HwlIsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)424 virtual BOOL_32 HwlIsStandardSwizzle( 425 AddrResourceType resourceType, 426 AddrSwizzleMode swizzleMode) const 427 { 428 ADDR_NOT_IMPLEMENTED(); 429 return FALSE; 430 } 431 HwlIsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)432 virtual BOOL_32 HwlIsDisplaySwizzle( 433 AddrResourceType resourceType, 434 AddrSwizzleMode swizzleMode) const 435 { 436 ADDR_NOT_IMPLEMENTED(); 437 return FALSE; 438 } 439 HwlIsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)440 virtual BOOL_32 HwlIsThin( 441 AddrResourceType resourceType, 442 AddrSwizzleMode swizzleMode) const 443 { 444 ADDR_NOT_IMPLEMENTED(); 445 return FALSE; 446 } 447 HwlIsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)448 virtual BOOL_32 HwlIsThick( 449 AddrResourceType resourceType, 450 AddrSwizzleMode swizzleMode) const 451 { 452 ADDR_NOT_IMPLEMENTED(); 453 return FALSE; 454 } 455 HwlComputeHtileInfo(const ADDR2_COMPUTE_HTILE_INFO_INPUT * pIn,ADDR2_COMPUTE_HTILE_INFO_OUTPUT * pOut)456 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo( 457 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 458 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const 459 { 460 ADDR_NOT_IMPLEMENTED(); 461 return ADDR_NOTSUPPORTED; 462 } 463 HwlComputeCmaskInfo(const ADDR2_COMPUTE_CMASK_INFO_INPUT * pIn,ADDR2_COMPUTE_CMASK_INFO_OUTPUT * pOut)464 virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo( 465 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 466 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const 467 { 468 ADDR_NOT_IMPLEMENTED(); 469 return ADDR_NOTSUPPORTED; 470 } 471 HwlComputeDccInfo(const ADDR2_COMPUTE_DCCINFO_INPUT * pIn,ADDR2_COMPUTE_DCCINFO_OUTPUT * pOut)472 virtual ADDR_E_RETURNCODE HwlComputeDccInfo( 473 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 474 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const 475 { 476 ADDR_NOT_IMPLEMENTED(); 477 return ADDR_NOTSUPPORTED; 478 } 479 HwlSupportComputeDccAddrFromCoord(const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT * pIn)480 virtual ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord( 481 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn) 482 { 483 ADDR_NOT_IMPLEMENTED(); 484 return ADDR_NOTSUPPORTED; 485 } 486 HwlComputeDccAddrFromCoord(const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT * pOut)487 virtual VOID HwlComputeDccAddrFromCoord( 488 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 489 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) 490 { 491 ADDR_NOT_IMPLEMENTED(); 492 } 493 HwlComputeCmaskAddrFromCoord(const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT * pOut)494 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( 495 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 496 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) 497 { 498 ADDR_NOT_IMPLEMENTED(); 499 return ADDR_NOTSUPPORTED; 500 } 501 HwlComputeHtileAddrFromCoord(const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT * pOut)502 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( 503 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 504 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) 505 { 506 ADDR_NOT_IMPLEMENTED(); 507 return ADDR_NOTSUPPORTED; 508 } 509 HwlComputeHtileCoordFromAddr(const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT * pIn,ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT * pOut)510 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr( 511 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 512 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) 513 { 514 ADDR_NOT_IMPLEMENTED(); 515 return ADDR_NOTSUPPORTED; 516 } 517 HwlComputeBlock256Equation(AddrResourceType rsrcType,AddrSwizzleMode swMode,UINT_32 elementBytesLog2,ADDR_EQUATION * pEquation)518 virtual ADDR_E_RETURNCODE HwlComputeBlock256Equation( 519 AddrResourceType rsrcType, 520 AddrSwizzleMode swMode, 521 UINT_32 elementBytesLog2, 522 ADDR_EQUATION* pEquation) const 523 { 524 ADDR_NOT_IMPLEMENTED(); 525 return ADDR_NOTSUPPORTED; 526 } 527 HwlComputeThinEquation(AddrResourceType rsrcType,AddrSwizzleMode swMode,UINT_32 elementBytesLog2,ADDR_EQUATION * pEquation)528 virtual ADDR_E_RETURNCODE HwlComputeThinEquation( 529 AddrResourceType rsrcType, 530 AddrSwizzleMode swMode, 531 UINT_32 elementBytesLog2, 532 ADDR_EQUATION* pEquation) const 533 { 534 ADDR_NOT_IMPLEMENTED(); 535 return ADDR_NOTSUPPORTED; 536 } 537 HwlComputeThickEquation(AddrResourceType rsrcType,AddrSwizzleMode swMode,UINT_32 elementBytesLog2,ADDR_EQUATION * pEquation)538 virtual ADDR_E_RETURNCODE HwlComputeThickEquation( 539 AddrResourceType rsrcType, 540 AddrSwizzleMode swMode, 541 UINT_32 elementBytesLog2, 542 ADDR_EQUATION* pEquation) const 543 { 544 ADDR_NOT_IMPLEMENTED(); 545 return ADDR_NOTSUPPORTED; 546 } 547 HwlGetEquationIndex(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)548 virtual UINT_32 HwlGetEquationIndex( 549 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 550 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 551 { 552 ADDR_NOT_IMPLEMENTED(); 553 return ADDR_INVALID_EQUATION_INDEX; 554 } 555 GetEquationIndex(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)556 UINT_32 GetEquationIndex( 557 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 558 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 559 { 560 return HwlGetEquationIndex(pIn, pOut); 561 } 562 HwlComputePipeBankXor(const ADDR2_COMPUTE_PIPEBANKXOR_INPUT * pIn,ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT * pOut)563 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor( 564 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 565 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const 566 { 567 ADDR_NOT_IMPLEMENTED(); 568 return ADDR_NOTSUPPORTED; 569 } 570 HwlComputeSlicePipeBankXor(const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT * pIn,ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT * pOut)571 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor( 572 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 573 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const 574 { 575 ADDR_NOT_IMPLEMENTED(); 576 return ADDR_NOTSUPPORTED; 577 } 578 HwlComputeSubResourceOffsetForSwizzlePattern(const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT * pIn,ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT * pOut)579 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern( 580 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 581 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const 582 { 583 ADDR_NOT_IMPLEMENTED(); 584 return ADDR_NOTSUPPORTED; 585 } 586 HwlComputeNonBlockCompressedView(const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT * pIn,ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT * pOut)587 virtual ADDR_E_RETURNCODE HwlComputeNonBlockCompressedView( 588 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 589 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut) const 590 { 591 ADDR_NOT_IMPLEMENTED(); 592 return ADDR_NOTSUPPORTED; 593 } 594 HwlGetPreferredSurfaceSetting(const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT * pIn,ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT * pOut)595 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting( 596 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 597 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const 598 { 599 ADDR_NOT_IMPLEMENTED(); 600 return ADDR_NOTSUPPORTED; 601 } 602 HwlGetPossibleSwizzleModes(const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT * pIn,ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT * pOut)603 virtual ADDR_E_RETURNCODE HwlGetPossibleSwizzleModes( 604 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 605 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const 606 { 607 ADDR_NOT_IMPLEMENTED(); 608 return ADDR_NOTSUPPORTED; 609 } 610 HwlGetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet,AddrResourceType rsrcType,ADDR2_BLOCK_SET * pAllowedBlockSet)611 virtual ADDR_E_RETURNCODE HwlGetAllowedBlockSet( 612 ADDR2_SWMODE_SET allowedSwModeSet, 613 AddrResourceType rsrcType, 614 ADDR2_BLOCK_SET* pAllowedBlockSet) const 615 { 616 ADDR_NOT_IMPLEMENTED(); 617 return ADDR_NOTIMPLEMENTED; 618 } 619 HwlGetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet,ADDR2_SWTYPE_SET * pAllowedSwSet)620 virtual ADDR_E_RETURNCODE HwlGetAllowedSwSet( 621 ADDR2_SWMODE_SET allowedSwModeSet, 622 ADDR2_SWTYPE_SET* pAllowedSwSet) const 623 { 624 ADDR_NOT_IMPLEMENTED(); 625 return ADDR_NOTIMPLEMENTED; 626 } 627 HwlComputeSurfaceInfoSanityCheck(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn)628 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck( 629 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const 630 { 631 ADDR_NOT_IMPLEMENTED(); 632 return ADDR_NOTSUPPORTED; 633 } 634 HwlComputeSurfaceInfoTiled(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)635 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled( 636 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 637 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 638 { 639 ADDR_NOT_IMPLEMENTED(); 640 return ADDR_NOTIMPLEMENTED; 641 } 642 HwlComputeSurfaceInfoLinear(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)643 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear( 644 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 645 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 646 { 647 ADDR_NOT_IMPLEMENTED(); 648 return ADDR_NOTIMPLEMENTED; 649 } 650 HwlComputeSurfaceAddrFromCoordTiled(const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT * pOut)651 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled( 652 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 653 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const 654 { 655 ADDR_NOT_IMPLEMENTED(); 656 return ADDR_NOTIMPLEMENTED; 657 } 658 HwlCopyMemToSurface(const ADDR2_COPY_MEMSURFACE_INPUT * pIn,const ADDR2_COPY_MEMSURFACE_REGION * pRegions,UINT_32 regionCount)659 virtual ADDR_E_RETURNCODE HwlCopyMemToSurface( 660 const ADDR2_COPY_MEMSURFACE_INPUT* pIn, 661 const ADDR2_COPY_MEMSURFACE_REGION* pRegions, 662 UINT_32 regionCount) const 663 { 664 ADDR_NOT_IMPLEMENTED(); 665 return ADDR_NOTSUPPORTED; 666 } 667 HwlCopySurfaceToMem(const ADDR2_COPY_MEMSURFACE_INPUT * pIn,const ADDR2_COPY_MEMSURFACE_REGION * pRegions,UINT_32 regionCount)668 virtual ADDR_E_RETURNCODE HwlCopySurfaceToMem( 669 const ADDR2_COPY_MEMSURFACE_INPUT* pIn, 670 const ADDR2_COPY_MEMSURFACE_REGION* pRegions, 671 UINT_32 regionCount) const 672 { 673 ADDR_NOT_IMPLEMENTED(); 674 return ADDR_NOTSUPPORTED; 675 } 676 677 ADDR_E_RETURNCODE ComputeBlock256Equation( 678 AddrResourceType rsrcType, 679 AddrSwizzleMode swMode, 680 UINT_32 elementBytesLog2, 681 ADDR_EQUATION* pEquation) const; 682 683 ADDR_E_RETURNCODE ComputeThinEquation( 684 AddrResourceType rsrcType, 685 AddrSwizzleMode swMode, 686 UINT_32 elementBytesLog2, 687 ADDR_EQUATION* pEquation) const; 688 689 ADDR_E_RETURNCODE ComputeThickEquation( 690 AddrResourceType rsrcType, 691 AddrSwizzleMode swMode, 692 UINT_32 elementBytesLog2, 693 ADDR_EQUATION* pEquation) const; 694 695 ADDR_E_RETURNCODE ComputeSurfaceInfoSanityCheck( 696 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 697 698 ADDR_E_RETURNCODE ComputeSurfaceInfoLinear( 699 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 700 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 701 702 ADDR_E_RETURNCODE ComputeSurfaceInfoTiled( 703 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 704 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 705 706 ADDR_E_RETURNCODE CopyLinearSurface( 707 const ADDR2_COPY_MEMSURFACE_INPUT* pIn, 708 const ADDR2_COPY_MEMSURFACE_REGION* pRegions, 709 UINT_32 regionCount, 710 bool surfaceIsDst) const; 711 712 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordLinear( 713 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 714 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 715 716 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordTiled( 717 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 718 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 719 720 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddrLinear( 721 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 722 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 723 724 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddrTiled( 725 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 726 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 727 728 UINT_32 ComputeSurface2DMicroBlockOffset( 729 const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const; 730 731 UINT_32 ComputeSurface3DMicroBlockOffset( 732 const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const; 733 734 // Misc 735 ADDR_E_RETURNCODE ComputeBlockDimensionForSurf( 736 UINT_32* pWidth, 737 UINT_32* pHeight, 738 UINT_32* pDepth, 739 UINT_32 bpp, 740 UINT_32 numSamples, 741 AddrResourceType resourceType, 742 AddrSwizzleMode swizzleMode) const; 743 744 ADDR_E_RETURNCODE ComputeBlockDimension( 745 UINT_32* pWidth, 746 UINT_32* pHeight, 747 UINT_32* pDepth, 748 UINT_32 bpp, 749 AddrResourceType resourceType, 750 AddrSwizzleMode swizzleMode) const; 751 752 virtual VOID ComputeThinBlockDimension( 753 UINT_32* pWidth, 754 UINT_32* pHeight, 755 UINT_32* pDepth, 756 UINT_32 bpp, 757 UINT_32 numSamples, 758 AddrResourceType resourceType, 759 AddrSwizzleMode swizzleMode) const; 760 761 VOID ComputeThickBlockDimension( 762 UINT_32* pWidth, 763 UINT_32* pHeight, 764 UINT_32* pDepth, 765 UINT_32 bpp, 766 AddrResourceType resourceType, 767 AddrSwizzleMode swizzleMode) const; 768 ComputePadSize(const Dim3d * pBlkDim,UINT_32 width,UINT_32 height,UINT_32 numSlices,Dim3d * pPadDim)769 static UINT_64 ComputePadSize( 770 const Dim3d* pBlkDim, 771 UINT_32 width, 772 UINT_32 height, 773 UINT_32 numSlices, 774 Dim3d* pPadDim) 775 { 776 pPadDim->w = PowTwoAlign(width ,pBlkDim->w); 777 pPadDim->h = PowTwoAlign(height ,pBlkDim->h); 778 pPadDim->d = PowTwoAlign(numSlices, pBlkDim->d); 779 return static_cast<UINT_64>(pPadDim->w) * pPadDim->h * pPadDim->d; 780 } 781 782 static ADDR_E_RETURNCODE ExtractPipeBankXor( 783 UINT_32 pipeBankXor, 784 UINT_32 bankBits, 785 UINT_32 pipeBits, 786 UINT_32* pBankX, 787 UINT_32* pPipeX); 788 Valid3DMipSliceIdConstraint(UINT_32 numSlices,UINT_32 mipId,UINT_32 slice)789 static BOOL_32 Valid3DMipSliceIdConstraint( 790 UINT_32 numSlices, 791 UINT_32 mipId, 792 UINT_32 slice) 793 { 794 return (Max((numSlices >> mipId), 1u) > slice); 795 } 796 797 Dim3d GetMipTailDim( 798 AddrResourceType resourceType, 799 AddrSwizzleMode swizzleMode, 800 UINT_32 blockWidth, 801 UINT_32 blockHeight, 802 UINT_32 blockDepth) const; 803 IsLocalHeap(AddrResrouceLocation resourceType)804 static BOOL_32 IsLocalHeap(AddrResrouceLocation resourceType) 805 { 806 return ((resourceType == ADDR_RSRC_LOC_LOCAL) || 807 (resourceType == ADDR_RSRC_LOC_INVIS)); 808 } 809 IsInvisibleHeap(AddrResrouceLocation resourceType)810 static BOOL_32 IsInvisibleHeap(AddrResrouceLocation resourceType) 811 { 812 return (resourceType == ADDR_RSRC_LOC_INVIS); 813 } 814 IsNonlocalHeap(AddrResrouceLocation resourceType)815 static BOOL_32 IsNonlocalHeap(AddrResrouceLocation resourceType) 816 { 817 return ((resourceType == ADDR_RSRC_LOC_USWC) || 818 (resourceType == ADDR_RSRC_LOC_CACHED)); 819 } 820 GetPipeLog2ForMetaAddressing(BOOL_32 pipeAligned,AddrSwizzleMode swizzleMode)821 UINT_32 GetPipeLog2ForMetaAddressing(BOOL_32 pipeAligned, AddrSwizzleMode swizzleMode) const 822 { 823 UINT_32 numPipeLog2 = pipeAligned ? Min(m_pipesLog2 + m_seLog2, 5u) : 0; 824 825 if (IsXor(swizzleMode)) 826 { 827 UINT_32 maxPipeLog2 = GetBlockSizeLog2(swizzleMode) - m_pipeInterleaveLog2; 828 829 numPipeLog2 = Min(numPipeLog2, maxPipeLog2); 830 } 831 832 return numPipeLog2; 833 } 834 GetPipeNumForMetaAddressing(BOOL_32 pipeAligned,AddrSwizzleMode swizzleMode)835 UINT_32 GetPipeNumForMetaAddressing(BOOL_32 pipeAligned, AddrSwizzleMode swizzleMode) const 836 { 837 return (1 << GetPipeLog2ForMetaAddressing(pipeAligned, swizzleMode)); 838 } 839 VerifyMipLevelInfo(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn)840 VOID VerifyMipLevelInfo(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const 841 { 842 #if DEBUG 843 if (pIn->numMipLevels > 1) 844 { 845 UINT_32 actualMipLevels = 1; 846 switch (pIn->resourceType) 847 { 848 case ADDR_RSRC_TEX_3D: 849 // Fall through to share 2D case 850 actualMipLevels = Max(actualMipLevels, Log2(pIn->numSlices) + 1); 851 case ADDR_RSRC_TEX_2D: 852 // Fall through to share 1D case 853 actualMipLevels = Max(actualMipLevels, Log2(pIn->height) + 1); 854 case ADDR_RSRC_TEX_1D: 855 // Base 1D case 856 actualMipLevels = Max(actualMipLevels, Log2(pIn->width) + 1); 857 break; 858 default: 859 ADDR_ASSERT_ALWAYS(); 860 break; 861 } 862 // Client pass wrong number of MipLevels to addrlib and result will be bad. 863 // Not sure if we should fail this calling instead of putting an assertion here. 864 ADDR_ASSERT(actualMipLevels >= pIn->numMipLevels); 865 } 866 #endif 867 } 868 ApplyCustomerPipeBankXor(AddrSwizzleMode swizzleMode,UINT_32 pipeBankXor,UINT_32 bankBits,UINT_32 pipeBits,UINT_32 * pBlockOffset)869 ADDR_E_RETURNCODE ApplyCustomerPipeBankXor( 870 AddrSwizzleMode swizzleMode, 871 UINT_32 pipeBankXor, 872 UINT_32 bankBits, 873 UINT_32 pipeBits, 874 UINT_32* pBlockOffset) const 875 { 876 ADDR_E_RETURNCODE returnCode = ADDR_OK; 877 878 if (IsXor(swizzleMode)) 879 { 880 // Apply driver set bankPipeXor 881 UINT_32 bankX = 0; 882 UINT_32 pipeX = 0; 883 returnCode = ExtractPipeBankXor(pipeBankXor, bankBits, pipeBits, &bankX, &pipeX); 884 *pBlockOffset ^= (pipeX << m_pipeInterleaveLog2); 885 *pBlockOffset ^= (bankX << (m_pipeInterleaveLog2 + pipeBits)); 886 } 887 888 return returnCode; 889 } 890 891 UINT_32 GetPipeXorBits(UINT_32 macroBlockBits) const; 892 893 ADDR_E_RETURNCODE ApplyCustomizedPitchHeight( 894 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 895 UINT_32 elementBytes, 896 UINT_32 pitchAlignInElement, 897 UINT_32* pPitch, 898 UINT_32* pHeight) const; 899 900 VOID ComputeQbStereoInfo(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 901 902 VOID FilterInvalidEqSwizzleMode( 903 ADDR2_SWMODE_SET& allowedSwModeSet, 904 AddrResourceType resourceType, 905 UINT_32 elemLog2, 906 UINT_32 maxComponents) const; 907 908 #if DEBUG 909 VOID ValidateStereoInfo( 910 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 911 const ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 912 #endif 913 914 UINT_32 m_se; ///< Number of shader engine 915 UINT_32 m_rbPerSe; ///< Number of render backend per shader engine 916 UINT_32 m_maxCompFrag; ///< Number of max compressed fragment 917 918 UINT_32 m_banksLog2; ///< Number of bank Log2 919 UINT_32 m_pipesLog2; ///< Number of pipe per shader engine Log2 920 UINT_32 m_seLog2; ///< Number of shader engine Log2 921 UINT_32 m_rbPerSeLog2; ///< Number of render backend per shader engine Log2 922 UINT_32 m_maxCompFragLog2; ///< Number of max compressed fragment Log2 923 924 UINT_32 m_pipeInterleaveLog2; ///< Log2 of pipe interleave bytes 925 926 UINT_32 m_blockVarSizeLog2; ///< Log2 of block var size 927 928 SwizzleModeFlags m_swizzleModeTable[ADDR_SW_MAX_TYPE]; ///< Swizzle mode table 929 930 // Max number of swizzle mode supported for equation 931 static const UINT_32 MaxSwModeType = 32; 932 // Max number of resource type (2D/3D) supported for equation 933 static const UINT_32 MaxRsrcType = 2; 934 // Almost all swizzle mode + resource type support equation 935 static const UINT_32 EquationTableSize = MaxElementBytesLog2 * MaxSwModeType * MaxRsrcType; 936 // Equation table 937 ADDR_EQUATION m_equationTable[EquationTableSize]; 938 939 // Number of equation entries in the table 940 UINT_32 m_numEquations; 941 // Equation lookup table according to bpp and tile index 942 UINT_32 m_equationLookupTable[MaxRsrcType][MaxSwModeType][MaxElementBytesLog2]; 943 944 private: 945 // Disallow the copy constructor 946 Lib(const Lib& a); 947 948 // Disallow the assignment operator 949 Lib& operator=(const Lib& a); 950 }; 951 952 } // V2 953 } // Addr 954 955 #endif 956 957