1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 19 #include "hi_type.h" 20 #include "hi_common_adapt.h" 21 #include "hi_comm_sys_adapt.h" 22 23 #ifndef __SYS_HAL_H__ 24 #define __SYS_HAL_H__ 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif /* end of #ifdef __cplusplus */ 29 30 typedef enum { 31 SYS_DRVFUNCID_DDRRST, 32 SYS_DRVFUNCID_VIURST, 33 SYS_DRVFUNCID_VOURST, 34 SYS_DRVFUNCID_BUTT, 35 } sys_drvfuncid; 36 37 hi_void sys_hal_soft_int_en(hi_bool soft_int_en); 38 hi_s32 sys_hal_vi_bus_reset(hi_bool reset); 39 hi_s32 sys_hal_vi_bus_clk_en(hi_bool clk_en); 40 hi_s32 sys_hal_vi_ppc_reset(hi_bool reset); 41 hi_s32 sys_hal_vi_ppc_clk_en(hi_bool clk_en); 42 43 hi_s32 sys_hal_vi_port_reset(hi_vi_dev dev, hi_bool reset); 44 hi_s32 sys_hal_vi_port_clk_en(hi_vi_dev dev, hi_bool clk_en); 45 hi_s32 sys_hal_vi_ppc_port_clk_en(hi_vi_dev dev, hi_bool clk_en); 46 47 hi_s32 sys_hal_vi_ppc_chn_clk_en(hi_vi_pipe pipe, hi_bool clk_en); 48 hi_s32 sys_hal_vi_isp_cfg_reset(hi_vi_pipe pipe, hi_bool reset); 49 hi_s32 sys_hal_vi_isp_core_reset(hi_vi_pipe pipe, hi_bool reset); 50 hi_s32 sys_hal_vi_isp_clk_en(hi_vi_pipe pipe, hi_bool clk_en); 51 52 hi_s32 sys_hal_vi_proc_reset(hi_s32 vi_proc, hi_bool reset); 53 hi_s32 sys_hal_vi_proc_clk_en(hi_s32 vi_proc, hi_bool clk_en); 54 55 hi_void sys_hal_vi_get_cap_online_flag(hi_u32 *value); 56 hi_s32 sys_hal_vi_cap_proc_online_sel(hi_s32 vi_proc, hi_bool online); 57 hi_s32 sys_hal_vpss_online_sel(hi_s32 vpss, hi_bool online); 58 hi_s32 sys_hal_vi_dev_inputi_sel(hi_s32 vi_dev, hi_s32 input); 59 hi_void sys_hal_vi_get_proc_clk(hi_u32 *read_crg63); 60 hi_void sys_hal_vi_get_port_clk(hi_u32 *value); 61 hi_void sys_hal_vi_set_port_clk(hi_s32 dev, hi_u32 clk_sel); 62 hi_void sys_hal_vi_get_ppc_clk(hi_u32 *value); 63 hi_void sys_hal_vi_set_ppc_clk(hi_u32 clk_sel); 64 hi_void sys_hal_vi_set_proc_clk(hi_u32 clk_sel); 65 hi_void sys_hal_get_isp_fe_clk(hi_u32 *read_crg64); 66 hi_void sys_hal_set_isp_fe_clk(hi_s32 pipe, hi_u32 clk_sel); 67 hi_void sys_hal_set_vi_cap_priority(hi_u32 id, hi_u32 priority_write); 68 #ifdef HI_DEBUG 69 hi_void sys_hal_set_vedu_priority(hi_u32 id, hi_u32 priority_write); 70 hi_void sys_hal_set_vgs_priority(hi_u32 id, hi_u32 priority_rrite); 71 #endif 72 hi_s32 sys_hal_vou_bus_reset_sel(hi_bool reset); 73 hi_s32 sys_hal_vou_hd_out_pctrl(hi_s32 dev, hi_bool clk_reverse); 74 hi_s32 sys_hal_vou_cfg_clk_en(hi_s32 dev, hi_bool clk_en); 75 hi_s32 sys_hal_vou_core_clk_en(hi_s32 dev, hi_bool clk_en); 76 hi_s32 sys_hal_vou_ppc_clk_en(hi_s32 dev, hi_bool clk_en); 77 hi_s32 sys_hal_vou_out_clk_en(hi_s32 dev, hi_bool clk_en); 78 hi_s32 sys_hal_vou_apb_clk_en(hi_s32 dev, hi_bool clk_en); 79 hi_s32 sys_hal_vou_bus_clk_en(hi_bool clk_en); 80 hi_s32 sys_hal_vou_dev_clk_en(hi_s32 vo_dev, hi_bool clk_en); 81 hi_s32 sys_hal_vou_hd_clk_sel(hi_s32 dev, hi_u32 clk_sel); 82 hi_s32 sys_hal_vou_hd0_div_mode(hi_s32 dev, hi_u32 hd1_div_mod); 83 hi_s32 sys_hal_vou_out_clk_sel(hi_s32 dev, hi_u32 clk_sel); 84 hi_s32 sys_hal_vou_hd_hdmi_clk_div(hi_s32 dev, hi_u32 hdmi_clk_div); 85 hi_s32 sys_hal_vou_hdmi_tx_clk_en(hi_s32 dev, hi_bool hdmi_tx_clk_en); 86 hi_s32 sys_hal_vou_mipi_tx_clk_en(hi_s32 dev, hi_bool mi_pi_tx_clk_en); 87 hi_s32 sys_hal_vou_hd_dac_clk_en(hi_bool clk_en); 88 hi_s32 sys_hal_vou_lcd_clk_en(hi_s32 vo_dev, hi_bool clk_en); 89 hi_s32 sys_hal_lcd_mclk_div(hi_u32 mclk_div); 90 hi_s32 sys_hal_lcd_data_mode(hi_u32 data_mode); 91 hi_s32 sys_hal_vou_bt_clk_en(hi_s32 vo_dev, hi_bool bt_clk_en); 92 #ifdef HI_DEBUG 93 hi_s32 sys_hal_vou_bt_clk_sel(hi_s32 vo_dev, hi_u32 bt_clk_ch_sel); 94 #endif 95 hi_s32 sys_hal_vou_mipi_clk_en(hi_s32 vo_dev, hi_bool mipi_clk_en); 96 hi_s32 sys_hal_vou_hdmi_clk_en(hi_s32 vo_dev, hi_bool hdmi_clk_en); 97 98 hi_s32 sys_hal_set_vo_pll_frac(hi_s32 pll, hi_u32 bits_set); 99 hi_s32 sys_hal_set_vo_pll_postdiv1(hi_s32 pll, hi_u32 bits_set); 100 hi_s32 sys_hal_set_vo_pll_postdiv2(hi_s32 pll, hi_u32 bits_set); 101 hi_s32 sys_hal_set_vo_pll_refdiv(hi_s32 pll, hi_u32 bits_set); 102 hi_s32 sys_hal_set_vo_pll_fbdiv(hi_s32 pll, hi_u32 bits_set); 103 104 hi_s32 sys_hal_vedu_reset_sel(hi_s32 vedu, hi_bool reset); 105 hi_s32 sys_hal_vedu_clk_en(hi_s32 vedu, hi_bool clk_en); 106 hi_s32 sys_hal_vedu_sed_clk_en(hi_s32 vedu, hi_bool clk_en); 107 #ifdef HI_DEBUG 108 hi_s32 sys_hal_vedu_clk_sel(hi_s32 vedu, hi_u32 clk_sel); 109 #endif 110 hi_s32 sys_hal_vpss_reset_sel(hi_s32 vpss, hi_bool reset); 111 hi_s32 sys_hal_vpss_clk_en(hi_s32 vpss, hi_bool clk_en); 112 #ifdef HI_DEBUG 113 hi_s32 sys_hal_vpss_get_frequency(hi_u32 *freq); 114 hi_s32 sys_hal_vpss_set_frequency(hi_u32 freq); 115 #endif 116 #ifdef CONFIG_HI_AVS_SUPPORT 117 hi_s32 sys_hal_avs_reset_sel(hi_bool reset); 118 hi_s32 sys_hal_avs_clk_en(hi_bool clk_en); 119 #endif 120 hi_s32 sys_hal_jpge_reset_sel(hi_bool reset); 121 hi_s32 sys_hal_jpge_clk_en(hi_bool clk_en); 122 123 hi_s32 sys_hal_jpgd_clk_en(hi_bool clk_en); 124 hi_s32 sys_hal_jpgd_reset_sel(hi_bool reset); 125 126 hi_s32 sys_hal_wk_cnn_reset_sel(hi_bool reset); 127 hi_s32 sys_hal_wk_cnn_clk_en(hi_bool clk_en); 128 hi_s32 sys_hal_wk_cnn_clk_set(hi_u32 clk_value); 129 hi_s32 sys_hal_wk_cnn_get_clk_state(hi_bool *clk_state); 130 131 hi_s32 sys_hal_md_clk_en(hi_bool clk_en); 132 hi_s32 sys_hal_ive_reset_sel(hi_bool reset); 133 hi_s32 sys_hal_ive_clk_en(hi_bool clk_en); 134 #ifdef HI_DEBUG 135 hi_s32 sys_hal_ive_set_frequency(hi_u32 clk_value); 136 #endif 137 hi_s32 sys_hal_vgs_reset_sel(hi_s32 vgs, hi_bool reset); 138 hi_s32 sys_hal_vgs_clk_en(hi_s32 vgs, hi_bool clk_en); 139 #ifdef HI_DEBUG 140 hi_s32 sys_hal_vgs_get_clk_sel(hi_s32 vgs, hi_u32 *clk_sel); 141 hi_s32 sys_hal_vgs_set_clk_sel(hi_s32 vgs, hi_u32 clk_sel); 142 #endif 143 hi_s32 sys_hal_vgs_bootroom_set_ram_using(hi_bool vgs_using); 144 hi_s32 sys_hal_gdc_reset_sel(hi_s32 gdc, hi_bool reset); 145 hi_s32 sys_hal_gdc_clk_en(hi_s32 gdc, hi_bool clk_en); 146 hi_s32 sys_hal_gdc_get_clk_state(hi_bool *clk_state); 147 hi_s32 sys_hal_gdc_nnie_set_ram_using(hi_bool gdc_using); 148 #ifdef HI_DEBUG 149 hi_s32 sys_hal_gdc_get_clk_sel(hi_u32 *clk_sel); 150 hi_s32 sys_hal_gdc_set_clk_sel(hi_ulong ul_clk_sel); 151 #endif 152 153 hi_s32 sys_hal_get_custom_code(hi_u32 *custom_code); 154 155 hi_s32 sys_hal_init(hi_void); 156 hi_void sys_hal_exit(hi_void); 157 158 hi_s32 sys_hal_aio_reset_sel(hi_bool reset); 159 hi_s32 sys_hal_aio_clk_en(hi_bool clk_en); 160 161 hi_u32 sys_hal_get_chip_id(hi_void); 162 hi_void sys_hal_get_unique_id(hi_unique_id *unique_id); 163 164 hi_void sys_hal_read_security_state(hi_bool *security); 165 166 /* nnie gdc mutual exclusion */ 167 hi_s32 sys_hal_gdc_nnie_mutex_sel(hi_bool gdc_sel); 168 /* nnie and venc mutual exclusion, while venc resolution is greater than 2688*1944 */ 169 hi_s32 sys_hal_venc_nnie_mutex_sel(hi_bool venc_sel); 170 hi_s32 sys_hal_nnie_get_mutex_state(hi_bool *mutex_state); 171 hi_s32 sys_hal_nnie_gdc_get_mutex_state(hi_bool *mutex_state); 172 hi_void sys_hal_get_sys(hi_u8 *read_crg_58); 173 hi_void sys_hal_get_sct(hi_u64 *sct); 174 hi_s32 sys_hal_udir_get_clk_state(hi_bool *clk_state); 175 hi_s32 sys_hal_udir_set_clk(hi_bool clk_state); 176 hi_s32 sys_hal_udir_reset_sel(hi_bool reset); 177 178 #ifdef __cplusplus 179 } 180 #endif /* end of #ifdef __cplusplus */ 181 182 #endif /* end of #ifndef __SYS_HAL_H__ */ 183