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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dsdhci-pxa.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: marvell,armada-380-sdhci
23 reg-names:
26 - reg-names
[all …]
/kernel/linux/linux-5.10/include/linux/platform_data/
Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
28 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */
104 u32 clk; member
105 u32 t_bacc; /* burst access valid clock to output delay */
106 u32 t_ces; /* CS setup time to clk */
107 u32 t_avds; /* ADV setup time to clk */
[all …]
/kernel/linux/linux-6.6/include/linux/platform_data/
Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
28 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */
104 u32 clk; member
105 u32 t_bacc; /* burst access valid clock to output delay */
106 u32 t_ces; /* CS setup time to clk */
107 u32 t_avds; /* ADV setup time to clk */
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/
Dsdhci-pxa.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: marvell,armada-380-sdhci
23 reg-names:
26 - reg-names
[all …]
/kernel/linux/linux-5.10/drivers/memory/
Dpl172.c1 // SPDX-License-Identifier: GPL-2.0
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
13 #include <linux/clk.h>
53 struct clk *clk; member
61 int cycles; in pl172_timing_prop() local
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
66 if (cycles < 0) { in pl172_timing_prop()
67 cycles = 0; in pl172_timing_prop()
68 } else if (cycles > max) { in pl172_timing_prop()
69 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
[all …]
/kernel/linux/linux-6.6/drivers/memory/
Dpl172.c1 // SPDX-License-Identifier: GPL-2.0
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
13 #include <linux/clk.h>
53 struct clk *clk; member
61 int cycles; in pl172_timing_prop() local
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
66 if (cycles < 0) { in pl172_timing_prop()
67 cycles = 0; in pl172_timing_prop()
68 } else if (cycles > max) { in pl172_timing_prop()
69 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
[all …]
/kernel/linux/linux-6.6/drivers/watchdog/
Drenesas_wdt.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
6 * Copyright (C) 2015-17 Renesas Electronics Corporation
9 #include <linux/clk.h>
10 #include <linux/delay.h>
37 DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
39 /* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
40 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
54 struct clk *clk; member
64 writel_relaxed(val, priv->base + reg); in rwdt_write()
[all …]
Dimgpdc_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * -----
12 * The timeout value is rounded to the next power of two clock cycles.
16 * timeout = 2^(delay + 1) clock cycles
18 * Where 'delay' is the value written in PDC_WDT_CONFIG register.
21 * as a power of two number of watchdog clock cycles. The current implementation
25 * The following table shows how the user-configured timeout relates
29 * -----------------------------------
40 #include <linux/clk.h>
84 struct clk *wdt_clk;
[all …]
/kernel/linux/linux-5.10/drivers/watchdog/
Drenesas_wdt.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
6 * Copyright (C) 2015-17 Renesas Electronics Corporation
9 #include <linux/clk.h>
10 #include <linux/delay.h>
36 DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
38 /* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
39 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
62 writel_relaxed(val, priv->base + reg); in rwdt_write()
69 rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT); in rwdt_init_timeout()
[all …]
Dimgpdc_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * -----
12 * The timeout value is rounded to the next power of two clock cycles.
16 * timeout = 2^(delay + 1) clock cycles
18 * Where 'delay' is the value written in PDC_WDT_CONFIG register.
21 * as a power of two number of watchdog clock cycles. The current implementation
25 * The following table shows how the user-configured timeout relates
29 * -----------------------------------
40 #include <linux/clk.h>
84 struct clk *wdt_clk;
[all …]
/kernel/linux/linux-6.6/drivers/clk/imx/
Dclk-lpcg-scu.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
9 #include <linux/delay.h>
16 #include "clk-scu.h"
25 * struct clk_lpcg_scu - Description of LPCG clock
46 /* e10858 -LPCG clock gating register synchronization errata */
54 * through the interconnect is longer than the minimum delay in lpcg_e10858_writel()
55 * of 4 clock cycles required by the errata. in lpcg_e10858_writel()
56 * Adding a readl will provide sufficient delay to prevent in lpcg_e10858_writel()
57 * back-to-back writes. in lpcg_e10858_writel()
[all …]
/kernel/linux/linux-6.6/drivers/pwm/
Dpwm-atmel.c1 // SPDX-License-Identifier: GPL-2.0-only
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
22 #include <linux/clk.h>
23 #include <linux/delay.h>
81 struct clk *clk; member
88 * pending we delay disabling the PWM until the new configuration is
[all …]
/kernel/linux/linux-5.10/drivers/cpufreq/
Dtegra194-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
19 #include <soc/tegra/bpmp-abi.h>
47 u32 delay; member
67 * Read per-core Read-only system register NVFREQ_FEEDBACK_EL1.
87 return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv); in map_ndiv_to_freq()
97 * ref_clk_counter(32 bit counter) runs on constant clk, in tegra_read_counters()
99 * It will take = 2 ^ 32 / 408 MHz to overflow ref clk counter in tegra_read_counters()
105 * It will take = 2 ^ 32 / 2000 MHz to overflow core clk counter in tegra_read_counters()
[all …]
/kernel/linux/linux-6.6/drivers/char/hw_random/
Dks-sa-rng.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com
16 #include <linux/clk.h>
23 #include <linux/delay.h>
64 /* Number of CLK input cycles between samples */
70 /* Delay between retries (in usecs) */
86 struct clk *clk; member
93 static unsigned int cycles_to_ns(unsigned long clk_rate, unsigned int cycles) in cycles_to_ns() argument
96 cycles, clk_rate); in cycles_to_ns()
116 struct device *dev = (struct device *)rng->priv; in ks_sa_rng_init()
[all …]
/kernel/linux/linux-5.10/drivers/char/hw_random/
Dks-sa-rng.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com
16 #include <linux/clk.h>
23 #include <linux/delay.h>
64 /* Number of CLK input cycles between samples */
70 /* Delay between retries (in usecs) */
86 struct clk *clk; member
93 static unsigned int cycles_to_ns(unsigned long clk_rate, unsigned int cycles) in cycles_to_ns() argument
96 cycles, clk_rate); in cycles_to_ns()
116 struct device *dev = (struct device *)rng->priv; in ks_sa_rng_init()
[all …]
/kernel/linux/linux-5.10/drivers/pwm/
Dpwm-atmel.c1 // SPDX-License-Identifier: GPL-2.0-only
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
22 #include <linux/clk.h>
23 #include <linux/delay.h>
83 struct clk *clk; member
100 return readl_relaxed(chip->base + offset); in atmel_pwm_readl()
[all …]
/kernel/linux/linux-6.6/drivers/clk/mmp/
Dclk-gate.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
13 #include <linux/delay.h>
15 #include "clk.h"
31 if (gate->lock) in mmp_clk_gate_enable()
32 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
34 tmp = readl(gate->reg); in mmp_clk_gate_enable()
35 tmp &= ~gate->mask; in mmp_clk_gate_enable()
36 tmp |= gate->val_enable; in mmp_clk_gate_enable()
37 writel(tmp, gate->reg); in mmp_clk_gate_enable()
[all …]
/kernel/linux/linux-5.10/drivers/clk/mmp/
Dclk-gate.c12 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
18 #include "clk.h"
34 if (gate->lock) in mmp_clk_gate_enable()
35 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
37 tmp = readl(gate->reg); in mmp_clk_gate_enable()
38 tmp &= ~gate->mask; in mmp_clk_gate_enable()
39 tmp |= gate->val_enable; in mmp_clk_gate_enable()
40 writel(tmp, gate->reg); in mmp_clk_gate_enable()
42 if (gate->lock) in mmp_clk_gate_enable()
[all …]
/kernel/linux/linux-5.10/drivers/iio/adc/
Dcc10001_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 Imagination Technologies Ltd.
6 #include <linux/clk.h>
7 #include <linux/delay.h>
48 * As per device specification, wait six clock cycles after power-up to
49 * activate START. Since adding two more clock cycles delay does not
50 * impact the performance too much, we are adding two additional cycles delay
57 struct clk *adc_clk;
70 writel(val, adc_dev->reg_base + reg); in cc10001_adc_write_reg()
76 return readl(adc_dev->reg_base + reg); in cc10001_adc_read_reg()
[all …]
/kernel/linux/linux-6.6/drivers/iio/adc/
Dcc10001_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 Imagination Technologies Ltd.
6 #include <linux/clk.h>
7 #include <linux/delay.h>
47 * As per device specification, wait six clock cycles after power-up to
48 * activate START. Since adding two more clock cycles delay does not
49 * impact the performance too much, we are adding two additional cycles delay
56 struct clk *adc_clk;
69 writel(val, adc_dev->reg_base + reg); in cc10001_adc_write_reg()
75 return readl(adc_dev->reg_base + reg); in cc10001_adc_read_reg()
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/
Dmmp2-olpc-xo-1-75.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/linux-event-codes.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/clock/marvell,mmp2-audio.h>
16 model = "OLPC XO-1.75";
17 compatible = "olpc,xo-1.75", "mrvl,mmp2";
20 #address-cells = <1>;
21 #size-cells = <1>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dmmp2-olpc-xo-1-75.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/linux-event-codes.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
15 model = "OLPC XO-1.75";
16 compatible = "olpc,xo-1.75", "mrvl,mmp2";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 compatible = "simple-framebuffer";
[all …]
/kernel/linux/linux-6.6/drivers/clocksource/
Dtimer-fttmr010.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
7 * Copyright (C) 2001-2006 Storlink, Corp.
8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
18 #include <linux/clk.h>
21 #include <linux/delay.h>
81 * - aspeed timer overflow interrupt is controlled by bits in Control
83 * - aspeed timers always generate interrupt when either one of the
112 * A local singleton used by sched_clock and delay timer reads, which are
124 return readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_up()
[all …]
Dtimer-microchip-pit64b.c1 // SPDX-License-Identifier: GPL-2.0
3 * 64-bit Periodic Interval Timer driver
10 #include <linux/clk.h>
12 #include <linux/delay.h>
51 * struct mchp_pit64b_timer - PIT64B timer data structure
59 struct clk *pclk;
60 struct clk *gclk;
65 * struct mchp_pit64b_clkevt - PIT64B clockevent data structure
79 * struct mchp_pit64b_clksrc - PIT64B clocksource data structure
94 /* Default cycles for clockevent timer. */
[all …]
/kernel/linux/linux-5.10/drivers/clocksource/
Dtimer-fttmr010.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
7 * Copyright (C) 2001-2006 Storlink, Corp.
8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
18 #include <linux/clk.h>
21 #include <linux/delay.h>
81 * - aspeed timer overflow interrupt is controlled by bits in Control
83 * - aspeed timers always generate interrupt when either one of the
112 * A local singleton used by sched_clock and delay timer reads, which are
124 return readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_up()
[all …]

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