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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30 tx-internal-delay-ps:
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/kernel/linux/linux-5.10/drivers/crypto/allwinner/sun4i-ss/
Dsun4i-ss.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * sun4i-ss.h - hardware cryptographic accelerator for Allwinner A20 SoC
5 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
14 #include <linux/clk.h>
65 /* PRNG generator mode - bit 15 */
72 /* SS operation mode - bits 12-13 */
77 /* Counter width for CNT mode - bits 10-11 */
78 #define SS_CNT_16BITS (0 << 10)
79 #define SS_CNT_32BITS (1 << 10)
80 #define SS_CNT_64BITS (2 << 10)
[all …]
/kernel/linux/linux-6.6/drivers/crypto/allwinner/sun4i-ss/
Dsun4i-ss.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * sun4i-ss.h - hardware cryptographic accelerator for Allwinner A20 SoC
5 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
14 #include <linux/clk.h>
65 /* PRNG generator mode - bit 15 */
72 /* SS operation mode - bits 12-13 */
77 /* Counter width for CNT mode - bits 10-11 */
78 #define SS_CNT_16BITS (0 << 10)
79 #define SS_CNT_32BITS (1 << 10)
80 #define SS_CNT_64BITS (2 << 10)
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dste-u300.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree for the ST-Ericsson U300 Machine and SoC
6 /dts-v1/;
9 model = "ST-Ericsson U300";
11 #address-cells = <1>;
12 #size-cells = <1>;
30 vana15-supply = <&ab3100_ldo_d_reg>;
35 compatible = "stericsson,u300-syscon", "syscon";
38 #clock-cells = <0>;
39 compatible = "fixed-clock";
[all …]
Dlpc3250-phy3250.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PHYTEC phyCORE-LPC3250 board
5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
9 /dts-v1/;
13 model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
22 compatible = "gpio-leds";
26 default-state = "off";
31 linux,default-trigger = "heartbeat";
37 power-supply = <&reg_lcd>;
41 remote-endpoint = <&cldc_output>;
[all …]
Dqcom-msm8974-sony-xperia-honami.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-msm8974.dtsi"
3 #include "qcom-pm8841.dtsi"
4 #include "qcom-pm8941.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
11 compatible = "sony,xperia-honami", "qcom,msm8974";
18 stdout-path = "serial0:115200n8";
21 gpio-keys {
[all …]
Darmada-385-clearfog-gtr.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
19 1. USB 2.0 - 1 mini PCIe CON2
20 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/
Dmt7986a-bananapi-bpi-r3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Frank Wunderlich <frank-w@public-files.de>
9 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
18 model = "Bananapi BPI-R3";
19 chassis-type = "embedded";
20 compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
[all …]
/kernel/linux/linux-5.10/drivers/spi/
Dspi-sifive.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
34 #define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
36 #define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
93 struct clk *clk; /* bus clock */ member
96 struct completion done; /* wake-up from interrupt */
101 iowrite32(value, spi->regs + offset); in sifive_spi_write()
106 return ioread32(spi->regs + offset); in sifive_spi_read()
126 /* Exit specialized memory-mapped SPI flash mode */ in sifive_spi_init()
134 struct spi_device *device = msg->spi; in sifive_spi_prepare_message()
[all …]
Dspi-omap-uwire.c38 #include <linux/clk.h>
48 #include <asm/mach-types.h>
93 struct clk *ck;
155 return -1; in wait_uwire_csr_flag()
176 struct uwire_state *ust = spi->controller_state; in uwire_chipselect()
184 old_cs = (w >> 10) & 0x03; in uwire_chipselect()
185 if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) { in uwire_chipselect()
192 uwire_set_clk1_div(ust->div1_idx); in uwire_chipselect()
194 if (spi->mode & SPI_CPOL) in uwire_chipselect()
199 w = spi->chip_select << 10; in uwire_chipselect()
[all …]
Dspi-imx.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 #include <linux/clk.h>
9 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/dma-imx.h>
91 struct clk *clk_per;
92 struct clk *clk_ipg;
100 void (*tx)(struct spi_imx_data *); member
104 unsigned int txfifo; /* number of words pushed in tx FIFO */
123 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/lpc/
Dlpc3250-phy3250.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PHYTEC phyCORE-LPC3250 board
5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
9 /dts-v1/;
13 model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
22 compatible = "gpio-leds";
26 default-state = "off";
31 linux,default-trigger = "heartbeat";
37 power-supply = <&reg_lcd>;
41 remote-endpoint = <&cldc_output>;
[all …]
/kernel/linux/linux-6.6/drivers/spi/
Dspi-sifive.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
34 #define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
36 #define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
93 struct clk *clk; /* bus clock */ member
96 struct completion done; /* wake-up from interrupt */
101 iowrite32(value, spi->regs + offset); in sifive_spi_write()
106 return ioread32(spi->regs + offset); in sifive_spi_read()
126 /* Exit specialized memory-mapped SPI flash mode */ in sifive_spi_init()
134 struct spi_device *device = msg->spi; in sifive_spi_prepare_message()
[all …]
Dspi-omap-uwire.c38 #include <linux/clk.h>
47 #include <asm/mach-types.h>
48 #include <linux/soc/ti/omap1-io.h>
49 #include <linux/soc/ti/omap1-soc.h>
50 #include <linux/soc/ti/omap1-mux.h>
90 struct clk *ck;
152 return -1; in wait_uwire_csr_flag()
173 struct uwire_state *ust = spi->controller_state; in uwire_chipselect()
181 old_cs = (w >> 10) & 0x03; in uwire_chipselect()
189 uwire_set_clk1_div(ust->div1_idx); in uwire_chipselect()
[all …]
Dspi-imx.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
26 #include <linux/dma/imx-dma.h>
100 struct clk *clk_per;
101 struct clk *clk_ipg;
109 void (*tx)(struct spi_imx_data *spi_imx); member
113 unsigned int txfifo; /* number of words pushed in tx FIFO */
133 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
[all …]
/kernel/linux/linux-6.6/drivers/net/phy/
Dmotorcomm.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: Frank <Frank.Sae@motor-comm.com>
22 * ------------------------------------------------------------
26 * ------------------------------------------------------------
28 * ------------------------------------------------------------
59 #define YTPHY_SSR_LINK BIT(10)
78 #define YTPHY_ISR_LINK_SUCCESSED BIT(10)
104 /* FIBER Auto-Negotiation link partner ability */
122 /* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */
125 /* TX Gig-E Delay is bits 7:4, default 0x5
[all …]
/kernel/linux/linux-6.6/drivers/tty/serial/
Dimx.c1 // SPDX-License-Identifier: GPL-2.0+
21 #include <linux/clk.h>
30 #include <linux/dma-mapping.h>
33 #include <linux/dma/imx-dma.h>
63 #define URXD_PRERR (1<<10)
69 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
98 #define UCR3_DSR (1<<10) /* Data set ready */
107 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
109 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
111 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
[all …]
Damba-pl011.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2010 ST-Ericsson SA
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
32 #include <linux/clk.h>
35 #include <linux/dma-mapping.h>
82 /* The size of the array - must be last */
257 struct clk *clk; member
262 unsigned int fifosize; /* vendor-specific */
263 unsigned int fixed_baud; /* vendor-set fixed baud rate */
[all …]
/kernel/linux/linux-5.10/drivers/tty/serial/
Dimx.c1 // SPDX-License-Identifier: GPL-2.0+
21 #include <linux/clk.h>
30 #include <linux/dma-mapping.h>
33 #include <linux/platform_data/serial-imx.h>
34 #include <linux/platform_data/dma-imx.h>
64 #define URXD_PRERR (1<<10)
70 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
99 #define UCR3_DSR (1<<10) /* Data set ready */
108 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
110 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/input/
Diqs626a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS626A is a 14-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
19 - $ref: touchscreen/touchscreen.yaml#
31 "#address-cells":
34 "#size-cells":
37 azoteq,suspend-mode:
[all …]
/kernel/linux/linux-5.10/sound/soc/ti/
Ddavinci-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * based on davinci-mcasp.c DT support
21 #include <linux/clk.h>
31 #include "edma-pcm.h"
32 #include "davinci-i2s.h"
34 #define DRV_NAME "davinci-i2s"
39 * - This driver supports the "Audio Serial Port" (ASP),
42 * - But it labels it a "Multi-channel Buffered Serial Port"
44 * backward-compatible, possibly explaining that confusion.
46 * - OMAP chips have a controller called McBSP, which is
[all …]
/kernel/linux/linux-6.6/sound/soc/ti/
Ddavinci-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * based on davinci-mcasp.c DT support
21 #include <linux/clk.h>
31 #include "edma-pcm.h"
32 #include "davinci-i2s.h"
34 #define DRV_NAME "davinci-i2s"
39 * - This driver supports the "Audio Serial Port" (ASP),
42 * - But it labels it a "Multi-channel Buffered Serial Port"
44 * backward-compatible, possibly explaining that confusion.
46 * - OMAP chips have a controller called McBSP, which is
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/
Darmada-385-clearfog-gtr.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
19 1. USB 2.0 - 1 mini PCIe CON2
20 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
[all …]
/kernel/linux/linux-6.6/sound/soc/fsl/
Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
32 #include <linux/clk.h>
43 #include <linux/dma/imx-dma.h>
53 #include "imx-pcm.h"
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
57 #define TX 1 macro
66 * (bit-endianness must match byte-endianness). Processors typically write
[all …]
/kernel/linux/linux-5.10/sound/soc/fsl/
Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
32 #include <linux/clk.h>
52 #include "imx-pcm.h"
54 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
56 #define TX 1 macro
65 * (bit-endianness must match byte-endianness). Processors typically write
67 * written in. So if the host CPU is big-endian, then only big-endian
[all …]

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