Lines Matching refs:X_MASK
1325 #define X_MASK XRC (0x3f, 0x3ff, 1) macro
1328 #define XRA_MASK (X_MASK | RA_MASK)
1331 #define XRB_MASK (X_MASK | RB_MASK)
1334 #define XRT_MASK (X_MASK | RT_MASK)
1337 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1340 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1346 #define XCMP_MASK (X_MASK | (1 << 22))
1354 #define XTO_MASK (X_MASK | TO_MASK)
1409 #define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11))
1418 #define XSPR_MASK (X_MASK | SPR_MASK)
2246 { "tw", X(31,4), X_MASK, PPC, { TO, RA, RB } },
2247 { "t", X(31,4), X_MASK, POWER, { TO, RA, RB } },
2279 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
2281 { "ldx", X(31,21), X_MASK, PPC|B64, { RT, RA, RB } },
2283 { "lwzx", X(31,23), X_MASK, PPC, { RT, RA, RB } },
2284 { "lx", X(31,23), X_MASK, POWER, { RT, RA, RB } },
2286 { "slw", XRC(31,24,0), X_MASK, PPC, { RA, RS, RB } },
2287 { "sl", XRC(31,24,0), X_MASK, POWER, { RA, RS, RB } },
2288 { "slw.", XRC(31,24,1), X_MASK, PPC, { RA, RS, RB } },
2289 { "sl.", XRC(31,24,1), X_MASK, POWER, { RA, RS, RB } },
2296 { "sld", XRC(31,27,0), X_MASK, PPC|B64, { RA, RS, RB } },
2297 { "sld.", XRC(31,27,1), X_MASK, PPC|B64, { RA, RS, RB } },
2299 { "and", XRC(31,28,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2300 { "and.", XRC(31,28,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2302 { "maskg", XRC(31,29,0), X_MASK, POWER|M601, { RA, RS, RB } },
2303 { "maskg.", XRC(31,29,1), X_MASK, POWER|M601, { RA, RS, RB } },
2319 { "ldux", X(31,53), X_MASK, PPC|B64, { RT, RAL, RB } },
2323 { "lwzux", X(31,55), X_MASK, PPC, { RT, RAL, RB } },
2324 { "lux", X(31,55), X_MASK, POWER, { RT, RA, RB } },
2329 { "andc", XRC(31,60,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2330 { "andc.", XRC(31,60,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2346 { "td", X(31,68), X_MASK, PPC|B64, { TO, RA, RB } },
2356 { "ldarx", X(31,84), X_MASK, PPC|B64, { RT, RA, RB } },
2360 { "lbzx", X(31,87), X_MASK, PPC|POWER, { RT, RA, RB } },
2374 { "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RAL, RB } },
2376 { "not", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
2377 { "nor", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2378 { "not.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
2379 { "nor.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2404 { "stdx", X(31,149), X_MASK, PPC|B64, { RS, RA, RB } },
2406 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
2408 { "stwx", X(31,151), X_MASK, PPC, { RS, RA, RB } },
2409 { "stx", X(31,151), X_MASK, POWER, { RS, RA, RB } },
2411 { "slq", XRC(31,152,0), X_MASK, POWER|M601, { RA, RS, RB } },
2412 { "slq.", XRC(31,152,1), X_MASK, POWER|M601, { RA, RS, RB } },
2414 { "sle", XRC(31,153,0), X_MASK, POWER|M601, { RA, RS, RB } },
2415 { "sle.", XRC(31,153,1), X_MASK, POWER|M601, { RA, RS, RB } },
2417 { "stdux", X(31,181), X_MASK, PPC|B64, { RS, RAS, RB } },
2419 { "stwux", X(31,183), X_MASK, PPC, { RS, RAS, RB } },
2420 { "stux", X(31,183), X_MASK, POWER, { RS, RA, RB } },
2422 { "sliq", XRC(31,184,0), X_MASK, POWER|M601, { RA, RS, SH } },
2423 { "sliq.", XRC(31,184,1), X_MASK, POWER|M601, { RA, RS, SH } },
2445 { "stdcx.", XRC(31,214,1), X_MASK, PPC|B64, { RS, RA, RB } },
2447 { "stbx", X(31,215), X_MASK, PPC|POWER, { RS, RA, RB } },
2449 { "sllq", XRC(31,216,0), X_MASK, POWER|M601, { RA, RS, RB } },
2450 { "sllq.", XRC(31,216,1), X_MASK, POWER|M601, { RA, RS, RB } },
2452 { "sleq", XRC(31,217,0), X_MASK, POWER|M601, { RA, RS, RB } },
2453 { "sleq.", XRC(31,217,1), X_MASK, POWER|M601, { RA, RS, RB } },
2492 { "stbux", X(31,247), X_MASK, PPC|POWER, { RS, RAS, RB } },
2494 { "slliq", XRC(31,248,0), X_MASK, POWER|M601, { RA, RS, SH } },
2495 { "slliq.", XRC(31,248,1), X_MASK, POWER|M601, { RA, RS, SH } },
2511 { "lscbx", XRC(31,277,0), X_MASK, POWER|M601, { RT, RA, RB } },
2512 { "lscbx.", XRC(31,277,1), X_MASK, POWER|M601, { RT, RA, RB } },
2516 { "lhzx", X(31,279), X_MASK, PPC|POWER, { RT, RA, RB } },
2520 { "eqv", XRC(31,284,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2521 { "eqv.", XRC(31,284,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2526 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
2528 { "lhzux", X(31,311), X_MASK, PPC|POWER, { RT, RAL, RB } },
2530 { "xor", XRC(31,316,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2531 { "xor.", XRC(31,316,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2533 { "mfdcr", X(31,323), X_MASK, PPC, { RT, SPR } },
2563 { "mfspr", X(31,339), X_MASK, PPC|POWER, { RT, SPR } },
2565 { "lwax", X(31,341), X_MASK, PPC|B64, { RT, RA, RB } },
2567 { "lhax", X(31,343), X_MASK, PPC|POWER, { RT, RA, RB } },
2584 { "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
2586 { "lwaux", X(31,373), X_MASK, PPC|B64, { RT, RAL, RB } },
2588 { "lhaux", X(31,375), X_MASK, PPC|POWER, { RT, RAL, RB } },
2590 { "sthx", X(31,407), X_MASK, PPC|POWER, { RS, RA, RB } },
2592 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
2594 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
2596 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
2598 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
2600 { "orc", XRC(31,412,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2601 { "orc.", XRC(31,412,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2608 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
2610 { "sthux", X(31,439), X_MASK, PPC|POWER, { RS, RAS, RB } },
2612 { "mr", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
2613 { "or", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2614 { "mr.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
2615 { "or.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2617 { "mtdcr", X(31,451), X_MASK, PPC, { SPR, RS } },
2652 { "mtspr", X(31,467), X_MASK, PPC|POWER, { SPR, RS } },
2656 { "nand", XRC(31,476,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2657 { "nand.", XRC(31,476,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2682 { "lswx", X(31,533), X_MASK, PPC, { RT, RA, RB } },
2683 { "lsx", X(31,533), X_MASK, POWER, { RT, RA, RB } },
2685 { "lwbrx", X(31,534), X_MASK, PPC, { RT, RA, RB } },
2686 { "lbrx", X(31,534), X_MASK, POWER, { RT, RA, RB } },
2688 { "lfsx", X(31,535), X_MASK, PPC|POWER, { FRT, RA, RB } },
2690 { "srw", XRC(31,536,0), X_MASK, PPC, { RA, RS, RB } },
2691 { "sr", XRC(31,536,0), X_MASK, POWER, { RA, RS, RB } },
2692 { "srw.", XRC(31,536,1), X_MASK, PPC, { RA, RS, RB } },
2693 { "sr.", XRC(31,536,1), X_MASK, POWER, { RA, RS, RB } },
2695 { "rrib", XRC(31,537,0), X_MASK, POWER|M601, { RA, RS, RB } },
2696 { "rrib.", XRC(31,537,1), X_MASK, POWER|M601, { RA, RS, RB } },
2698 { "srd", XRC(31,539,0), X_MASK, PPC|B64, { RA, RS, RB } },
2699 { "srd.", XRC(31,539,1), X_MASK, PPC|B64, { RA, RS, RB } },
2701 { "maskir", XRC(31,541,0), X_MASK, POWER|M601, { RA, RS, RB } },
2702 { "maskir.", XRC(31,541,1), X_MASK, POWER|M601, { RA, RS, RB } },
2706 { "lfsux", X(31,567), X_MASK, PPC|POWER, { FRT, RAS, RB } },
2710 { "lswi", X(31,597), X_MASK, PPC, { RT, RA, NB } },
2711 { "lsi", X(31,597), X_MASK, POWER, { RT, RA, NB } },
2716 { "lfdx", X(31,599), X_MASK, PPC|POWER, { FRT, RA, RB } },
2718 { "mfsri", X(31,627), X_MASK, POWER, { RT, RA, RB } },
2722 { "lfdux", X(31,631), X_MASK, PPC|POWER, { FRT, RAS, RB } },
2726 { "stswx", X(31,661), X_MASK, PPC, { RS, RA, RB } },
2727 { "stsx", X(31,661), X_MASK, POWER, { RS, RA, RB } },
2729 { "stwbrx", X(31,662), X_MASK, PPC, { RS, RA, RB } },
2730 { "stbrx", X(31,662), X_MASK, POWER, { RS, RA, RB } },
2732 { "stfsx", X(31,663), X_MASK, PPC|POWER, { FRS, RA, RB } },
2734 { "srq", XRC(31,664,0), X_MASK, POWER|M601, { RA, RS, RB } },
2735 { "srq.", XRC(31,664,1), X_MASK, POWER|M601, { RA, RS, RB } },
2737 { "sre", XRC(31,665,0), X_MASK, POWER|M601, { RA, RS, RB } },
2738 { "sre.", XRC(31,665,1), X_MASK, POWER|M601, { RA, RS, RB } },
2740 { "stfsux", X(31,695), X_MASK, PPC|POWER, { FRS, RAS, RB } },
2742 { "sriq", XRC(31,696,0), X_MASK, POWER|M601, { RA, RS, SH } },
2743 { "sriq.", XRC(31,696,1), X_MASK, POWER|M601, { RA, RS, SH } },
2745 { "stswi", X(31,725), X_MASK, PPC, { RS, RA, NB } },
2746 { "stsi", X(31,725), X_MASK, POWER, { RS, RA, NB } },
2748 { "stfdx", X(31,727), X_MASK, PPC|POWER, { FRS, RA, RB } },
2750 { "srlq", XRC(31,728,0), X_MASK, POWER|M601, { RA, RS, RB } },
2751 { "srlq.", XRC(31,728,1), X_MASK, POWER|M601, { RA, RS, RB } },
2753 { "sreq", XRC(31,729,0), X_MASK, POWER|M601, { RA, RS, RB } },
2754 { "sreq.", XRC(31,729,1), X_MASK, POWER|M601, { RA, RS, RB } },
2756 { "stfdux", X(31,759), X_MASK, PPC|POWER, { FRS, RAS, RB } },
2758 { "srliq", XRC(31,760,0), X_MASK, POWER|M601, { RA, RS, SH } },
2759 { "srliq.", XRC(31,760,1), X_MASK, POWER|M601, { RA, RS, SH } },
2761 { "lhbrx", X(31,790), X_MASK, PPC|POWER, { RT, RA, RB } },
2763 { "sraw", XRC(31,792,0), X_MASK, PPC, { RA, RS, RB } },
2764 { "sra", XRC(31,792,0), X_MASK, POWER, { RA, RS, RB } },
2765 { "sraw.", XRC(31,792,1), X_MASK, PPC, { RA, RS, RB } },
2766 { "sra.", XRC(31,792,1), X_MASK, POWER, { RA, RS, RB } },
2768 { "srad", XRC(31,794,0), X_MASK, PPC|B64, { RA, RS, RB } },
2769 { "srad.", XRC(31,794,1), X_MASK, PPC|B64, { RA, RS, RB } },
2771 { "rac", X(31,818), X_MASK, POWER, { RT, RA, RB } },
2773 { "srawi", XRC(31,824,0), X_MASK, PPC, { RA, RS, SH } },
2774 { "srai", XRC(31,824,0), X_MASK, POWER, { RA, RS, SH } },
2775 { "srawi.", XRC(31,824,1), X_MASK, PPC, { RA, RS, SH } },
2776 { "srai.", XRC(31,824,1), X_MASK, POWER, { RA, RS, SH } },
2780 { "sthbrx", X(31,918), X_MASK, PPC|POWER, { RS, RA, RB } },
2782 { "sraq", XRC(31,920,0), X_MASK, POWER|M601, { RA, RS, RB } },
2783 { "sraq.", XRC(31,920,1), X_MASK, POWER|M601, { RA, RS, RB } },
2785 { "srea", XRC(31,921,0), X_MASK, POWER|M601, { RA, RS, RB } },
2786 { "srea.", XRC(31,921,1), X_MASK, POWER|M601, { RA, RS, RB } },
2793 { "sraiq", XRC(31,952,0), X_MASK, POWER|M601, { RA, RS, SH } },
2794 { "sraiq.", XRC(31,952,1), X_MASK, POWER|M601, { RA, RS, SH } },
2803 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
2913 { "fcmpu", X(63,0), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
2977 { "fcmpo", X(63,30), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },