1 /*
2 * defines common to all virtual CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #ifndef CPU_ALL_H
21 #define CPU_ALL_H
22
23 #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__)
24 #define WORDS_ALIGNED
25 #endif
26
27 /* some important defines:
28 *
29 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
30 * memory accesses.
31 *
32 * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
33 * otherwise little endian.
34 *
35 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
36 *
37 * TARGET_WORDS_BIGENDIAN : same for target cpu
38 */
39
40 #include "bswap.h"
41 #include "softfloat.h"
42
43 #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
44 #define BSWAP_NEEDED
45 #endif
46
47 #ifdef BSWAP_NEEDED
48
tswap16(uint16_t s)49 static inline uint16_t tswap16(uint16_t s)
50 {
51 return bswap16(s);
52 }
53
tswap32(uint32_t s)54 static inline uint32_t tswap32(uint32_t s)
55 {
56 return bswap32(s);
57 }
58
tswap64(uint64_t s)59 static inline uint64_t tswap64(uint64_t s)
60 {
61 return bswap64(s);
62 }
63
tswap16s(uint16_t * s)64 static inline void tswap16s(uint16_t *s)
65 {
66 *s = bswap16(*s);
67 }
68
tswap32s(uint32_t * s)69 static inline void tswap32s(uint32_t *s)
70 {
71 *s = bswap32(*s);
72 }
73
tswap64s(uint64_t * s)74 static inline void tswap64s(uint64_t *s)
75 {
76 *s = bswap64(*s);
77 }
78
79 #else
80
tswap16(uint16_t s)81 static inline uint16_t tswap16(uint16_t s)
82 {
83 return s;
84 }
85
tswap32(uint32_t s)86 static inline uint32_t tswap32(uint32_t s)
87 {
88 return s;
89 }
90
tswap64(uint64_t s)91 static inline uint64_t tswap64(uint64_t s)
92 {
93 return s;
94 }
95
tswap16s(uint16_t * s)96 static inline void tswap16s(uint16_t *s)
97 {
98 }
99
tswap32s(uint32_t * s)100 static inline void tswap32s(uint32_t *s)
101 {
102 }
103
tswap64s(uint64_t * s)104 static inline void tswap64s(uint64_t *s)
105 {
106 }
107
108 #endif
109
110 #if TARGET_LONG_SIZE == 4
111 #define tswapl(s) tswap32(s)
112 #define tswapls(s) tswap32s((uint32_t *)(s))
113 #define bswaptls(s) bswap32s(s)
114 #else
115 #define tswapl(s) tswap64(s)
116 #define tswapls(s) tswap64s((uint64_t *)(s))
117 #define bswaptls(s) bswap64s(s)
118 #endif
119
120 typedef union {
121 float32 f;
122 uint32_t l;
123 } CPU_FloatU;
124
125 /* NOTE: arm FPA is horrible as double 32 bit words are stored in big
126 endian ! */
127 typedef union {
128 float64 d;
129 #if defined(WORDS_BIGENDIAN) \
130 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
131 struct {
132 uint32_t upper;
133 uint32_t lower;
134 } l;
135 #else
136 struct {
137 uint32_t lower;
138 uint32_t upper;
139 } l;
140 #endif
141 uint64_t ll;
142 } CPU_DoubleU;
143
144 #ifdef TARGET_SPARC
145 typedef union {
146 float128 q;
147 #if defined(WORDS_BIGENDIAN) \
148 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
149 struct {
150 uint32_t upmost;
151 uint32_t upper;
152 uint32_t lower;
153 uint32_t lowest;
154 } l;
155 struct {
156 uint64_t upper;
157 uint64_t lower;
158 } ll;
159 #else
160 struct {
161 uint32_t lowest;
162 uint32_t lower;
163 uint32_t upper;
164 uint32_t upmost;
165 } l;
166 struct {
167 uint64_t lower;
168 uint64_t upper;
169 } ll;
170 #endif
171 } CPU_QuadU;
172 #endif
173
174 /* CPU memory access without any memory or io remapping */
175
176 /*
177 * the generic syntax for the memory accesses is:
178 *
179 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
180 *
181 * store: st{type}{size}{endian}_{access_type}(ptr, val)
182 *
183 * type is:
184 * (empty): integer access
185 * f : float access
186 *
187 * sign is:
188 * (empty): for floats or 32 bit size
189 * u : unsigned
190 * s : signed
191 *
192 * size is:
193 * b: 8 bits
194 * w: 16 bits
195 * l: 32 bits
196 * q: 64 bits
197 *
198 * endian is:
199 * (empty): target cpu endianness or 8 bit access
200 * r : reversed target cpu endianness (not implemented yet)
201 * be : big endian (not implemented yet)
202 * le : little endian (not implemented yet)
203 *
204 * access_type is:
205 * raw : host memory access
206 * user : user mode access using soft MMU
207 * kernel : kernel mode access using soft MMU
208 */
ldub_p(void * ptr)209 static inline int ldub_p(void *ptr)
210 {
211 return *(uint8_t *)ptr;
212 }
213
ldsb_p(void * ptr)214 static inline int ldsb_p(void *ptr)
215 {
216 return *(int8_t *)ptr;
217 }
218
stb_p(void * ptr,int v)219 static inline void stb_p(void *ptr, int v)
220 {
221 *(uint8_t *)ptr = v;
222 }
223
224 /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
225 kernel handles unaligned load/stores may give better results, but
226 it is a system wide setting : bad */
227 #if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
228
229 /* conservative code for little endian unaligned accesses */
lduw_le_p(void * ptr)230 static inline int lduw_le_p(void *ptr)
231 {
232 #ifdef __powerpc__
233 int val;
234 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
235 return val;
236 #else
237 uint8_t *p = ptr;
238 return p[0] | (p[1] << 8);
239 #endif
240 }
241
ldsw_le_p(void * ptr)242 static inline int ldsw_le_p(void *ptr)
243 {
244 #ifdef __powerpc__
245 int val;
246 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
247 return (int16_t)val;
248 #else
249 uint8_t *p = ptr;
250 return (int16_t)(p[0] | (p[1] << 8));
251 #endif
252 }
253
ldl_le_p(void * ptr)254 static inline int ldl_le_p(void *ptr)
255 {
256 #ifdef __powerpc__
257 int val;
258 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
259 return val;
260 #else
261 uint8_t *p = ptr;
262 return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
263 #endif
264 }
265
ldq_le_p(void * ptr)266 static inline uint64_t ldq_le_p(void *ptr)
267 {
268 uint8_t *p = ptr;
269 uint32_t v1, v2;
270 v1 = ldl_le_p(p);
271 v2 = ldl_le_p(p + 4);
272 return v1 | ((uint64_t)v2 << 32);
273 }
274
stw_le_p(void * ptr,int v)275 static inline void stw_le_p(void *ptr, int v)
276 {
277 #ifdef __powerpc__
278 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
279 #else
280 uint8_t *p = ptr;
281 p[0] = v;
282 p[1] = v >> 8;
283 #endif
284 }
285
stl_le_p(void * ptr,int v)286 static inline void stl_le_p(void *ptr, int v)
287 {
288 #ifdef __powerpc__
289 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
290 #else
291 uint8_t *p = ptr;
292 p[0] = v;
293 p[1] = v >> 8;
294 p[2] = v >> 16;
295 p[3] = v >> 24;
296 #endif
297 }
298
stq_le_p(void * ptr,uint64_t v)299 static inline void stq_le_p(void *ptr, uint64_t v)
300 {
301 uint8_t *p = ptr;
302 stl_le_p(p, (uint32_t)v);
303 stl_le_p(p + 4, v >> 32);
304 }
305
306 /* float access */
307
ldfl_le_p(void * ptr)308 static inline float32 ldfl_le_p(void *ptr)
309 {
310 union {
311 float32 f;
312 uint32_t i;
313 } u;
314 u.i = ldl_le_p(ptr);
315 return u.f;
316 }
317
stfl_le_p(void * ptr,float32 v)318 static inline void stfl_le_p(void *ptr, float32 v)
319 {
320 union {
321 float32 f;
322 uint32_t i;
323 } u;
324 u.f = v;
325 stl_le_p(ptr, u.i);
326 }
327
ldfq_le_p(void * ptr)328 static inline float64 ldfq_le_p(void *ptr)
329 {
330 CPU_DoubleU u;
331 u.l.lower = ldl_le_p(ptr);
332 u.l.upper = ldl_le_p(ptr + 4);
333 return u.d;
334 }
335
stfq_le_p(void * ptr,float64 v)336 static inline void stfq_le_p(void *ptr, float64 v)
337 {
338 CPU_DoubleU u;
339 u.d = v;
340 stl_le_p(ptr, u.l.lower);
341 stl_le_p(ptr + 4, u.l.upper);
342 }
343
344 #else
345
lduw_le_p(void * ptr)346 static inline int lduw_le_p(void *ptr)
347 {
348 return *(uint16_t *)ptr;
349 }
350
ldsw_le_p(void * ptr)351 static inline int ldsw_le_p(void *ptr)
352 {
353 return *(int16_t *)ptr;
354 }
355
ldl_le_p(void * ptr)356 static inline int ldl_le_p(void *ptr)
357 {
358 return *(uint32_t *)ptr;
359 }
360
ldq_le_p(void * ptr)361 static inline uint64_t ldq_le_p(void *ptr)
362 {
363 return *(uint64_t *)ptr;
364 }
365
stw_le_p(void * ptr,int v)366 static inline void stw_le_p(void *ptr, int v)
367 {
368 *(uint16_t *)ptr = v;
369 }
370
stl_le_p(void * ptr,int v)371 static inline void stl_le_p(void *ptr, int v)
372 {
373 *(uint32_t *)ptr = v;
374 }
375
stq_le_p(void * ptr,uint64_t v)376 static inline void stq_le_p(void *ptr, uint64_t v)
377 {
378 #if defined(__i386__) && __GNUC__ >= 4
379 const union { uint64_t v; uint32_t p[2]; } x = { .v = v };
380 ((uint32_t *)ptr)[0] = x.p[0];
381 ((uint32_t *)ptr)[1] = x.p[1];
382 #else
383 *(uint64_t *)ptr = v;
384 #endif
385 }
386
387 /* float access */
388
ldfl_le_p(void * ptr)389 static inline float32 ldfl_le_p(void *ptr)
390 {
391 return *(float32 *)ptr;
392 }
393
ldfq_le_p(void * ptr)394 static inline float64 ldfq_le_p(void *ptr)
395 {
396 return *(float64 *)ptr;
397 }
398
stfl_le_p(void * ptr,float32 v)399 static inline void stfl_le_p(void *ptr, float32 v)
400 {
401 *(float32 *)ptr = v;
402 }
403
stfq_le_p(void * ptr,float64 v)404 static inline void stfq_le_p(void *ptr, float64 v)
405 {
406 *(float64 *)ptr = v;
407 }
408 #endif
409
410 #if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
411
lduw_be_p(void * ptr)412 static inline int lduw_be_p(void *ptr)
413 {
414 #if defined(__i386__)
415 int val;
416 asm volatile ("movzwl %1, %0\n"
417 "xchgb %b0, %h0\n"
418 : "=q" (val)
419 : "m" (*(uint16_t *)ptr));
420 return val;
421 #else
422 uint8_t *b = (uint8_t *) ptr;
423 return ((b[0] << 8) | b[1]);
424 #endif
425 }
426
ldsw_be_p(void * ptr)427 static inline int ldsw_be_p(void *ptr)
428 {
429 #if defined(__i386__)
430 int val;
431 asm volatile ("movzwl %1, %0\n"
432 "xchgb %b0, %h0\n"
433 : "=q" (val)
434 : "m" (*(uint16_t *)ptr));
435 return (int16_t)val;
436 #else
437 uint8_t *b = (uint8_t *) ptr;
438 return (int16_t)((b[0] << 8) | b[1]);
439 #endif
440 }
441
ldl_be_p(void * ptr)442 static inline int ldl_be_p(void *ptr)
443 {
444 #if defined(__i386__) || defined(__x86_64__)
445 int val;
446 asm volatile ("movl %1, %0\n"
447 "bswap %0\n"
448 : "=r" (val)
449 : "m" (*(uint32_t *)ptr));
450 return val;
451 #else
452 uint8_t *b = (uint8_t *) ptr;
453 return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
454 #endif
455 }
456
ldq_be_p(void * ptr)457 static inline uint64_t ldq_be_p(void *ptr)
458 {
459 uint32_t a,b;
460 a = ldl_be_p(ptr);
461 b = ldl_be_p((uint8_t *)ptr + 4);
462 return (((uint64_t)a<<32)|b);
463 }
464
stw_be_p(void * ptr,int v)465 static inline void stw_be_p(void *ptr, int v)
466 {
467 #if defined(__i386__)
468 asm volatile ("xchgb %b0, %h0\n"
469 "movw %w0, %1\n"
470 : "=q" (v)
471 : "m" (*(uint16_t *)ptr), "0" (v));
472 #else
473 uint8_t *d = (uint8_t *) ptr;
474 d[0] = v >> 8;
475 d[1] = v;
476 #endif
477 }
478
stl_be_p(void * ptr,int v)479 static inline void stl_be_p(void *ptr, int v)
480 {
481 #if defined(__i386__) || defined(__x86_64__)
482 asm volatile ("bswap %0\n"
483 "movl %0, %1\n"
484 : "=r" (v)
485 : "m" (*(uint32_t *)ptr), "0" (v));
486 #else
487 uint8_t *d = (uint8_t *) ptr;
488 d[0] = v >> 24;
489 d[1] = v >> 16;
490 d[2] = v >> 8;
491 d[3] = v;
492 #endif
493 }
494
stq_be_p(void * ptr,uint64_t v)495 static inline void stq_be_p(void *ptr, uint64_t v)
496 {
497 stl_be_p(ptr, v >> 32);
498 stl_be_p((uint8_t *)ptr + 4, v);
499 }
500
501 /* float access */
502
ldfl_be_p(void * ptr)503 static inline float32 ldfl_be_p(void *ptr)
504 {
505 union {
506 float32 f;
507 uint32_t i;
508 } u;
509 u.i = ldl_be_p(ptr);
510 return u.f;
511 }
512
stfl_be_p(void * ptr,float32 v)513 static inline void stfl_be_p(void *ptr, float32 v)
514 {
515 union {
516 float32 f;
517 uint32_t i;
518 } u;
519 u.f = v;
520 stl_be_p(ptr, u.i);
521 }
522
ldfq_be_p(void * ptr)523 static inline float64 ldfq_be_p(void *ptr)
524 {
525 CPU_DoubleU u;
526 u.l.upper = ldl_be_p(ptr);
527 u.l.lower = ldl_be_p((uint8_t *)ptr + 4);
528 return u.d;
529 }
530
stfq_be_p(void * ptr,float64 v)531 static inline void stfq_be_p(void *ptr, float64 v)
532 {
533 CPU_DoubleU u;
534 u.d = v;
535 stl_be_p(ptr, u.l.upper);
536 stl_be_p((uint8_t *)ptr + 4, u.l.lower);
537 }
538
539 #else
540
lduw_be_p(void * ptr)541 static inline int lduw_be_p(void *ptr)
542 {
543 return *(uint16_t *)ptr;
544 }
545
ldsw_be_p(void * ptr)546 static inline int ldsw_be_p(void *ptr)
547 {
548 return *(int16_t *)ptr;
549 }
550
ldl_be_p(void * ptr)551 static inline int ldl_be_p(void *ptr)
552 {
553 return *(uint32_t *)ptr;
554 }
555
ldq_be_p(void * ptr)556 static inline uint64_t ldq_be_p(void *ptr)
557 {
558 return *(uint64_t *)ptr;
559 }
560
stw_be_p(void * ptr,int v)561 static inline void stw_be_p(void *ptr, int v)
562 {
563 *(uint16_t *)ptr = v;
564 }
565
stl_be_p(void * ptr,int v)566 static inline void stl_be_p(void *ptr, int v)
567 {
568 *(uint32_t *)ptr = v;
569 }
570
stq_be_p(void * ptr,uint64_t v)571 static inline void stq_be_p(void *ptr, uint64_t v)
572 {
573 *(uint64_t *)ptr = v;
574 }
575
576 /* float access */
577
ldfl_be_p(void * ptr)578 static inline float32 ldfl_be_p(void *ptr)
579 {
580 return *(float32 *)ptr;
581 }
582
ldfq_be_p(void * ptr)583 static inline float64 ldfq_be_p(void *ptr)
584 {
585 return *(float64 *)ptr;
586 }
587
stfl_be_p(void * ptr,float32 v)588 static inline void stfl_be_p(void *ptr, float32 v)
589 {
590 *(float32 *)ptr = v;
591 }
592
stfq_be_p(void * ptr,float64 v)593 static inline void stfq_be_p(void *ptr, float64 v)
594 {
595 *(float64 *)ptr = v;
596 }
597
598 #endif
599
600 /* target CPU memory access functions */
601 #if defined(TARGET_WORDS_BIGENDIAN)
602 #define lduw_p(p) lduw_be_p(p)
603 #define ldsw_p(p) ldsw_be_p(p)
604 #define ldl_p(p) ldl_be_p(p)
605 #define ldq_p(p) ldq_be_p(p)
606 #define ldfl_p(p) ldfl_be_p(p)
607 #define ldfq_p(p) ldfq_be_p(p)
608 #define stw_p(p, v) stw_be_p(p, v)
609 #define stl_p(p, v) stl_be_p(p, v)
610 #define stq_p(p, v) stq_be_p(p, v)
611 #define stfl_p(p, v) stfl_be_p(p, v)
612 #define stfq_p(p, v) stfq_be_p(p, v)
613 #else
614 #define lduw_p(p) lduw_le_p(p)
615 #define ldsw_p(p) ldsw_le_p(p)
616 #define ldl_p(p) ldl_le_p(p)
617 #define ldq_p(p) ldq_le_p(p)
618 #define ldfl_p(p) ldfl_le_p(p)
619 #define ldfq_p(p) ldfq_le_p(p)
620 #define stw_p(p, v) stw_le_p(p, v)
621 #define stl_p(p, v) stl_le_p(p, v)
622 #define stq_p(p, v) stq_le_p(p, v)
623 #define stfl_p(p, v) stfl_le_p(p, v)
624 #define stfq_p(p, v) stfq_le_p(p, v)
625 #endif
626
627 /* MMU memory access macros */
628
629 #if defined(CONFIG_USER_ONLY)
630 /* On some host systems the guest address space is reserved on the host.
631 * This allows the guest address space to be offset to a convenient location.
632 */
633 //#define GUEST_BASE 0x20000000
634 #define GUEST_BASE 0
635
636 /* All direct uses of g2h and h2g need to go away for usermode softmmu. */
637 #define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
638 #define h2g(x) ((target_ulong)((unsigned long)(x) - GUEST_BASE))
639
640 #define saddr(x) g2h(x)
641 #define laddr(x) g2h(x)
642
643 #else /* !CONFIG_USER_ONLY */
644 /* NOTE: we use double casts if pointers and target_ulong have
645 different sizes */
646 #define saddr(x) (uint8_t *)(long)(x)
647 #define laddr(x) (uint8_t *)(long)(x)
648 #endif
649
650 #define ldub_raw(p) ldub_p(laddr((p)))
651 #define ldsb_raw(p) ldsb_p(laddr((p)))
652 #define lduw_raw(p) lduw_p(laddr((p)))
653 #define ldsw_raw(p) ldsw_p(laddr((p)))
654 #define ldl_raw(p) ldl_p(laddr((p)))
655 #define ldq_raw(p) ldq_p(laddr((p)))
656 #define ldfl_raw(p) ldfl_p(laddr((p)))
657 #define ldfq_raw(p) ldfq_p(laddr((p)))
658 #define stb_raw(p, v) stb_p(saddr((p)), v)
659 #define stw_raw(p, v) stw_p(saddr((p)), v)
660 #define stl_raw(p, v) stl_p(saddr((p)), v)
661 #define stq_raw(p, v) stq_p(saddr((p)), v)
662 #define stfl_raw(p, v) stfl_p(saddr((p)), v)
663 #define stfq_raw(p, v) stfq_p(saddr((p)), v)
664
665
666 #if defined(CONFIG_USER_ONLY)
667
668 /* if user mode, no other memory access functions */
669 #define ldub(p) ldub_raw(p)
670 #define ldsb(p) ldsb_raw(p)
671 #define lduw(p) lduw_raw(p)
672 #define ldsw(p) ldsw_raw(p)
673 #define ldl(p) ldl_raw(p)
674 #define ldq(p) ldq_raw(p)
675 #define ldfl(p) ldfl_raw(p)
676 #define ldfq(p) ldfq_raw(p)
677 #define stb(p, v) stb_raw(p, v)
678 #define stw(p, v) stw_raw(p, v)
679 #define stl(p, v) stl_raw(p, v)
680 #define stq(p, v) stq_raw(p, v)
681 #define stfl(p, v) stfl_raw(p, v)
682 #define stfq(p, v) stfq_raw(p, v)
683
684 #define ldub_code(p) ldub_raw(p)
685 #define ldsb_code(p) ldsb_raw(p)
686 #define lduw_code(p) lduw_raw(p)
687 #define ldsw_code(p) ldsw_raw(p)
688 #define ldl_code(p) ldl_raw(p)
689 #define ldq_code(p) ldq_raw(p)
690
691 #define ldub_kernel(p) ldub_raw(p)
692 #define ldsb_kernel(p) ldsb_raw(p)
693 #define lduw_kernel(p) lduw_raw(p)
694 #define ldsw_kernel(p) ldsw_raw(p)
695 #define ldl_kernel(p) ldl_raw(p)
696 #define ldq_kernel(p) ldq_raw(p)
697 #define ldfl_kernel(p) ldfl_raw(p)
698 #define ldfq_kernel(p) ldfq_raw(p)
699 #define stb_kernel(p, v) stb_raw(p, v)
700 #define stw_kernel(p, v) stw_raw(p, v)
701 #define stl_kernel(p, v) stl_raw(p, v)
702 #define stq_kernel(p, v) stq_raw(p, v)
703 #define stfl_kernel(p, v) stfl_raw(p, v)
704 #define stfq_kernel(p, vt) stfq_raw(p, v)
705
706 #endif /* defined(CONFIG_USER_ONLY) */
707
708 /* page related stuff */
709
710 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
711 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
712 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
713
714 /* ??? These should be the larger of unsigned long and target_ulong. */
715 extern unsigned long qemu_real_host_page_size;
716 extern unsigned long qemu_host_page_bits;
717 extern unsigned long qemu_host_page_size;
718 extern unsigned long qemu_host_page_mask;
719
720 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
721
722 /* same as PROT_xxx */
723 #define PAGE_READ 0x0001
724 #define PAGE_WRITE 0x0002
725 #define PAGE_EXEC 0x0004
726 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
727 #define PAGE_VALID 0x0008
728 /* original state of the write flag (used when tracking self-modifying
729 code */
730 #define PAGE_WRITE_ORG 0x0010
731 #define PAGE_RESERVED 0x0020
732
733 void page_dump(FILE *f);
734 int page_get_flags(target_ulong address);
735 void page_set_flags(target_ulong start, target_ulong end, int flags);
736 int page_check_range(target_ulong start, target_ulong len, int flags);
737
738 void cpu_exec_init_all(unsigned long tb_size);
739 CPUState *cpu_copy(CPUState *env);
740
741 void cpu_dump_state(CPUState *env, FILE *f,
742 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
743 int flags);
744 void cpu_dump_statistics (CPUState *env, FILE *f,
745 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
746 int flags);
747
748 void cpu_abort(CPUState *env, const char *fmt, ...)
749 __attribute__ ((__format__ (__printf__, 2, 3)))
750 __attribute__ ((__noreturn__));
751 extern CPUState *first_cpu;
752 extern CPUState *cpu_single_env;
753 extern int64_t qemu_icount;
754 extern int use_icount;
755
756 #define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
757 #define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
758 #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
759 #define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
760 #define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
761 #define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */
762 #define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */
763 #define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */
764 #define CPU_INTERRUPT_VIRQ 0x100 /* virtual interrupt pending. */
765 #define CPU_INTERRUPT_NMI 0x200 /* NMI pending. */
766
767 void cpu_interrupt(CPUState *s, int mask);
768 void cpu_reset_interrupt(CPUState *env, int mask);
769
770 int cpu_watchpoint_insert(CPUState *env, target_ulong addr, int type);
771 int cpu_watchpoint_remove(CPUState *env, target_ulong addr);
772 void cpu_watchpoint_remove_all(CPUState *env);
773 int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
774 int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
775 void cpu_breakpoint_remove_all(CPUState *env);
776
777 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
778 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
779 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
780
781 void cpu_single_step(CPUState *env, int enabled);
782 void cpu_reset(CPUState *s);
783
784 /* Return the physical page corresponding to a virtual one. Use it
785 only for debugging because no protection checks are done. Return -1
786 if no page found. */
787 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
788
789 #define CPU_LOG_TB_OUT_ASM (1 << 0)
790 #define CPU_LOG_TB_IN_ASM (1 << 1)
791 #define CPU_LOG_TB_OP (1 << 2)
792 #define CPU_LOG_TB_OP_OPT (1 << 3)
793 #define CPU_LOG_INT (1 << 4)
794 #define CPU_LOG_EXEC (1 << 5)
795 #define CPU_LOG_PCALL (1 << 6)
796 #define CPU_LOG_IOPORT (1 << 7)
797 #define CPU_LOG_TB_CPU (1 << 8)
798
799 /* define log items */
800 typedef struct CPULogItem {
801 int mask;
802 const char *name;
803 const char *help;
804 } CPULogItem;
805
806 extern CPULogItem cpu_log_items[];
807
808 void cpu_set_log(int log_flags);
809 void cpu_set_log_filename(const char *filename);
810 int cpu_str_to_log_mask(const char *str);
811
812 /* IO ports API */
813
814 /* NOTE: as these functions may be even used when there is an isa
815 brige on non x86 targets, we always defined them */
816 #ifndef NO_CPU_IO_DEFS
817 void cpu_outb(CPUState *env, int addr, int val);
818 void cpu_outw(CPUState *env, int addr, int val);
819 void cpu_outl(CPUState *env, int addr, int val);
820 int cpu_inb(CPUState *env, int addr);
821 int cpu_inw(CPUState *env, int addr);
822 int cpu_inl(CPUState *env, int addr);
823 #endif
824
825 /* address in the RAM (different from a physical address) */
826 #ifdef USE_KQEMU
827 typedef uint32_t ram_addr_t;
828 #else
829 typedef unsigned long ram_addr_t;
830 #endif
831
832 /* memory API */
833
834 extern ram_addr_t phys_ram_size;
835 extern int phys_ram_fd;
836 extern uint8_t *phys_ram_base;
837 extern uint8_t *phys_ram_dirty;
838 extern ram_addr_t ram_size;
839
840 /* physical memory access */
841
842 /* MMIO pages are identified by a combination of an IO device index and
843 3 flags. The ROMD code stores the page ram offset in iotlb entry,
844 so only a limited number of ids are avaiable. */
845
846 #define IO_MEM_SHIFT 3
847 #define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
848
849 #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
850 #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
851 #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
852 #define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
853
854 /* Acts like a ROM when read and like a device when written. */
855 #define IO_MEM_ROMD (1)
856 #define IO_MEM_SUBPAGE (2)
857 #define IO_MEM_SUBWIDTH (4)
858
859 /* Flags stored in the low bits of the TLB virtual address. These are
860 defined so that fast path ram access is all zeros. */
861 /* Zero if TLB entry is valid. */
862 #define TLB_INVALID_MASK (1 << 3)
863 /* Set if TLB entry references a clean RAM page. The iotlb entry will
864 contain the page physical address. */
865 #define TLB_NOTDIRTY (1 << 4)
866 /* Set if TLB entry is an IO callback. */
867 #define TLB_MMIO (1 << 5)
868
869 typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
870 typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
871
872 void cpu_register_physical_memory(target_phys_addr_t start_addr,
873 ram_addr_t size,
874 ram_addr_t phys_offset);
875 ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
876 ram_addr_t qemu_ram_alloc(ram_addr_t);
877 void qemu_ram_free(ram_addr_t addr);
878 int cpu_register_io_memory(int io_index,
879 CPUReadMemoryFunc **mem_read,
880 CPUWriteMemoryFunc **mem_write,
881 void *opaque);
882 CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
883 CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
884
885 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
886 int len, int is_write);
cpu_physical_memory_read(target_phys_addr_t addr,uint8_t * buf,int len)887 static inline void cpu_physical_memory_read(target_phys_addr_t addr,
888 uint8_t *buf, int len)
889 {
890 cpu_physical_memory_rw(addr, buf, len, 0);
891 }
cpu_physical_memory_write(target_phys_addr_t addr,const uint8_t * buf,int len)892 static inline void cpu_physical_memory_write(target_phys_addr_t addr,
893 const uint8_t *buf, int len)
894 {
895 cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
896 }
897 uint32_t ldub_phys(target_phys_addr_t addr);
898 uint32_t lduw_phys(target_phys_addr_t addr);
899 uint32_t ldl_phys(target_phys_addr_t addr);
900 uint64_t ldq_phys(target_phys_addr_t addr);
901 void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
902 void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
903 void stb_phys(target_phys_addr_t addr, uint32_t val);
904 void stw_phys(target_phys_addr_t addr, uint32_t val);
905 void stl_phys(target_phys_addr_t addr, uint32_t val);
906 void stq_phys(target_phys_addr_t addr, uint64_t val);
907
908 void cpu_physical_memory_write_rom(target_phys_addr_t addr,
909 const uint8_t *buf, int len);
910 int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
911 uint8_t *buf, int len, int is_write);
912
913 #define VGA_DIRTY_FLAG 0x01
914 #define CODE_DIRTY_FLAG 0x02
915
916 /* read dirty bit (return 0 or 1) */
cpu_physical_memory_is_dirty(ram_addr_t addr)917 static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
918 {
919 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
920 }
921
cpu_physical_memory_get_dirty(ram_addr_t addr,int dirty_flags)922 static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
923 int dirty_flags)
924 {
925 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
926 }
927
cpu_physical_memory_set_dirty(ram_addr_t addr)928 static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
929 {
930 phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
931 }
932
933 void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
934 int dirty_flags);
935 void cpu_tlb_update_dirty(CPUState *env);
936
937 void dump_exec_info(FILE *f,
938 int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
939
940 /*******************************************/
941 /* host CPU ticks (if available) */
942
943 #if defined(__powerpc__)
944
get_tbl(void)945 static inline uint32_t get_tbl(void)
946 {
947 uint32_t tbl;
948 asm volatile("mftb %0" : "=r" (tbl));
949 return tbl;
950 }
951
get_tbu(void)952 static inline uint32_t get_tbu(void)
953 {
954 uint32_t tbl;
955 asm volatile("mftbu %0" : "=r" (tbl));
956 return tbl;
957 }
958
cpu_get_real_ticks(void)959 static inline int64_t cpu_get_real_ticks(void)
960 {
961 uint32_t l, h, h1;
962 /* NOTE: we test if wrapping has occurred */
963 do {
964 h = get_tbu();
965 l = get_tbl();
966 h1 = get_tbu();
967 } while (h != h1);
968 return ((int64_t)h << 32) | l;
969 }
970
971 #elif defined(__i386__)
972
cpu_get_real_ticks(void)973 static inline int64_t cpu_get_real_ticks(void)
974 {
975 int64_t val;
976 asm volatile ("rdtsc" : "=A" (val));
977 return val;
978 }
979
980 #elif defined(__x86_64__)
981
cpu_get_real_ticks(void)982 static inline int64_t cpu_get_real_ticks(void)
983 {
984 uint32_t low,high;
985 int64_t val;
986 asm volatile("rdtsc" : "=a" (low), "=d" (high));
987 val = high;
988 val <<= 32;
989 val |= low;
990 return val;
991 }
992
993 #elif defined(__hppa__)
994
cpu_get_real_ticks(void)995 static inline int64_t cpu_get_real_ticks(void)
996 {
997 int val;
998 asm volatile ("mfctl %%cr16, %0" : "=r"(val));
999 return val;
1000 }
1001
1002 #elif defined(__ia64)
1003
cpu_get_real_ticks(void)1004 static inline int64_t cpu_get_real_ticks(void)
1005 {
1006 int64_t val;
1007 asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory");
1008 return val;
1009 }
1010
1011 #elif defined(__s390__)
1012
cpu_get_real_ticks(void)1013 static inline int64_t cpu_get_real_ticks(void)
1014 {
1015 int64_t val;
1016 asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc");
1017 return val;
1018 }
1019
1020 #elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
1021
cpu_get_real_ticks(void)1022 static inline int64_t cpu_get_real_ticks (void)
1023 {
1024 #if defined(_LP64)
1025 uint64_t rval;
1026 asm volatile("rd %%tick,%0" : "=r"(rval));
1027 return rval;
1028 #else
1029 union {
1030 uint64_t i64;
1031 struct {
1032 uint32_t high;
1033 uint32_t low;
1034 } i32;
1035 } rval;
1036 asm volatile("rd %%tick,%1; srlx %1,32,%0"
1037 : "=r"(rval.i32.high), "=r"(rval.i32.low));
1038 return rval.i64;
1039 #endif
1040 }
1041
1042 #elif defined(__mips__)
1043
cpu_get_real_ticks(void)1044 static inline int64_t cpu_get_real_ticks(void)
1045 {
1046 #if __mips_isa_rev >= 2
1047 uint32_t count;
1048 static uint32_t cyc_per_count = 0;
1049
1050 if (!cyc_per_count)
1051 __asm__ __volatile__("rdhwr %0, $3" : "=r" (cyc_per_count));
1052
1053 __asm__ __volatile__("rdhwr %1, $2" : "=r" (count));
1054 return (int64_t)(count * cyc_per_count);
1055 #else
1056 /* FIXME */
1057 static int64_t ticks = 0;
1058 return ticks++;
1059 #endif
1060 }
1061
1062 #else
1063 /* The host CPU doesn't have an easily accessible cycle counter.
1064 Just return a monotonically increasing value. This will be
1065 totally wrong, but hopefully better than nothing. */
cpu_get_real_ticks(void)1066 static inline int64_t cpu_get_real_ticks (void)
1067 {
1068 static int64_t ticks = 0;
1069 return ticks++;
1070 }
1071 #endif
1072
1073 /* profiling */
1074 #ifdef CONFIG_PROFILER
profile_getclock(void)1075 static inline int64_t profile_getclock(void)
1076 {
1077 return cpu_get_real_ticks();
1078 }
1079
1080 extern int64_t kqemu_time, kqemu_time_start;
1081 extern int64_t qemu_time, qemu_time_start;
1082 extern int64_t tlb_flush_time;
1083 extern int64_t kqemu_exec_count;
1084 extern int64_t dev_time;
1085 extern int64_t kqemu_ret_int_count;
1086 extern int64_t kqemu_ret_excp_count;
1087 extern int64_t kqemu_ret_intr_count;
1088 #endif
1089
1090 #endif /* CPU_ALL_H */
1091