1 /* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20 #ifndef CPU_DEFS_H 21 #define CPU_DEFS_H 22 23 #include "config.h" 24 #include <setjmp.h> 25 #include <inttypes.h> 26 #include "osdep.h" 27 28 #ifndef TARGET_LONG_BITS 29 #error TARGET_LONG_BITS must be defined before including this header 30 #endif 31 32 #ifndef TARGET_PHYS_ADDR_BITS 33 #if TARGET_LONG_BITS >= HOST_LONG_BITS 34 #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS 35 #else 36 #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS 37 #endif 38 #endif 39 40 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) 41 42 /* target_ulong is the type of a virtual address */ 43 #if TARGET_LONG_SIZE == 4 44 typedef int32_t target_long; 45 typedef uint32_t target_ulong; 46 #define TARGET_FMT_lx "%08x" 47 #define TARGET_FMT_ld "%d" 48 #define TARGET_FMT_lu "%u" 49 #elif TARGET_LONG_SIZE == 8 50 typedef int64_t target_long; 51 typedef uint64_t target_ulong; 52 #define TARGET_FMT_lx "%016" PRIx64 53 #define TARGET_FMT_ld "%" PRId64 54 #define TARGET_FMT_lu "%" PRIu64 55 #else 56 #error TARGET_LONG_SIZE undefined 57 #endif 58 59 /* target_phys_addr_t is the type of a physical address (its size can 60 be different from 'target_ulong'). We have sizeof(target_phys_addr) 61 = max(sizeof(unsigned long), 62 sizeof(size_of_target_physical_address)) because we must pass a 63 host pointer to memory operations in some cases */ 64 65 #if TARGET_PHYS_ADDR_BITS == 32 66 typedef uint32_t target_phys_addr_t; 67 #define TARGET_FMT_plx "%08x" 68 #elif TARGET_PHYS_ADDR_BITS == 64 69 typedef uint64_t target_phys_addr_t; 70 #define TARGET_FMT_plx "%016" PRIx64 71 #else 72 #error TARGET_PHYS_ADDR_BITS undefined 73 #endif 74 75 #define HOST_LONG_SIZE (HOST_LONG_BITS / 8) 76 77 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 78 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 79 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 80 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 81 #define MAX_BREAKPOINTS 32 82 #define MAX_WATCHPOINTS 32 83 84 #define TB_JMP_CACHE_BITS 12 85 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) 86 87 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for 88 addresses on the same page. The top bits are the same. This allows 89 TLB invalidation to quickly clear a subset of the hash table. */ 90 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) 91 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) 92 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) 93 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) 94 95 #define CPU_TLB_BITS 8 96 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) 97 98 #if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32 99 #define CPU_TLB_ENTRY_BITS 4 100 #else 101 #define CPU_TLB_ENTRY_BITS 5 102 #endif 103 104 typedef struct CPUTLBEntry { 105 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address 106 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not 107 go directly to ram. 108 bit 3 : indicates that the entry is invalid 109 bit 2..0 : zero 110 */ 111 target_ulong addr_read; 112 target_ulong addr_write; 113 target_ulong addr_code; 114 /* Addend to virtual address to get physical address. IO accesses 115 use the correcponding iotlb value. */ 116 #if TARGET_PHYS_ADDR_BITS == 64 117 /* on i386 Linux make sure it is aligned */ 118 target_phys_addr_t addend __attribute__((aligned(8))); 119 #else 120 target_phys_addr_t addend; 121 #endif 122 /* padding to get a power of two size */ 123 uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - 124 (sizeof(target_ulong) * 3 + 125 ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) + 126 sizeof(target_phys_addr_t))]; 127 } CPUTLBEntry; 128 129 #ifdef WORDS_BIGENDIAN 130 typedef struct icount_decr_u16 { 131 uint16_t high; 132 uint16_t low; 133 } icount_decr_u16; 134 #else 135 typedef struct icount_decr_u16 { 136 uint16_t low; 137 uint16_t high; 138 } icount_decr_u16; 139 #endif 140 141 #define CPU_TEMP_BUF_NLONGS 128 142 #define CPU_COMMON \ 143 struct TranslationBlock *current_tb; /* currently executing TB */ \ 144 /* soft mmu support */ \ 145 /* in order to avoid passing too many arguments to the MMIO \ 146 helpers, we store some rarely used information in the CPU \ 147 context) */ \ 148 unsigned long mem_io_pc; /* host pc at which the memory was \ 149 accessed */ \ 150 target_ulong mem_io_vaddr; /* target virtual addr at which the \ 151 memory was accessed */ \ 152 uint32_t halted; /* Nonzero if the CPU is in suspend state */ \ 153 uint32_t interrupt_request; \ 154 /* The meaning of the MMU modes is defined in the target code. */ \ 155 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ 156 target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ 157 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ 158 /* buffer for temporaries in the code generator */ \ 159 long temp_buf[CPU_TEMP_BUF_NLONGS]; \ 160 \ 161 int64_t icount_extra; /* Instructions until next timer event. */ \ 162 /* Number of cycles left, with interrupt flag in high bit. \ 163 This allows a single read-compare-cbranch-write sequence to test \ 164 for both decrementer underflow and exceptions. */ \ 165 union { \ 166 uint32_t u32; \ 167 icount_decr_u16 u16; \ 168 } icount_decr; \ 169 uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \ 170 \ 171 /* from this point: preserved by CPU reset */ \ 172 /* ice debug support */ \ 173 target_ulong breakpoints[MAX_BREAKPOINTS]; \ 174 int nb_breakpoints; \ 175 int singlestep_enabled; \ 176 \ 177 struct { \ 178 target_ulong vaddr; \ 179 int type; /* PAGE_READ/PAGE_WRITE */ \ 180 } watchpoint[MAX_WATCHPOINTS]; \ 181 int nb_watchpoints; \ 182 int watchpoint_hit; \ 183 \ 184 /* Core interrupt code */ \ 185 jmp_buf jmp_env; \ 186 int exception_index; \ 187 \ 188 int user_mode_only; \ 189 \ 190 void *next_cpu; /* next CPU sharing TB cache */ \ 191 int cpu_index; /* CPU index (informative) */ \ 192 int running; /* Nonzero if cpu is currently running(usermode). */ \ 193 /* user data */ \ 194 void *opaque; \ 195 \ 196 const char *cpu_model_str; 197 198 #endif 199