1 #include "hw/hw.h"
2 #include "hw/boards.h"
3
register_machines(void)4 void register_machines(void)
5 {
6 #if 0 /* ANDROID */
7 qemu_register_machine(&integratorcp_machine);
8 qemu_register_machine(&versatilepb_machine);
9 qemu_register_machine(&versatileab_machine);
10 qemu_register_machine(&realview_machine);
11 qemu_register_machine(&akitapda_machine);
12 qemu_register_machine(&spitzpda_machine);
13 qemu_register_machine(&borzoipda_machine);
14 qemu_register_machine(&terrierpda_machine);
15 qemu_register_machine(&palmte_machine);
16 qemu_register_machine(&n800_machine);
17 qemu_register_machine(&n810_machine);
18 qemu_register_machine(&lm3s811evb_machine);
19 qemu_register_machine(&lm3s6965evb_machine);
20 qemu_register_machine(&connex_machine);
21 qemu_register_machine(&verdex_machine);
22 qemu_register_machine(&mainstone2_machine);
23 qemu_register_machine(&musicpal_machine);
24 qemu_register_machine(&tosapda_machine);
25 #endif
26 qemu_register_machine(&android_arm_machine);
27 }
28
cpu_save(QEMUFile * f,void * opaque)29 void cpu_save(QEMUFile *f, void *opaque)
30 {
31 int i;
32 CPUARMState *env = (CPUARMState *)opaque;
33
34 for (i = 0; i < 16; i++) {
35 qemu_put_be32(f, env->regs[i]);
36 }
37 qemu_put_be32(f, cpsr_read(env));
38 qemu_put_be32(f, env->spsr);
39 for (i = 0; i < 6; i++) {
40 qemu_put_be32(f, env->banked_spsr[i]);
41 qemu_put_be32(f, env->banked_r13[i]);
42 qemu_put_be32(f, env->banked_r14[i]);
43 }
44 for (i = 0; i < 5; i++) {
45 qemu_put_be32(f, env->usr_regs[i]);
46 qemu_put_be32(f, env->fiq_regs[i]);
47 }
48 qemu_put_be32(f, env->cp15.c0_cpuid);
49 qemu_put_be32(f, env->cp15.c0_cachetype);
50 qemu_put_be32(f, env->cp15.c1_sys);
51 qemu_put_be32(f, env->cp15.c1_coproc);
52 qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
53 qemu_put_be32(f, env->cp15.c2_base0);
54 qemu_put_be32(f, env->cp15.c2_base1);
55 qemu_put_be32(f, env->cp15.c2_mask);
56 qemu_put_be32(f, env->cp15.c2_data);
57 qemu_put_be32(f, env->cp15.c2_insn);
58 qemu_put_be32(f, env->cp15.c3);
59 qemu_put_be32(f, env->cp15.c5_insn);
60 qemu_put_be32(f, env->cp15.c5_data);
61 for (i = 0; i < 8; i++) {
62 qemu_put_be32(f, env->cp15.c6_region[i]);
63 }
64 qemu_put_be32(f, env->cp15.c6_insn);
65 qemu_put_be32(f, env->cp15.c6_data);
66 qemu_put_be32(f, env->cp15.c9_insn);
67 qemu_put_be32(f, env->cp15.c9_data);
68 qemu_put_be32(f, env->cp15.c13_fcse);
69 qemu_put_be32(f, env->cp15.c13_context);
70 qemu_put_be32(f, env->cp15.c13_tls1);
71 qemu_put_be32(f, env->cp15.c13_tls2);
72 qemu_put_be32(f, env->cp15.c13_tls3);
73 qemu_put_be32(f, env->cp15.c15_cpar);
74
75 qemu_put_be32(f, env->features);
76
77 if (arm_feature(env, ARM_FEATURE_VFP)) {
78 for (i = 0; i < 16; i++) {
79 CPU_DoubleU u;
80 u.d = env->vfp.regs[i];
81 qemu_put_be32(f, u.l.upper);
82 qemu_put_be32(f, u.l.lower);
83 }
84 for (i = 0; i < 16; i++) {
85 qemu_put_be32(f, env->vfp.xregs[i]);
86 }
87
88 /* TODO: Should use proper FPSCR access functions. */
89 qemu_put_be32(f, env->vfp.vec_len);
90 qemu_put_be32(f, env->vfp.vec_stride);
91
92 if (arm_feature(env, ARM_FEATURE_VFP3)) {
93 for (i = 16; i < 32; i++) {
94 CPU_DoubleU u;
95 u.d = env->vfp.regs[i];
96 qemu_put_be32(f, u.l.upper);
97 qemu_put_be32(f, u.l.lower);
98 }
99 }
100 }
101
102 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
103 for (i = 0; i < 16; i++) {
104 qemu_put_be64(f, env->iwmmxt.regs[i]);
105 }
106 for (i = 0; i < 16; i++) {
107 qemu_put_be32(f, env->iwmmxt.cregs[i]);
108 }
109 }
110
111 if (arm_feature(env, ARM_FEATURE_M)) {
112 qemu_put_be32(f, env->v7m.other_sp);
113 qemu_put_be32(f, env->v7m.vecbase);
114 qemu_put_be32(f, env->v7m.basepri);
115 qemu_put_be32(f, env->v7m.control);
116 qemu_put_be32(f, env->v7m.current_sp);
117 qemu_put_be32(f, env->v7m.exception);
118 }
119 }
120
cpu_load(QEMUFile * f,void * opaque,int version_id)121 int cpu_load(QEMUFile *f, void *opaque, int version_id)
122 {
123 CPUARMState *env = (CPUARMState *)opaque;
124 int i;
125
126 if (version_id != CPU_SAVE_VERSION)
127 return -EINVAL;
128
129 for (i = 0; i < 16; i++) {
130 env->regs[i] = qemu_get_be32(f);
131 }
132 cpsr_write(env, qemu_get_be32(f), 0xffffffff);
133 env->spsr = qemu_get_be32(f);
134 for (i = 0; i < 6; i++) {
135 env->banked_spsr[i] = qemu_get_be32(f);
136 env->banked_r13[i] = qemu_get_be32(f);
137 env->banked_r14[i] = qemu_get_be32(f);
138 }
139 for (i = 0; i < 5; i++) {
140 env->usr_regs[i] = qemu_get_be32(f);
141 env->fiq_regs[i] = qemu_get_be32(f);
142 }
143 env->cp15.c0_cpuid = qemu_get_be32(f);
144 env->cp15.c0_cachetype = qemu_get_be32(f);
145 env->cp15.c1_sys = qemu_get_be32(f);
146 env->cp15.c1_coproc = qemu_get_be32(f);
147 env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
148 env->cp15.c2_base0 = qemu_get_be32(f);
149 env->cp15.c2_base1 = qemu_get_be32(f);
150 env->cp15.c2_mask = qemu_get_be32(f);
151 env->cp15.c2_data = qemu_get_be32(f);
152 env->cp15.c2_insn = qemu_get_be32(f);
153 env->cp15.c3 = qemu_get_be32(f);
154 env->cp15.c5_insn = qemu_get_be32(f);
155 env->cp15.c5_data = qemu_get_be32(f);
156 for (i = 0; i < 8; i++) {
157 env->cp15.c6_region[i] = qemu_get_be32(f);
158 }
159 env->cp15.c6_insn = qemu_get_be32(f);
160 env->cp15.c6_data = qemu_get_be32(f);
161 env->cp15.c9_insn = qemu_get_be32(f);
162 env->cp15.c9_data = qemu_get_be32(f);
163 env->cp15.c13_fcse = qemu_get_be32(f);
164 env->cp15.c13_context = qemu_get_be32(f);
165 env->cp15.c13_tls1 = qemu_get_be32(f);
166 env->cp15.c13_tls2 = qemu_get_be32(f);
167 env->cp15.c13_tls3 = qemu_get_be32(f);
168 env->cp15.c15_cpar = qemu_get_be32(f);
169
170 env->features = qemu_get_be32(f);
171
172 if (arm_feature(env, ARM_FEATURE_VFP)) {
173 for (i = 0; i < 16; i++) {
174 CPU_DoubleU u;
175 u.l.upper = qemu_get_be32(f);
176 u.l.lower = qemu_get_be32(f);
177 env->vfp.regs[i] = u.d;
178 }
179 for (i = 0; i < 16; i++) {
180 env->vfp.xregs[i] = qemu_get_be32(f);
181 }
182
183 /* TODO: Should use proper FPSCR access functions. */
184 env->vfp.vec_len = qemu_get_be32(f);
185 env->vfp.vec_stride = qemu_get_be32(f);
186
187 if (arm_feature(env, ARM_FEATURE_VFP3)) {
188 for (i = 0; i < 16; i++) {
189 CPU_DoubleU u;
190 u.l.upper = qemu_get_be32(f);
191 u.l.lower = qemu_get_be32(f);
192 env->vfp.regs[i] = u.d;
193 }
194 }
195 }
196
197 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
198 for (i = 0; i < 16; i++) {
199 env->iwmmxt.regs[i] = qemu_get_be64(f);
200 }
201 for (i = 0; i < 16; i++) {
202 env->iwmmxt.cregs[i] = qemu_get_be32(f);
203 }
204 }
205
206 if (arm_feature(env, ARM_FEATURE_M)) {
207 env->v7m.other_sp = qemu_get_be32(f);
208 env->v7m.vecbase = qemu_get_be32(f);
209 env->v7m.basepri = qemu_get_be32(f);
210 env->v7m.control = qemu_get_be32(f);
211 env->v7m.current_sp = qemu_get_be32(f);
212 env->v7m.exception = qemu_get_be32(f);
213 }
214
215 return 0;
216 }
217
218
219