1 /*
2 * internal execution defines for qemu
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
22 #define DEBUG_DISAS
23
24 /* is_jmp field values */
25 #define DISAS_NEXT 0 /* next instruction can be analyzed */
26 #define DISAS_JUMP 1 /* only pc was modified dynamically */
27 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
28 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
29
30 typedef struct TranslationBlock TranslationBlock;
31
32 /* XXX: make safe guess about sizes */
33 #define MAX_OP_PER_INSTR 64
34 /* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
35 #define MAX_OPC_PARAM 10
36 #define OPC_BUF_SIZE 512
37 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
38
39 /* Maximum size a TCG op can expand to. This is complicated because a
40 single op may require several host instructions and regirster reloads.
41 For now take a wild guess at 128 bytes, which should allow at least
42 a couple of fixup instructions per argument. */
43 #define TCG_MAX_OP_SIZE 128
44
45 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
46
47 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
48 extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
49 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
50 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
51 extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
52 extern target_ulong gen_opc_jump_pc[2];
53 extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
54
55 typedef void (GenOpFunc)(void);
56 typedef void (GenOpFunc1)(long);
57 typedef void (GenOpFunc2)(long, long);
58 typedef void (GenOpFunc3)(long, long, long);
59
60 #include "qemu-log.h"
61
62 void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
63 void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
64 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
65 unsigned long searched_pc, int pc_pos, void *puc);
66
67 unsigned long code_gen_max_block_size(void);
68 void cpu_gen_init(void);
69 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
70 int *gen_code_size_ptr);
71 int cpu_restore_state(struct TranslationBlock *tb,
72 CPUState *env, unsigned long searched_pc,
73 void *puc);
74 int cpu_restore_state_copy(struct TranslationBlock *tb,
75 CPUState *env, unsigned long searched_pc,
76 void *puc);
77 void cpu_resume_from_signal(CPUState *env1, void *puc);
78 void cpu_io_recompile(CPUState *env, void *retaddr);
79 TranslationBlock *tb_gen_code(CPUState *env,
80 target_ulong pc, target_ulong cs_base, int flags,
81 int cflags);
82 void cpu_exec_init(CPUState *env);
83 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
84 void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
85 int is_cpu_write_access);
86 void tb_invalidate_page_range(target_ulong start, target_ulong end);
87 void tlb_flush_page(CPUState *env, target_ulong addr);
88 void tlb_flush(CPUState *env, int flush_global);
89 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
90 target_phys_addr_t paddr, int prot,
91 int mmu_idx, int is_softmmu);
tlb_set_page(CPUState * env1,target_ulong vaddr,target_phys_addr_t paddr,int prot,int mmu_idx,int is_softmmu)92 static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
93 target_phys_addr_t paddr, int prot,
94 int mmu_idx, int is_softmmu)
95 {
96 if (prot & PAGE_READ)
97 prot |= PAGE_EXEC;
98 return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
99 }
100
101 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
102
103 #define CODE_GEN_PHYS_HASH_BITS 15
104 #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
105
106 #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
107
108 /* estimated block size for TB allocation */
109 /* XXX: use a per code average code fragment size and modulate it
110 according to the host CPU */
111 #if defined(CONFIG_SOFTMMU)
112 #define CODE_GEN_AVG_BLOCK_SIZE 128
113 #else
114 #define CODE_GEN_AVG_BLOCK_SIZE 64
115 #endif
116
117 #if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__)
118 #define USE_DIRECT_JUMP
119 #endif
120 #if defined(__i386__) && !defined(_WIN32)
121 #define USE_DIRECT_JUMP
122 #endif
123
124 struct TranslationBlock {
125 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
126 target_ulong cs_base; /* CS base for this block */
127 uint64_t flags; /* flags defining in which context the code was generated */
128 uint16_t size; /* size of target code for this block (1 <=
129 size <= TARGET_PAGE_SIZE) */
130 uint16_t cflags; /* compile flags */
131 #define CF_COUNT_MASK 0x7fff
132 #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
133
134 uint8_t *tc_ptr; /* pointer to the translated code */
135 /* next matching tb for physical address. */
136 struct TranslationBlock *phys_hash_next;
137 /* first and second physical page containing code. The lower bit
138 of the pointer tells the index in page_next[] */
139 struct TranslationBlock *page_next[2];
140 target_ulong page_addr[2];
141
142 /* the following data are used to directly call another TB from
143 the code of this one. */
144 uint16_t tb_next_offset[2]; /* offset of original jump target */
145 #ifdef USE_DIRECT_JUMP
146 uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
147 #else
148 unsigned long tb_next[2]; /* address of jump generated code */
149 #endif
150 /* list of TBs jumping to this one. This is a circular list using
151 the two least significant bits of the pointers to tell what is
152 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
153 jmp_first */
154 struct TranslationBlock *jmp_next[2];
155 struct TranslationBlock *jmp_first;
156
157 #ifdef CONFIG_TRACE
158 struct BBRec *bb_rec;
159 uint64_t prev_time;
160 #endif
161 uint32_t icount;
162 };
163
tb_jmp_cache_hash_page(target_ulong pc)164 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
165 {
166 target_ulong tmp;
167 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
168 return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
169 }
170
tb_jmp_cache_hash_func(target_ulong pc)171 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
172 {
173 target_ulong tmp;
174 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
175 return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
176 | (tmp & TB_JMP_ADDR_MASK));
177 }
178
tb_phys_hash_func(unsigned long pc)179 static inline unsigned int tb_phys_hash_func(unsigned long pc)
180 {
181 return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
182 }
183
184 TranslationBlock *tb_alloc(target_ulong pc);
185 void tb_free(TranslationBlock *tb);
186 void tb_flush(CPUState *env);
187 void tb_link_phys(TranslationBlock *tb,
188 target_ulong phys_pc, target_ulong phys_page2);
189 void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
190
191 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
192 extern uint8_t *code_gen_ptr;
193 extern int code_gen_max_blocks;
194
195 #if defined(USE_DIRECT_JUMP)
196
197 #if defined(__powerpc__)
198 extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
199 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
200 #elif defined(__i386__) || defined(__x86_64__)
tb_set_jmp_target1(unsigned long jmp_addr,unsigned long addr)201 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
202 {
203 /* patch the branch destination */
204 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
205 /* no need to flush icache explicitly */
206 }
207 #elif defined(__arm__)
tb_set_jmp_target1(unsigned long jmp_addr,unsigned long addr)208 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
209 {
210 register unsigned long _beg __asm ("a1");
211 register unsigned long _end __asm ("a2");
212 register unsigned long _flg __asm ("a3");
213
214 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
215 *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff;
216
217 /* flush icache */
218 _beg = jmp_addr;
219 _end = jmp_addr + 4;
220 _flg = 0;
221 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
222 }
223 #endif
224
tb_set_jmp_target(TranslationBlock * tb,int n,unsigned long addr)225 static inline void tb_set_jmp_target(TranslationBlock *tb,
226 int n, unsigned long addr)
227 {
228 unsigned long offset;
229
230 offset = tb->tb_jmp_offset[n];
231 tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
232 offset = tb->tb_jmp_offset[n + 2];
233 if (offset != 0xffff)
234 tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
235 }
236
237 #else
238
239 /* set the jump target */
tb_set_jmp_target(TranslationBlock * tb,int n,unsigned long addr)240 static inline void tb_set_jmp_target(TranslationBlock *tb,
241 int n, unsigned long addr)
242 {
243 tb->tb_next[n] = addr;
244 }
245
246 #endif
247
tb_add_jump(TranslationBlock * tb,int n,TranslationBlock * tb_next)248 static inline void tb_add_jump(TranslationBlock *tb, int n,
249 TranslationBlock *tb_next)
250 {
251 /* NOTE: this test is only needed for thread safety */
252 if (!tb->jmp_next[n]) {
253 /* patch the native jump address */
254 tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
255
256 /* add in TB jmp circular list */
257 tb->jmp_next[n] = tb_next->jmp_first;
258 tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
259 }
260 }
261
262 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
263
264 #if defined(_WIN32)
265 #define ASM_DATA_SECTION ".section \".data\"\n"
266 #define ASM_PREVIOUS_SECTION ".section .text\n"
267 #elif defined(__APPLE__)
268 #define ASM_DATA_SECTION ".data\n"
269 #define ASM_PREVIOUS_SECTION ".text\n"
270 #else
271 #define ASM_DATA_SECTION ".section \".data\"\n"
272 #define ASM_PREVIOUS_SECTION ".previous\n"
273 #endif
274
275 #define ASM_OP_LABEL_NAME(n, opname) \
276 ASM_NAME(__op_label) #n "." ASM_NAME(opname)
277
278 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
279 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
280 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
281
282 #include "qemu-lock.h"
283
284 extern spinlock_t tb_lock;
285
286 extern int tb_invalidated_flag;
287
288 #if !defined(CONFIG_USER_ONLY)
289
290 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
291 void *retaddr);
292
293 #include "softmmu_defs.h"
294
295 #define ACCESS_TYPE (NB_MMU_MODES + 1)
296 #define MEMSUFFIX _code
297 #define env cpu_single_env
298
299 #define DATA_SIZE 1
300 #include "softmmu_header.h"
301
302 #define DATA_SIZE 2
303 #include "softmmu_header.h"
304
305 #define DATA_SIZE 4
306 #include "softmmu_header.h"
307
308 #define DATA_SIZE 8
309 #include "softmmu_header.h"
310
311 #undef ACCESS_TYPE
312 #undef MEMSUFFIX
313 #undef env
314
315 #endif
316
317 #if defined(CONFIG_USER_ONLY)
get_phys_addr_code(CPUState * env1,target_ulong addr)318 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
319 {
320 return addr;
321 }
322 #else
323 /* NOTE: this function can trigger an exception */
324 /* NOTE2: the returned address is not exactly the physical address: it
325 is the offset relative to phys_ram_base */
get_phys_addr_code(CPUState * env1,target_ulong addr)326 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
327 {
328 int mmu_idx, page_index, pd;
329
330 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
331 mmu_idx = cpu_mmu_index(env1);
332 if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
333 (addr & TARGET_PAGE_MASK))) {
334 ldub_code(addr);
335 }
336 pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
337 if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
338 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
339 do_unassigned_access(addr, 0, 1, 0);
340 #else
341 cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
342 #endif
343 }
344 return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;
345 }
346
347 /* Deterministic execution requires that IO only be performed on the last
348 instruction of a TB so that interrupts take effect immediately. */
can_do_io(CPUState * env)349 static inline int can_do_io(CPUState *env)
350 {
351 if (!use_icount)
352 return 1;
353
354 /* If not executing code then assume we are ok. */
355 if (!env->current_tb)
356 return 1;
357
358 return env->can_do_io != 0;
359 }
360 #endif
361
362 #ifdef USE_KQEMU
363 #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
364
365 #define MSR_QPI_COMMBASE 0xfabe0010
366
367 int kqemu_init(CPUState *env);
368 int kqemu_cpu_exec(CPUState *env);
369 void kqemu_flush_page(CPUState *env, target_ulong addr);
370 void kqemu_flush(CPUState *env, int global);
371 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
372 void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
373 void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size,
374 ram_addr_t phys_offset);
375 void kqemu_cpu_interrupt(CPUState *env);
376 void kqemu_record_dump(void);
377
378 extern uint32_t kqemu_comm_base;
379
kqemu_is_ok(CPUState * env)380 static inline int kqemu_is_ok(CPUState *env)
381 {
382 return(env->kqemu_enabled &&
383 (env->cr[0] & CR0_PE_MASK) &&
384 !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
385 (env->eflags & IF_MASK) &&
386 !(env->eflags & VM_MASK) &&
387 (env->kqemu_enabled == 2 ||
388 ((env->hflags & HF_CPL_MASK) == 3 &&
389 (env->eflags & IOPL_MASK) != IOPL_MASK)));
390 }
391
392 #endif
393