1 /* 2 * Copyright (c) 2008, Google Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in 12 * the documentation and/or other materials provided with the 13 * distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 18 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 19 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 25 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef __ASM_ARCH_MSM7200_DMOV_H 30 #define __ASM_ARCH_MSM7200_DMOV_H 31 32 #define MSM_DMOV_BASE 0xA9700000 33 34 /* see 80-VA736-2 C pp 415-439 */ 35 36 #define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2)) 37 #define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2)) 38 #define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2)) 39 #define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2)) 40 41 /* only security domain 3 is available to the ARM11 42 ** 43 ** SD0 -> mARM trusted, SD1 -> mARM nontrusted, SD2 -> aDSP, SD3 -> aARM 44 ** 45 */ 46 47 #define DMOV_CMD_PTR(ch) DMOV_SD3(0x000, ch) 48 #define DMOV_CMD_LIST (0 << 29) /* does not work */ 49 #define DMOV_CMD_PTR_LIST (1 << 29) /* works */ 50 #define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */ 51 #define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */ 52 #define DMOV_CMD_ADDR(addr) ((addr) >> 3) 53 54 #define DMOV_RSLT(ch) DMOV_SD3(0x040, ch) 55 #define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */ 56 #define DMOV_RSLT_ERROR (1 << 3) 57 #define DMOV_RSLT_FLUSH (1 << 2) 58 #define DMOV_RSLT_DONE (1 << 1) /* top pointer done */ 59 #define DMOV_RSLT_USER (1 << 0) /* command with FR force result */ 60 61 #define DMOV_FLUSH0(ch) DMOV_SD3(0x080, ch) 62 #define DMOV_FLUSH1(ch) DMOV_SD3(0x0C0, ch) 63 #define DMOV_FLUSH2(ch) DMOV_SD3(0x100, ch) 64 #define DMOV_FLUSH3(ch) DMOV_SD3(0x140, ch) 65 #define DMOV_FLUSH4(ch) DMOV_SD3(0x180, ch) 66 #define DMOV_FLUSH5(ch) DMOV_SD3(0x1C0, ch) 67 68 #define DMOV_STATUS(ch) DMOV_SD3(0x200, ch) 69 #define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29)) 70 #define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3) 71 #define DMOV_STATUS_RSLT_VALID (1 << 1) 72 #define DMOV_STATUS_CMD_PTR_RDY (1 << 0) 73 74 #define DMOV_ISR DMOV_SD3(0x380, 0) 75 76 #define DMOV_CONFIG(ch) DMOV_SD3(0x300, ch) 77 #define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2) 78 #define DMOV_CONFIG_FOREC_FLUSH_RSLT (1 << 1) 79 #define DMOV_CONFIG_IRQ_EN (1 << 0) 80 81 /* channel assignments - from qc/dmov_7500.h */ 82 83 #define DMOV_NAND_CHAN 7 84 #define DMOV_NAND_CRCI_CMD 5 85 #define DMOV_NAND_CRCI_DATA 4 86 87 #define DMOV_SDC1_CHAN 8 88 #define DMOV_SDC1_CRCI 6 89 90 #define DMOV_SDC2_CHAN 8 91 #define DMOV_SDC2_CRCI 7 92 93 #define DMOV_TSIF_CHAN 10 94 #define DMOV_TSIF_CRCI 10 95 96 #define DMOV_USB_CHAN 11 97 98 /* no client rate control ifc (eg, ram) */ 99 #define DMOV_NONE_CRCI 0 100 101 102 /* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover 103 ** is going to walk a list of 32bit pointers as described below. Each 104 ** pointer points to a *array* of dmov_s, etc structs. The last pointer 105 ** in the list is marked with CMD_PTR_LP. The last struct in each array 106 ** is marked with CMD_LC (see below). 107 */ 108 #define CMD_PTR_ADDR(addr) ((addr) >> 3) 109 #define CMD_PTR_LP (1 << 31) /* last pointer */ 110 #define CMD_PTR_PT (3 << 29) /* ? */ 111 112 113 /* Single Item Mode -- seems to work as expected */ 114 typedef struct { 115 unsigned cmd; 116 unsigned src; 117 unsigned dst; 118 unsigned len; 119 } dmov_s; 120 121 /* Scatter/Gather Mode -- does this work?*/ 122 typedef struct { 123 unsigned cmd; 124 unsigned src_dscr; 125 unsigned dst_dscr; 126 unsigned _reserved; 127 } dmov_sg; 128 129 /* bits for the cmd field of the above structures */ 130 131 #define CMD_LC (1 << 31) /* last command */ 132 #define CMD_FR (1 << 22) /* force result -- does not work? */ 133 #define CMD_OCU (1 << 21) /* other channel unblock */ 134 #define CMD_OCB (1 << 20) /* other channel block */ 135 #define CMD_TCB (1 << 19) /* ? */ 136 #define CMD_DAH (1 << 18) /* destination address hold -- does not work?*/ 137 #define CMD_SAH (1 << 17) /* source address hold -- does not work? */ 138 139 #define CMD_MODE_SINGLE (0 << 0) /* dmov_s structure used */ 140 #define CMD_MODE_SG (1 << 0) /* untested */ 141 #define CMD_MODE_IND_SG (2 << 0) /* untested */ 142 #define CMD_MODE_BOX (3 << 0) /* untested */ 143 144 #define CMD_DST_SWAP_BYTES (1 << 14) /* exchange each byte n with byte n+1 */ 145 #define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */ 146 #define CMD_DST_SWAP_WORDS (1 << 16) /* exchange each word n with word n+1 */ 147 148 #define CMD_SRC_SWAP_BYTES (1 << 11) /* exchange each byte n with byte n+1 */ 149 #define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */ 150 #define CMD_SRC_SWAP_WORDS (1 << 13) /* exchange each word n with word n+1 */ 151 152 #define CMD_DST_CRCI(n) (((n) & 15) << 7) 153 #define CMD_SRC_CRCI(n) (((n) & 15) << 3) 154 155 156 /* NOTES: 157 ** 158 ** Looks like Channels 4, 5, 6, 7, 8, 10, 11 are available to the ARM11 159 ** 160 */ 161 #endif 162