1 /* 2 * Copyright (c) 2008, Google Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in 12 * the documentation and/or other materials provided with the 13 * distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 18 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 19 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 25 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef __ASM_ARCH_MSM7200_NAND_H 30 #define __ASM_ARCH_MSM7200_NAND_H 31 32 #define MSM_NAND_BASE 0xA0A00000 33 34 /* see 80-VA736-2 C pp 354-414 */ 35 36 #define NAND_REG(off) (MSM_NAND_BASE + (off)) 37 38 #define NAND_FLASH_CMD NAND_REG(0x0000) 39 #define NAND_ADDR0 NAND_REG(0x0004) 40 #define NAND_ADDR1 NAND_REG(0x0008) 41 #define NAND_FLASH_CHIP_SELECT NAND_REG(0x000C) 42 #define NAND_EXEC_CMD NAND_REG(0x0010) 43 #define NAND_FLASH_STATUS NAND_REG(0x0014) 44 #define NAND_BUFFER_STATUS NAND_REG(0x0018) 45 #define NAND_DEV0_CFG0 NAND_REG(0x0020) 46 #define NAND_DEV0_CFG1 NAND_REG(0x0024) 47 #define NAND_DEV1_CFG0 NAND_REG(0x0030) 48 #define NAND_DEV1_CFG1 NAND_REG(0x0034) 49 #define NAND_READ_ID NAND_REG(0x0040) 50 #define NAND_READ_STATUS NAND_REG(0x0044) 51 #define NAND_CONFIG_DATA NAND_REG(0x0050) 52 #define NAND_CONFIG NAND_REG(0x0054) 53 #define NAND_CONFIG_MODE NAND_REG(0x0058) 54 #define NAND_CONFIG_STATUS NAND_REG(0x0060) 55 #define NAND_MACRO1_REG NAND_REG(0x0064) 56 #define NAND_XFR_STEP1 NAND_REG(0x0070) 57 #define NAND_XFR_STEP2 NAND_REG(0x0074) 58 #define NAND_XFR_STEP3 NAND_REG(0x0078) 59 #define NAND_XFR_STEP4 NAND_REG(0x007C) 60 #define NAND_XFR_STEP5 NAND_REG(0x0080) 61 #define NAND_XFR_STEP6 NAND_REG(0x0084) 62 #define NAND_XFR_STEP7 NAND_REG(0x0088) 63 #define NAND_DEV_CMD0 NAND_REG(0x00A0) 64 #define NAND_DEV_CMD1 NAND_REG(0x00A4) 65 #define NAND_DEV_CMD2 NAND_REG(0x00A8) 66 #define NAND_DEV_CMD_VLD NAND_REG(0x00AC) 67 #define NAND_EBI2_MISR_SIG_REG NAND_REG(0x00B0) 68 #define NAND_EBI2_ECC_BUF_CFG NAND_REG(0x00F0) 69 #define NAND_FLASH_BUFFER NAND_REG(0x0100) 70 71 /* device commands */ 72 73 #define NAND_CMD_SOFT_RESET 0x01 74 #define NAND_CMD_PAGE_READ 0x32 75 #define NAND_CMD_PAGE_READ_ECC 0x33 76 #define NAND_CMD_PAGE_READ_ALL 0x34 77 #define NAND_CMD_SEQ_PAGE_READ 0x15 78 #define NAND_CMD_PRG_PAGE 0x36 79 #define NAND_CMD_PRG_PAGE_ECC 0x37 80 #define NAND_CMD_PRG_PAGE_ALL 0x39 81 #define NAND_CMD_BLOCK_ERASE 0x3A 82 #define NAND_CMD_FETCH_ID 0x0B 83 #define NAND_CMD_STATUS 0x0C 84 #define NAND_CMD_RESET 0x0D 85 86 #endif 87