Lines Matching refs:imm
3268 Immediate imm(second.GetConstant()->AsIntConstant()->GetValue()); in VisitSub() local
3269 __ subl(first.AsRegister<CpuRegister>(), imm); in VisitSub()
3371 Immediate imm(mul->InputAt(1)->AsIntConstant()->GetValue()); in VisitMul() local
3372 __ imull(out.AsRegister<CpuRegister>(), first.AsRegister<CpuRegister>(), imm); in VisitMul()
3529 int64_t imm = Int64FromConstant(second.GetConstant()); in DivRemOneOrMinusOne() local
3531 DCHECK(imm == 1 || imm == -1); in DivRemOneOrMinusOne()
3539 if (imm == -1) { in DivRemOneOrMinusOne()
3551 if (imm == -1) { in DivRemOneOrMinusOne()
3567 int64_t imm = Int64FromConstant(second.GetConstant()); in RemByPowerOfTwo() local
3568 DCHECK(IsPowerOfTwo(AbsOrMin(imm))); in RemByPowerOfTwo()
3569 uint64_t abs_imm = AbsOrMin(imm); in RemByPowerOfTwo()
3603 int64_t imm = Int64FromConstant(second.GetConstant()); in DivByPowerOfTwo() local
3604 DCHECK(IsPowerOfTwo(AbsOrMin(imm))); in DivByPowerOfTwo()
3605 uint64_t abs_imm = AbsOrMin(imm); in DivByPowerOfTwo()
3621 int shift = CTZ(imm); in DivByPowerOfTwo()
3624 if (imm < 0) { in DivByPowerOfTwo()
3642 int shift = CTZ(imm); in DivByPowerOfTwo()
3645 if (imm < 0) { in DivByPowerOfTwo()
3679 int imm = second.GetConstant()->AsIntConstant()->GetValue(); in GenerateDivRemWithAnyConstant() local
3681 CalculateMagicAndShiftForDivRem(imm, false /* is_long= */, &magic, &shift); in GenerateDivRemWithAnyConstant()
3688 if (imm > 0 && magic < 0) { in GenerateDivRemWithAnyConstant()
3690 } else if (imm < 0 && magic > 0) { in GenerateDivRemWithAnyConstant()
3704 __ imull(edx, Immediate(imm)); in GenerateDivRemWithAnyConstant()
3711 int64_t imm = second.GetConstant()->AsLongConstant()->GetValue(); in GenerateDivRemWithAnyConstant() local
3718 CalculateMagicAndShiftForDivRem(imm, true /* is_long= */, &magic, &shift); in GenerateDivRemWithAnyConstant()
3729 if (imm > 0 && magic < 0) { in GenerateDivRemWithAnyConstant()
3732 } else if (imm < 0 && magic > 0) { in GenerateDivRemWithAnyConstant()
3750 if (IsInt<32>(imm)) { in GenerateDivRemWithAnyConstant()
3751 __ imulq(rdx, Immediate(static_cast<int32_t>(imm))); in GenerateDivRemWithAnyConstant()
3753 __ imulq(rdx, codegen_->LiteralInt64Address(imm)); in GenerateDivRemWithAnyConstant()
3779 int64_t imm = Int64FromConstant(second.GetConstant()); in GenerateDivRemIntegral() local
3781 if (imm == 0) { in GenerateDivRemIntegral()
3783 } else if (imm == 1 || imm == -1) { in GenerateDivRemIntegral()
3785 } else if (IsPowerOfTwo(AbsOrMin(imm))) { in GenerateDivRemIntegral()
3792 DCHECK(imm <= -2 || imm >= 2); in GenerateDivRemIntegral()
4287 Immediate imm(second.GetConstant()->AsIntConstant()->GetValue() & kMaxIntShiftDistance); in HandleShift() local
4289 __ shll(first_reg, imm); in HandleShift()
4291 __ sarl(first_reg, imm); in HandleShift()
4293 __ shrl(first_reg, imm); in HandleShift()
4309 Immediate imm(second.GetConstant()->AsIntConstant()->GetValue() & kMaxLongShiftDistance); in HandleShift() local
4311 __ shlq(first_reg, imm); in HandleShift()
4313 __ sarq(first_reg, imm); in HandleShift()
4315 __ shrq(first_reg, imm); in HandleShift()
4356 Immediate imm(second.GetConstant()->AsIntConstant()->GetValue() & kMaxIntShiftDistance); in VisitRor() local
4357 __ rorl(first_reg, imm); in VisitRor()
4365 Immediate imm(second.GetConstant()->AsIntConstant()->GetValue() & kMaxLongShiftDistance); in VisitRor() local
4366 __ rorq(first_reg, imm); in VisitRor()
5664 Immediate imm(bit_cast<int32_t, float>(fp_value)); in EmitMove()
5665 __ movl(Address(CpuRegister(RSP), destination.GetStackIndex()), imm); in EmitMove()
6871 Immediate imm(second.GetConstant()->AsIntConstant()->GetValue()); in HandleBitwiseOperation() local
6873 __ andl(first.AsRegister<CpuRegister>(), imm); in HandleBitwiseOperation()
6875 __ orl(first.AsRegister<CpuRegister>(), imm); in HandleBitwiseOperation()
6878 __ xorl(first.AsRegister<CpuRegister>(), imm); in HandleBitwiseOperation()