Lines Matching defs:rt
99 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, in EmitR()
126 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, in EmitRtd()
139 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { in EmitI()
303 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Addu()
307 void Mips64Assembler::Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Addiu()
311 void Mips64Assembler::Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Daddu()
315 void Mips64Assembler::Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Daddiu()
319 void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Subu()
323 void Mips64Assembler::Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dsubu()
327 void Mips64Assembler::MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MulR6()
331 void Mips64Assembler::MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MuhR6()
335 void Mips64Assembler::DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in DivR6()
339 void Mips64Assembler::ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in ModR6()
343 void Mips64Assembler::DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in DivuR6()
347 void Mips64Assembler::ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in ModuR6()
351 void Mips64Assembler::Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmul()
355 void Mips64Assembler::Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmuh()
359 void Mips64Assembler::Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Ddiv()
363 void Mips64Assembler::Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmod()
367 void Mips64Assembler::Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Ddivu()
371 void Mips64Assembler::Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmodu()
375 void Mips64Assembler::And(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in And()
379 void Mips64Assembler::Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Andi()
383 void Mips64Assembler::Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Or()
387 void Mips64Assembler::Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Ori()
391 void Mips64Assembler::Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Xor()
395 void Mips64Assembler::Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Xori()
399 void Mips64Assembler::Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Nor()
403 void Mips64Assembler::Bitswap(GpuRegister rd, GpuRegister rt) { in Bitswap()
407 void Mips64Assembler::Dbitswap(GpuRegister rd, GpuRegister rt) { in Dbitswap()
411 void Mips64Assembler::Seb(GpuRegister rd, GpuRegister rt) { in Seb()
415 void Mips64Assembler::Seh(GpuRegister rd, GpuRegister rt) { in Seh()
419 void Mips64Assembler::Dsbh(GpuRegister rd, GpuRegister rt) { in Dsbh()
423 void Mips64Assembler::Dshd(GpuRegister rd, GpuRegister rt) { in Dshd()
427 void Mips64Assembler::Dext(GpuRegister rt, GpuRegister rs, int pos, int size) { in Dext()
433 void Mips64Assembler::Ins(GpuRegister rd, GpuRegister rt, int pos, int size) { in Ins()
440 void Mips64Assembler::Dinsm(GpuRegister rt, GpuRegister rs, int pos, int size) { in Dinsm()
447 void Mips64Assembler::Dinsu(GpuRegister rt, GpuRegister rs, int pos, int size) { in Dinsu()
454 void Mips64Assembler::Dins(GpuRegister rt, GpuRegister rs, int pos, int size) { in Dins()
461 void Mips64Assembler::DblIns(GpuRegister rt, GpuRegister rs, int pos, int size) { in DblIns()
471 void Mips64Assembler::Lsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne) { in Lsa()
477 void Mips64Assembler::Dlsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne) { in Dlsa()
483 void Mips64Assembler::Wsbh(GpuRegister rd, GpuRegister rt) { in Wsbh()
487 void Mips64Assembler::Sc(GpuRegister rt, GpuRegister base, int16_t imm9) { in Sc()
492 void Mips64Assembler::Scd(GpuRegister rt, GpuRegister base, int16_t imm9) { in Scd()
497 void Mips64Assembler::Ll(GpuRegister rt, GpuRegister base, int16_t imm9) { in Ll()
502 void Mips64Assembler::Lld(GpuRegister rt, GpuRegister base, int16_t imm9) { in Lld()
507 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) { in Sll()
511 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) { in Srl()
515 void Mips64Assembler::Rotr(GpuRegister rd, GpuRegister rt, int shamt) { in Rotr()
519 void Mips64Assembler::Sra(GpuRegister rd, GpuRegister rt, int shamt) { in Sra()
523 void Mips64Assembler::Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Sllv()
527 void Mips64Assembler::Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Rotrv()
531 void Mips64Assembler::Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Srlv()
535 void Mips64Assembler::Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Srav()
539 void Mips64Assembler::Dsll(GpuRegister rd, GpuRegister rt, int shamt) { in Dsll()
543 void Mips64Assembler::Dsrl(GpuRegister rd, GpuRegister rt, int shamt) { in Dsrl()
547 void Mips64Assembler::Drotr(GpuRegister rd, GpuRegister rt, int shamt) { in Drotr()
551 void Mips64Assembler::Dsra(GpuRegister rd, GpuRegister rt, int shamt) { in Dsra()
555 void Mips64Assembler::Dsll32(GpuRegister rd, GpuRegister rt, int shamt) { in Dsll32()
559 void Mips64Assembler::Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) { in Dsrl32()
563 void Mips64Assembler::Drotr32(GpuRegister rd, GpuRegister rt, int shamt) { in Drotr32()
567 void Mips64Assembler::Dsra32(GpuRegister rd, GpuRegister rt, int shamt) { in Dsra32()
571 void Mips64Assembler::Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Dsllv()
575 void Mips64Assembler::Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Dsrlv()
579 void Mips64Assembler::Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Drotrv()
583 void Mips64Assembler::Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Dsrav()
587 void Mips64Assembler::Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lb()
591 void Mips64Assembler::Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lh()
595 void Mips64Assembler::Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lw()
599 void Mips64Assembler::Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Ld()
603 void Mips64Assembler::Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lbu()
607 void Mips64Assembler::Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lhu()
611 void Mips64Assembler::Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lwu()
630 void Mips64Assembler::Lui(GpuRegister rt, uint16_t imm16) { in Lui()
634 void Mips64Assembler::Aui(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Aui()
638 void Mips64Assembler::Daui(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Daui()
656 void Mips64Assembler::Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sb()
660 void Mips64Assembler::Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sh()
664 void Mips64Assembler::Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sw()
668 void Mips64Assembler::Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sd()
672 void Mips64Assembler::Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Slt()
676 void Mips64Assembler::Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Sltu()
680 void Mips64Assembler::Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Slti()
684 void Mips64Assembler::Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sltiu()
688 void Mips64Assembler::Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Seleqz()
692 void Mips64Assembler::Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Selnez()
741 void Mips64Assembler::Jic(GpuRegister rt, uint16_t imm16) { in Jic()
745 void Mips64Assembler::Jialc(GpuRegister rt, uint16_t imm16) { in Jialc()
749 void Mips64Assembler::Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bltc()
756 void Mips64Assembler::Bltzc(GpuRegister rt, uint16_t imm16) { in Bltzc()
761 void Mips64Assembler::Bgtzc(GpuRegister rt, uint16_t imm16) { in Bgtzc()
766 void Mips64Assembler::Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bgec()
773 void Mips64Assembler::Bgezc(GpuRegister rt, uint16_t imm16) { in Bgezc()
778 void Mips64Assembler::Blezc(GpuRegister rt, uint16_t imm16) { in Blezc()
783 void Mips64Assembler::Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bltuc()
790 void Mips64Assembler::Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bgeuc()
797 void Mips64Assembler::Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Beqc()
804 void Mips64Assembler::Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bnec()
829 void Mips64Assembler::Beq(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Beq()
833 void Mips64Assembler::Bne(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bne()
837 void Mips64Assembler::Beqz(GpuRegister rt, uint16_t imm16) { in Beqz()
841 void Mips64Assembler::Bnez(GpuRegister rt, uint16_t imm16) { in Bnez()
845 void Mips64Assembler::Bltz(GpuRegister rt, uint16_t imm16) { in Bltz()
849 void Mips64Assembler::Bgez(GpuRegister rt, uint16_t imm16) { in Bgez()
853 void Mips64Assembler::Blez(GpuRegister rt, uint16_t imm16) { in Blez()
857 void Mips64Assembler::Bgtz(GpuRegister rt, uint16_t imm16) { in Bgtz()
863 GpuRegister rt, in EmitBcondR6()
930 GpuRegister rt, in EmitBcondR2()
1265 void Mips64Assembler::Mfc1(GpuRegister rt, FpuRegister fs) { in Mfc1()
1269 void Mips64Assembler::Mfhc1(GpuRegister rt, FpuRegister fs) { in Mfhc1()
1273 void Mips64Assembler::Mtc1(GpuRegister rt, FpuRegister fs) { in Mtc1()
1277 void Mips64Assembler::Mthc1(GpuRegister rt, FpuRegister fs) { in Mthc1()
1281 void Mips64Assembler::Dmfc1(GpuRegister rt, FpuRegister fs) { in Dmfc1()
1285 void Mips64Assembler::Dmtc1(GpuRegister rt, FpuRegister fs) { in Dmtc1()
2325 void Mips64Assembler::Addiu32(GpuRegister rt, GpuRegister rs, int32_t value) { in Addiu32()
2340 void Mips64Assembler::Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp) { in Daddiu64()
3280 void Mips64Assembler::Bltc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Bltc()
3284 void Mips64Assembler::Bltzc(GpuRegister rt, Mips64Label* label, bool is_bare) { in Bltzc()
3288 void Mips64Assembler::Bgtzc(GpuRegister rt, Mips64Label* label, bool is_bare) { in Bgtzc()
3292 void Mips64Assembler::Bgec(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Bgec()
3296 void Mips64Assembler::Bgezc(GpuRegister rt, Mips64Label* label, bool is_bare) { in Bgezc()
3300 void Mips64Assembler::Blezc(GpuRegister rt, Mips64Label* label, bool is_bare) { in Blezc()
3304 void Mips64Assembler::Bltuc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Bltuc()
3308 void Mips64Assembler::Bgeuc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Bgeuc()
3312 void Mips64Assembler::Beqc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Beqc()
3316 void Mips64Assembler::Bnec(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Bnec()
3336 void Mips64Assembler::Bltz(GpuRegister rt, Mips64Label* label, bool is_bare) { in Bltz()
3341 void Mips64Assembler::Bgtz(GpuRegister rt, Mips64Label* label, bool is_bare) { in Bgtz()
3346 void Mips64Assembler::Bgez(GpuRegister rt, Mips64Label* label, bool is_bare) { in Bgez()
3351 void Mips64Assembler::Blez(GpuRegister rt, Mips64Label* label, bool is_bare) { in Blez()
3356 void Mips64Assembler::Beq(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Beq()
3361 void Mips64Assembler::Bne(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Bne()