Lines Matching refs:ft
164 void Mips64Assembler::EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd, in EmitFR() argument
166 CHECK_NE(ft, kNoFpuRegister); in EmitFR()
171 static_cast<uint32_t>(ft) << kFtShift | in EmitFR()
178 void Mips64Assembler::EmitFI(int opcode, int fmt, FpuRegister ft, uint16_t imm) { in EmitFI() argument
179 CHECK_NE(ft, kNoFpuRegister); in EmitFI()
182 static_cast<uint32_t>(ft) << kFtShift | in EmitFI()
821 void Mips64Assembler::Bc1eqz(FpuRegister ft, uint16_t imm16) { in Bc1eqz() argument
822 EmitFI(0x11, 0x9, ft, imm16); in Bc1eqz()
825 void Mips64Assembler::Bc1nez(FpuRegister ft, uint16_t imm16) { in Bc1nez() argument
826 EmitFI(0x11, 0xD, ft, imm16); in Bc1nez()
977 void Mips64Assembler::AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in AddS() argument
978 EmitFR(0x11, 0x10, ft, fs, fd, 0x0); in AddS()
981 void Mips64Assembler::SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in SubS() argument
982 EmitFR(0x11, 0x10, ft, fs, fd, 0x1); in SubS()
985 void Mips64Assembler::MulS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in MulS() argument
986 EmitFR(0x11, 0x10, ft, fs, fd, 0x2); in MulS()
989 void Mips64Assembler::DivS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in DivS() argument
990 EmitFR(0x11, 0x10, ft, fs, fd, 0x3); in DivS()
993 void Mips64Assembler::AddD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in AddD() argument
994 EmitFR(0x11, 0x11, ft, fs, fd, 0x0); in AddD()
997 void Mips64Assembler::SubD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in SubD() argument
998 EmitFR(0x11, 0x11, ft, fs, fd, 0x1); in SubD()
1001 void Mips64Assembler::MulD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in MulD() argument
1002 EmitFR(0x11, 0x11, ft, fs, fd, 0x2); in MulD()
1005 void Mips64Assembler::DivD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in DivD() argument
1006 EmitFR(0x11, 0x11, ft, fs, fd, 0x3); in DivD()
1105 void Mips64Assembler::SelS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in SelS() argument
1106 EmitFR(0x11, 0x10, ft, fs, fd, 0x10); in SelS()
1109 void Mips64Assembler::SelD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in SelD() argument
1110 EmitFR(0x11, 0x11, ft, fs, fd, 0x10); in SelD()
1113 void Mips64Assembler::SeleqzS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in SeleqzS() argument
1114 EmitFR(0x11, 0x10, ft, fs, fd, 0x14); in SeleqzS()
1117 void Mips64Assembler::SeleqzD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in SeleqzD() argument
1118 EmitFR(0x11, 0x11, ft, fs, fd, 0x14); in SeleqzD()
1121 void Mips64Assembler::SelnezS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in SelnezS() argument
1122 EmitFR(0x11, 0x10, ft, fs, fd, 0x17); in SelnezS()
1125 void Mips64Assembler::SelnezD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in SelnezD() argument
1126 EmitFR(0x11, 0x11, ft, fs, fd, 0x17); in SelnezD()
1145 void Mips64Assembler::MinS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in MinS() argument
1146 EmitFR(0x11, 0x10, ft, fs, fd, 0x1c); in MinS()
1149 void Mips64Assembler::MinD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in MinD() argument
1150 EmitFR(0x11, 0x11, ft, fs, fd, 0x1c); in MinD()
1153 void Mips64Assembler::MaxS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in MaxS() argument
1154 EmitFR(0x11, 0x10, ft, fs, fd, 0x1e); in MaxS()
1157 void Mips64Assembler::MaxD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in MaxD() argument
1158 EmitFR(0x11, 0x11, ft, fs, fd, 0x1e); in MaxD()
1161 void Mips64Assembler::CmpUnS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpUnS() argument
1162 EmitFR(0x11, 0x14, ft, fs, fd, 0x01); in CmpUnS()
1165 void Mips64Assembler::CmpEqS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpEqS() argument
1166 EmitFR(0x11, 0x14, ft, fs, fd, 0x02); in CmpEqS()
1169 void Mips64Assembler::CmpUeqS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpUeqS() argument
1170 EmitFR(0x11, 0x14, ft, fs, fd, 0x03); in CmpUeqS()
1173 void Mips64Assembler::CmpLtS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpLtS() argument
1174 EmitFR(0x11, 0x14, ft, fs, fd, 0x04); in CmpLtS()
1177 void Mips64Assembler::CmpUltS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpUltS() argument
1178 EmitFR(0x11, 0x14, ft, fs, fd, 0x05); in CmpUltS()
1181 void Mips64Assembler::CmpLeS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpLeS() argument
1182 EmitFR(0x11, 0x14, ft, fs, fd, 0x06); in CmpLeS()
1185 void Mips64Assembler::CmpUleS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpUleS() argument
1186 EmitFR(0x11, 0x14, ft, fs, fd, 0x07); in CmpUleS()
1189 void Mips64Assembler::CmpOrS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpOrS() argument
1190 EmitFR(0x11, 0x14, ft, fs, fd, 0x11); in CmpOrS()
1193 void Mips64Assembler::CmpUneS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpUneS() argument
1194 EmitFR(0x11, 0x14, ft, fs, fd, 0x12); in CmpUneS()
1197 void Mips64Assembler::CmpNeS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpNeS() argument
1198 EmitFR(0x11, 0x14, ft, fs, fd, 0x13); in CmpNeS()
1201 void Mips64Assembler::CmpUnD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpUnD() argument
1202 EmitFR(0x11, 0x15, ft, fs, fd, 0x01); in CmpUnD()
1205 void Mips64Assembler::CmpEqD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpEqD() argument
1206 EmitFR(0x11, 0x15, ft, fs, fd, 0x02); in CmpEqD()
1209 void Mips64Assembler::CmpUeqD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpUeqD() argument
1210 EmitFR(0x11, 0x15, ft, fs, fd, 0x03); in CmpUeqD()
1213 void Mips64Assembler::CmpLtD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpLtD() argument
1214 EmitFR(0x11, 0x15, ft, fs, fd, 0x04); in CmpLtD()
1217 void Mips64Assembler::CmpUltD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpUltD() argument
1218 EmitFR(0x11, 0x15, ft, fs, fd, 0x05); in CmpUltD()
1221 void Mips64Assembler::CmpLeD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpLeD() argument
1222 EmitFR(0x11, 0x15, ft, fs, fd, 0x06); in CmpLeD()
1225 void Mips64Assembler::CmpUleD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpUleD() argument
1226 EmitFR(0x11, 0x15, ft, fs, fd, 0x07); in CmpUleD()
1229 void Mips64Assembler::CmpOrD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpOrD() argument
1230 EmitFR(0x11, 0x15, ft, fs, fd, 0x11); in CmpOrD()
1233 void Mips64Assembler::CmpUneD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpUneD() argument
1234 EmitFR(0x11, 0x15, ft, fs, fd, 0x12); in CmpUneD()
1237 void Mips64Assembler::CmpNeD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { in CmpNeD() argument
1238 EmitFR(0x11, 0x15, ft, fs, fd, 0x13); in CmpNeD()
1289 void Mips64Assembler::Lwc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { in Lwc1() argument
1290 EmitI(0x31, rs, static_cast<GpuRegister>(ft), imm16); in Lwc1()
1293 void Mips64Assembler::Ldc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { in Ldc1() argument
1294 EmitI(0x35, rs, static_cast<GpuRegister>(ft), imm16); in Ldc1()
1297 void Mips64Assembler::Swc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { in Swc1() argument
1298 EmitI(0x39, rs, static_cast<GpuRegister>(ft), imm16); in Swc1()
1301 void Mips64Assembler::Sdc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { in Sdc1() argument
1302 EmitI(0x3d, rs, static_cast<GpuRegister>(ft), imm16); in Sdc1()
3328 void Mips64Assembler::Bc1eqz(FpuRegister ft, Mips64Label* label, bool is_bare) { in Bc1eqz() argument
3329 Bcond(label, /* is_r6= */ true, is_bare, kCondF, static_cast<GpuRegister>(ft), ZERO); in Bc1eqz()
3332 void Mips64Assembler::Bc1nez(FpuRegister ft, Mips64Label* label, bool is_bare) { in Bc1nez() argument
3333 Bcond(label, /* is_r6= */ true, is_bare, kCondT, static_cast<GpuRegister>(ft), ZERO); in Bc1nez()