Lines Matching refs:imm16
307 void Mips64Assembler::Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Addiu() argument
308 EmitI(0x9, rs, rt, imm16); in Addiu()
315 void Mips64Assembler::Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Daddiu() argument
316 EmitI(0x19, rs, rt, imm16); in Daddiu()
379 void Mips64Assembler::Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Andi() argument
380 EmitI(0xc, rs, rt, imm16); in Andi()
387 void Mips64Assembler::Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Ori() argument
388 EmitI(0xd, rs, rt, imm16); in Ori()
395 void Mips64Assembler::Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Xori() argument
396 EmitI(0xe, rs, rt, imm16); in Xori()
587 void Mips64Assembler::Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lb() argument
588 EmitI(0x20, rs, rt, imm16); in Lb()
591 void Mips64Assembler::Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lh() argument
592 EmitI(0x21, rs, rt, imm16); in Lh()
595 void Mips64Assembler::Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lw() argument
596 EmitI(0x23, rs, rt, imm16); in Lw()
599 void Mips64Assembler::Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Ld() argument
600 EmitI(0x37, rs, rt, imm16); in Ld()
603 void Mips64Assembler::Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lbu() argument
604 EmitI(0x24, rs, rt, imm16); in Lbu()
607 void Mips64Assembler::Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lhu() argument
608 EmitI(0x25, rs, rt, imm16); in Lhu()
611 void Mips64Assembler::Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lwu() argument
612 EmitI(0x27, rs, rt, imm16); in Lwu()
630 void Mips64Assembler::Lui(GpuRegister rt, uint16_t imm16) { in Lui() argument
631 EmitI(0xf, static_cast<GpuRegister>(0), rt, imm16); in Lui()
634 void Mips64Assembler::Aui(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Aui() argument
635 EmitI(0xf, rs, rt, imm16); in Aui()
638 void Mips64Assembler::Daui(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Daui() argument
640 EmitI(0x1d, rs, rt, imm16); in Daui()
643 void Mips64Assembler::Dahi(GpuRegister rs, uint16_t imm16) { in Dahi() argument
644 EmitI(1, rs, static_cast<GpuRegister>(6), imm16); in Dahi()
647 void Mips64Assembler::Dati(GpuRegister rs, uint16_t imm16) { in Dati() argument
648 EmitI(1, rs, static_cast<GpuRegister>(0x1e), imm16); in Dati()
656 void Mips64Assembler::Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sb() argument
657 EmitI(0x28, rs, rt, imm16); in Sb()
660 void Mips64Assembler::Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sh() argument
661 EmitI(0x29, rs, rt, imm16); in Sh()
664 void Mips64Assembler::Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sw() argument
665 EmitI(0x2b, rs, rt, imm16); in Sw()
668 void Mips64Assembler::Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sd() argument
669 EmitI(0x3f, rs, rt, imm16); in Sd()
680 void Mips64Assembler::Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Slti() argument
681 EmitI(0xa, rs, rt, imm16); in Slti()
684 void Mips64Assembler::Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sltiu() argument
685 EmitI(0xb, rs, rt, imm16); in Sltiu()
724 void Mips64Assembler::Auipc(GpuRegister rs, uint16_t imm16) { in Auipc() argument
725 EmitI(0x3B, rs, static_cast<GpuRegister>(0x1E), imm16); in Auipc()
741 void Mips64Assembler::Jic(GpuRegister rt, uint16_t imm16) { in Jic() argument
742 EmitI(0x36, static_cast<GpuRegister>(0), rt, imm16); in Jic()
745 void Mips64Assembler::Jialc(GpuRegister rt, uint16_t imm16) { in Jialc() argument
746 EmitI(0x3E, static_cast<GpuRegister>(0), rt, imm16); in Jialc()
749 void Mips64Assembler::Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bltc() argument
753 EmitI(0x17, rs, rt, imm16); in Bltc()
756 void Mips64Assembler::Bltzc(GpuRegister rt, uint16_t imm16) { in Bltzc() argument
758 EmitI(0x17, rt, rt, imm16); in Bltzc()
761 void Mips64Assembler::Bgtzc(GpuRegister rt, uint16_t imm16) { in Bgtzc() argument
763 EmitI(0x17, static_cast<GpuRegister>(0), rt, imm16); in Bgtzc()
766 void Mips64Assembler::Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bgec() argument
770 EmitI(0x16, rs, rt, imm16); in Bgec()
773 void Mips64Assembler::Bgezc(GpuRegister rt, uint16_t imm16) { in Bgezc() argument
775 EmitI(0x16, rt, rt, imm16); in Bgezc()
778 void Mips64Assembler::Blezc(GpuRegister rt, uint16_t imm16) { in Blezc() argument
780 EmitI(0x16, static_cast<GpuRegister>(0), rt, imm16); in Blezc()
783 void Mips64Assembler::Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bltuc() argument
787 EmitI(0x7, rs, rt, imm16); in Bltuc()
790 void Mips64Assembler::Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bgeuc() argument
794 EmitI(0x6, rs, rt, imm16); in Bgeuc()
797 void Mips64Assembler::Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Beqc() argument
801 EmitI(0x8, std::min(rs, rt), std::max(rs, rt), imm16); in Beqc()
804 void Mips64Assembler::Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bnec() argument
808 EmitI(0x18, std::min(rs, rt), std::max(rs, rt), imm16); in Bnec()
821 void Mips64Assembler::Bc1eqz(FpuRegister ft, uint16_t imm16) { in Bc1eqz() argument
822 EmitFI(0x11, 0x9, ft, imm16); in Bc1eqz()
825 void Mips64Assembler::Bc1nez(FpuRegister ft, uint16_t imm16) { in Bc1nez() argument
826 EmitFI(0x11, 0xD, ft, imm16); in Bc1nez()
829 void Mips64Assembler::Beq(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Beq() argument
830 EmitI(0x4, rs, rt, imm16); in Beq()
833 void Mips64Assembler::Bne(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bne() argument
834 EmitI(0x5, rs, rt, imm16); in Bne()
837 void Mips64Assembler::Beqz(GpuRegister rt, uint16_t imm16) { in Beqz() argument
838 Beq(rt, ZERO, imm16); in Beqz()
841 void Mips64Assembler::Bnez(GpuRegister rt, uint16_t imm16) { in Bnez() argument
842 Bne(rt, ZERO, imm16); in Bnez()
845 void Mips64Assembler::Bltz(GpuRegister rt, uint16_t imm16) { in Bltz() argument
846 EmitI(0x1, rt, static_cast<GpuRegister>(0), imm16); in Bltz()
849 void Mips64Assembler::Bgez(GpuRegister rt, uint16_t imm16) { in Bgez() argument
850 EmitI(0x1, rt, static_cast<GpuRegister>(0x1), imm16); in Bgez()
853 void Mips64Assembler::Blez(GpuRegister rt, uint16_t imm16) { in Blez() argument
854 EmitI(0x6, rt, static_cast<GpuRegister>(0), imm16); in Blez()
857 void Mips64Assembler::Bgtz(GpuRegister rt, uint16_t imm16) { in Bgtz() argument
858 EmitI(0x7, rt, static_cast<GpuRegister>(0), imm16); in Bgtz()
931 uint16_t imm16) { in EmitBcondR2() argument
935 Bltz(rs, imm16); in EmitBcondR2()
939 Bgez(rs, imm16); in EmitBcondR2()
943 Blez(rs, imm16); in EmitBcondR2()
947 Bgtz(rs, imm16); in EmitBcondR2()
950 Beq(rs, rt, imm16); in EmitBcondR2()
953 Bne(rs, rt, imm16); in EmitBcondR2()
957 Beqz(rs, imm16); in EmitBcondR2()
961 Bnez(rs, imm16); in EmitBcondR2()
1289 void Mips64Assembler::Lwc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { in Lwc1() argument
1290 EmitI(0x31, rs, static_cast<GpuRegister>(ft), imm16); in Lwc1()
1293 void Mips64Assembler::Ldc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { in Ldc1() argument
1294 EmitI(0x35, rs, static_cast<GpuRegister>(ft), imm16); in Ldc1()
1297 void Mips64Assembler::Swc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { in Swc1() argument
1298 EmitI(0x39, rs, static_cast<GpuRegister>(ft), imm16); in Swc1()
1301 void Mips64Assembler::Sdc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { in Sdc1() argument
1302 EmitI(0x3d, rs, static_cast<GpuRegister>(ft), imm16); in Sdc1()