Lines Matching refs:rt
99 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, in EmitR() argument
102 CHECK_NE(rt, kNoGpuRegister); in EmitR()
106 static_cast<uint32_t>(rt) << kRtShift | in EmitR()
126 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, in EmitRtd() argument
128 CHECK_NE(rt, kNoGpuRegister); in EmitRtd()
132 static_cast<uint32_t>(rt) << kRtShift | in EmitRtd()
139 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { in EmitI() argument
141 CHECK_NE(rt, kNoGpuRegister); in EmitI()
144 static_cast<uint32_t>(rt) << kRtShift | in EmitI()
303 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Addu() argument
304 EmitR(0, rs, rt, rd, 0, 0x21); in Addu()
307 void Mips64Assembler::Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Addiu() argument
308 EmitI(0x9, rs, rt, imm16); in Addiu()
311 void Mips64Assembler::Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Daddu() argument
312 EmitR(0, rs, rt, rd, 0, 0x2d); in Daddu()
315 void Mips64Assembler::Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Daddiu() argument
316 EmitI(0x19, rs, rt, imm16); in Daddiu()
319 void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Subu() argument
320 EmitR(0, rs, rt, rd, 0, 0x23); in Subu()
323 void Mips64Assembler::Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dsubu() argument
324 EmitR(0, rs, rt, rd, 0, 0x2f); in Dsubu()
327 void Mips64Assembler::MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MulR6() argument
328 EmitR(0, rs, rt, rd, 2, 0x18); in MulR6()
331 void Mips64Assembler::MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MuhR6() argument
332 EmitR(0, rs, rt, rd, 3, 0x18); in MuhR6()
335 void Mips64Assembler::DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in DivR6() argument
336 EmitR(0, rs, rt, rd, 2, 0x1a); in DivR6()
339 void Mips64Assembler::ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in ModR6() argument
340 EmitR(0, rs, rt, rd, 3, 0x1a); in ModR6()
343 void Mips64Assembler::DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in DivuR6() argument
344 EmitR(0, rs, rt, rd, 2, 0x1b); in DivuR6()
347 void Mips64Assembler::ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in ModuR6() argument
348 EmitR(0, rs, rt, rd, 3, 0x1b); in ModuR6()
351 void Mips64Assembler::Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmul() argument
352 EmitR(0, rs, rt, rd, 2, 0x1c); in Dmul()
355 void Mips64Assembler::Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmuh() argument
356 EmitR(0, rs, rt, rd, 3, 0x1c); in Dmuh()
359 void Mips64Assembler::Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Ddiv() argument
360 EmitR(0, rs, rt, rd, 2, 0x1e); in Ddiv()
363 void Mips64Assembler::Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmod() argument
364 EmitR(0, rs, rt, rd, 3, 0x1e); in Dmod()
367 void Mips64Assembler::Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Ddivu() argument
368 EmitR(0, rs, rt, rd, 2, 0x1f); in Ddivu()
371 void Mips64Assembler::Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmodu() argument
372 EmitR(0, rs, rt, rd, 3, 0x1f); in Dmodu()
375 void Mips64Assembler::And(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in And() argument
376 EmitR(0, rs, rt, rd, 0, 0x24); in And()
379 void Mips64Assembler::Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Andi() argument
380 EmitI(0xc, rs, rt, imm16); in Andi()
383 void Mips64Assembler::Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Or() argument
384 EmitR(0, rs, rt, rd, 0, 0x25); in Or()
387 void Mips64Assembler::Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Ori() argument
388 EmitI(0xd, rs, rt, imm16); in Ori()
391 void Mips64Assembler::Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Xor() argument
392 EmitR(0, rs, rt, rd, 0, 0x26); in Xor()
395 void Mips64Assembler::Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Xori() argument
396 EmitI(0xe, rs, rt, imm16); in Xori()
399 void Mips64Assembler::Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Nor() argument
400 EmitR(0, rs, rt, rd, 0, 0x27); in Nor()
403 void Mips64Assembler::Bitswap(GpuRegister rd, GpuRegister rt) { in Bitswap() argument
404 EmitRtd(0x1f, rt, rd, 0x0, 0x20); in Bitswap()
407 void Mips64Assembler::Dbitswap(GpuRegister rd, GpuRegister rt) { in Dbitswap() argument
408 EmitRtd(0x1f, rt, rd, 0x0, 0x24); in Dbitswap()
411 void Mips64Assembler::Seb(GpuRegister rd, GpuRegister rt) { in Seb() argument
412 EmitR(0x1f, static_cast<GpuRegister>(0), rt, rd, 0x10, 0x20); in Seb()
415 void Mips64Assembler::Seh(GpuRegister rd, GpuRegister rt) { in Seh() argument
416 EmitR(0x1f, static_cast<GpuRegister>(0), rt, rd, 0x18, 0x20); in Seh()
419 void Mips64Assembler::Dsbh(GpuRegister rd, GpuRegister rt) { in Dsbh() argument
420 EmitRtd(0x1f, rt, rd, 0x2, 0x24); in Dsbh()
423 void Mips64Assembler::Dshd(GpuRegister rd, GpuRegister rt) { in Dshd() argument
424 EmitRtd(0x1f, rt, rd, 0x5, 0x24); in Dshd()
427 void Mips64Assembler::Dext(GpuRegister rt, GpuRegister rs, int pos, int size) { in Dext() argument
430 EmitR(0x1f, rs, rt, static_cast<GpuRegister>(size - 1), pos, 0x3); in Dext()
433 void Mips64Assembler::Ins(GpuRegister rd, GpuRegister rt, int pos, int size) { in Ins() argument
437 EmitR(0x1f, rt, rd, static_cast<GpuRegister>(pos + size - 1), pos, 0x04); in Ins()
440 void Mips64Assembler::Dinsm(GpuRegister rt, GpuRegister rs, int pos, int size) { in Dinsm() argument
444 EmitR(0x1f, rs, rt, static_cast<GpuRegister>(pos + size - 33), pos, 0x5); in Dinsm()
447 void Mips64Assembler::Dinsu(GpuRegister rt, GpuRegister rs, int pos, int size) { in Dinsu() argument
451 EmitR(0x1f, rs, rt, static_cast<GpuRegister>(pos + size - 33), pos - 32, 0x6); in Dinsu()
454 void Mips64Assembler::Dins(GpuRegister rt, GpuRegister rs, int pos, int size) { in Dins() argument
458 EmitR(0x1f, rs, rt, static_cast<GpuRegister>(pos + size - 1), pos, 0x7); in Dins()
461 void Mips64Assembler::DblIns(GpuRegister rt, GpuRegister rs, int pos, int size) { in DblIns() argument
463 Dinsu(rt, rs, pos, size); in DblIns()
465 Dinsm(rt, rs, pos, size); in DblIns()
467 Dins(rt, rs, pos, size); in DblIns()
471 void Mips64Assembler::Lsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne) { in Lsa() argument
474 EmitR(0x0, rs, rt, rd, sa, 0x05); in Lsa()
477 void Mips64Assembler::Dlsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne) { in Dlsa() argument
480 EmitR(0x0, rs, rt, rd, sa, 0x15); in Dlsa()
483 void Mips64Assembler::Wsbh(GpuRegister rd, GpuRegister rt) { in Wsbh() argument
484 EmitRtd(0x1f, rt, rd, 2, 0x20); in Wsbh()
487 void Mips64Assembler::Sc(GpuRegister rt, GpuRegister base, int16_t imm9) { in Sc() argument
489 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x26); in Sc()
492 void Mips64Assembler::Scd(GpuRegister rt, GpuRegister base, int16_t imm9) { in Scd() argument
494 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x27); in Scd()
497 void Mips64Assembler::Ll(GpuRegister rt, GpuRegister base, int16_t imm9) { in Ll() argument
499 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x36); in Ll()
502 void Mips64Assembler::Lld(GpuRegister rt, GpuRegister base, int16_t imm9) { in Lld() argument
504 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x37); in Lld()
507 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) { in Sll() argument
508 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00); in Sll()
511 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) { in Srl() argument
512 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x02); in Srl()
515 void Mips64Assembler::Rotr(GpuRegister rd, GpuRegister rt, int shamt) { in Rotr() argument
516 EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x02); in Rotr()
519 void Mips64Assembler::Sra(GpuRegister rd, GpuRegister rt, int shamt) { in Sra() argument
520 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x03); in Sra()
523 void Mips64Assembler::Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Sllv() argument
524 EmitR(0, rs, rt, rd, 0, 0x04); in Sllv()
527 void Mips64Assembler::Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Rotrv() argument
528 EmitR(0, rs, rt, rd, 1, 0x06); in Rotrv()
531 void Mips64Assembler::Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Srlv() argument
532 EmitR(0, rs, rt, rd, 0, 0x06); in Srlv()
535 void Mips64Assembler::Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Srav() argument
536 EmitR(0, rs, rt, rd, 0, 0x07); in Srav()
539 void Mips64Assembler::Dsll(GpuRegister rd, GpuRegister rt, int shamt) { in Dsll() argument
540 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x38); in Dsll()
543 void Mips64Assembler::Dsrl(GpuRegister rd, GpuRegister rt, int shamt) { in Dsrl() argument
544 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3a); in Dsrl()
547 void Mips64Assembler::Drotr(GpuRegister rd, GpuRegister rt, int shamt) { in Drotr() argument
548 EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x3a); in Drotr()
551 void Mips64Assembler::Dsra(GpuRegister rd, GpuRegister rt, int shamt) { in Dsra() argument
552 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3b); in Dsra()
555 void Mips64Assembler::Dsll32(GpuRegister rd, GpuRegister rt, int shamt) { in Dsll32() argument
556 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3c); in Dsll32()
559 void Mips64Assembler::Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) { in Dsrl32() argument
560 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3e); in Dsrl32()
563 void Mips64Assembler::Drotr32(GpuRegister rd, GpuRegister rt, int shamt) { in Drotr32() argument
564 EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x3e); in Drotr32()
567 void Mips64Assembler::Dsra32(GpuRegister rd, GpuRegister rt, int shamt) { in Dsra32() argument
568 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3f); in Dsra32()
571 void Mips64Assembler::Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Dsllv() argument
572 EmitR(0, rs, rt, rd, 0, 0x14); in Dsllv()
575 void Mips64Assembler::Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Dsrlv() argument
576 EmitR(0, rs, rt, rd, 0, 0x16); in Dsrlv()
579 void Mips64Assembler::Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Drotrv() argument
580 EmitR(0, rs, rt, rd, 1, 0x16); in Drotrv()
583 void Mips64Assembler::Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Dsrav() argument
584 EmitR(0, rs, rt, rd, 0, 0x17); in Dsrav()
587 void Mips64Assembler::Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lb() argument
588 EmitI(0x20, rs, rt, imm16); in Lb()
591 void Mips64Assembler::Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lh() argument
592 EmitI(0x21, rs, rt, imm16); in Lh()
595 void Mips64Assembler::Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lw() argument
596 EmitI(0x23, rs, rt, imm16); in Lw()
599 void Mips64Assembler::Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Ld() argument
600 EmitI(0x37, rs, rt, imm16); in Ld()
603 void Mips64Assembler::Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lbu() argument
604 EmitI(0x24, rs, rt, imm16); in Lbu()
607 void Mips64Assembler::Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lhu() argument
608 EmitI(0x25, rs, rt, imm16); in Lhu()
611 void Mips64Assembler::Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lwu() argument
612 EmitI(0x27, rs, rt, imm16); in Lwu()
630 void Mips64Assembler::Lui(GpuRegister rt, uint16_t imm16) { in Lui() argument
631 EmitI(0xf, static_cast<GpuRegister>(0), rt, imm16); in Lui()
634 void Mips64Assembler::Aui(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Aui() argument
635 EmitI(0xf, rs, rt, imm16); in Aui()
638 void Mips64Assembler::Daui(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Daui() argument
640 EmitI(0x1d, rs, rt, imm16); in Daui()
656 void Mips64Assembler::Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sb() argument
657 EmitI(0x28, rs, rt, imm16); in Sb()
660 void Mips64Assembler::Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sh() argument
661 EmitI(0x29, rs, rt, imm16); in Sh()
664 void Mips64Assembler::Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sw() argument
665 EmitI(0x2b, rs, rt, imm16); in Sw()
668 void Mips64Assembler::Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sd() argument
669 EmitI(0x3f, rs, rt, imm16); in Sd()
672 void Mips64Assembler::Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Slt() argument
673 EmitR(0, rs, rt, rd, 0, 0x2a); in Slt()
676 void Mips64Assembler::Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Sltu() argument
677 EmitR(0, rs, rt, rd, 0, 0x2b); in Sltu()
680 void Mips64Assembler::Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Slti() argument
681 EmitI(0xa, rs, rt, imm16); in Slti()
684 void Mips64Assembler::Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sltiu() argument
685 EmitI(0xb, rs, rt, imm16); in Sltiu()
688 void Mips64Assembler::Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Seleqz() argument
689 EmitR(0, rs, rt, rd, 0, 0x35); in Seleqz()
692 void Mips64Assembler::Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Selnez() argument
693 EmitR(0, rs, rt, rd, 0, 0x37); in Selnez()
741 void Mips64Assembler::Jic(GpuRegister rt, uint16_t imm16) { in Jic() argument
742 EmitI(0x36, static_cast<GpuRegister>(0), rt, imm16); in Jic()
745 void Mips64Assembler::Jialc(GpuRegister rt, uint16_t imm16) { in Jialc() argument
746 EmitI(0x3E, static_cast<GpuRegister>(0), rt, imm16); in Jialc()
749 void Mips64Assembler::Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bltc() argument
751 CHECK_NE(rt, ZERO); in Bltc()
752 CHECK_NE(rs, rt); in Bltc()
753 EmitI(0x17, rs, rt, imm16); in Bltc()
756 void Mips64Assembler::Bltzc(GpuRegister rt, uint16_t imm16) { in Bltzc() argument
757 CHECK_NE(rt, ZERO); in Bltzc()
758 EmitI(0x17, rt, rt, imm16); in Bltzc()
761 void Mips64Assembler::Bgtzc(GpuRegister rt, uint16_t imm16) { in Bgtzc() argument
762 CHECK_NE(rt, ZERO); in Bgtzc()
763 EmitI(0x17, static_cast<GpuRegister>(0), rt, imm16); in Bgtzc()
766 void Mips64Assembler::Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bgec() argument
768 CHECK_NE(rt, ZERO); in Bgec()
769 CHECK_NE(rs, rt); in Bgec()
770 EmitI(0x16, rs, rt, imm16); in Bgec()
773 void Mips64Assembler::Bgezc(GpuRegister rt, uint16_t imm16) { in Bgezc() argument
774 CHECK_NE(rt, ZERO); in Bgezc()
775 EmitI(0x16, rt, rt, imm16); in Bgezc()
778 void Mips64Assembler::Blezc(GpuRegister rt, uint16_t imm16) { in Blezc() argument
779 CHECK_NE(rt, ZERO); in Blezc()
780 EmitI(0x16, static_cast<GpuRegister>(0), rt, imm16); in Blezc()
783 void Mips64Assembler::Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bltuc() argument
785 CHECK_NE(rt, ZERO); in Bltuc()
786 CHECK_NE(rs, rt); in Bltuc()
787 EmitI(0x7, rs, rt, imm16); in Bltuc()
790 void Mips64Assembler::Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bgeuc() argument
792 CHECK_NE(rt, ZERO); in Bgeuc()
793 CHECK_NE(rs, rt); in Bgeuc()
794 EmitI(0x6, rs, rt, imm16); in Bgeuc()
797 void Mips64Assembler::Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Beqc() argument
799 CHECK_NE(rt, ZERO); in Beqc()
800 CHECK_NE(rs, rt); in Beqc()
801 EmitI(0x8, std::min(rs, rt), std::max(rs, rt), imm16); in Beqc()
804 void Mips64Assembler::Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bnec() argument
806 CHECK_NE(rt, ZERO); in Bnec()
807 CHECK_NE(rs, rt); in Bnec()
808 EmitI(0x18, std::min(rs, rt), std::max(rs, rt), imm16); in Bnec()
829 void Mips64Assembler::Beq(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Beq() argument
830 EmitI(0x4, rs, rt, imm16); in Beq()
833 void Mips64Assembler::Bne(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bne() argument
834 EmitI(0x5, rs, rt, imm16); in Bne()
837 void Mips64Assembler::Beqz(GpuRegister rt, uint16_t imm16) { in Beqz() argument
838 Beq(rt, ZERO, imm16); in Beqz()
841 void Mips64Assembler::Bnez(GpuRegister rt, uint16_t imm16) { in Bnez() argument
842 Bne(rt, ZERO, imm16); in Bnez()
845 void Mips64Assembler::Bltz(GpuRegister rt, uint16_t imm16) { in Bltz() argument
846 EmitI(0x1, rt, static_cast<GpuRegister>(0), imm16); in Bltz()
849 void Mips64Assembler::Bgez(GpuRegister rt, uint16_t imm16) { in Bgez() argument
850 EmitI(0x1, rt, static_cast<GpuRegister>(0x1), imm16); in Bgez()
853 void Mips64Assembler::Blez(GpuRegister rt, uint16_t imm16) { in Blez() argument
854 EmitI(0x6, rt, static_cast<GpuRegister>(0), imm16); in Blez()
857 void Mips64Assembler::Bgtz(GpuRegister rt, uint16_t imm16) { in Bgtz() argument
858 EmitI(0x7, rt, static_cast<GpuRegister>(0), imm16); in Bgtz()
863 GpuRegister rt, in EmitBcondR6() argument
867 Bltc(rs, rt, imm16_21); in EmitBcondR6()
870 Bgec(rs, rt, imm16_21); in EmitBcondR6()
873 Bgec(rt, rs, imm16_21); in EmitBcondR6()
876 Bltc(rt, rs, imm16_21); in EmitBcondR6()
879 CHECK_EQ(rt, ZERO); in EmitBcondR6()
883 CHECK_EQ(rt, ZERO); in EmitBcondR6()
887 CHECK_EQ(rt, ZERO); in EmitBcondR6()
891 CHECK_EQ(rt, ZERO); in EmitBcondR6()
895 Beqc(rs, rt, imm16_21); in EmitBcondR6()
898 Bnec(rs, rt, imm16_21); in EmitBcondR6()
901 CHECK_EQ(rt, ZERO); in EmitBcondR6()
905 CHECK_EQ(rt, ZERO); in EmitBcondR6()
909 Bltuc(rs, rt, imm16_21); in EmitBcondR6()
912 Bgeuc(rs, rt, imm16_21); in EmitBcondR6()
915 CHECK_EQ(rt, ZERO); in EmitBcondR6()
919 CHECK_EQ(rt, ZERO); in EmitBcondR6()
930 GpuRegister rt, in EmitBcondR2() argument
934 CHECK_EQ(rt, ZERO); in EmitBcondR2()
938 CHECK_EQ(rt, ZERO); in EmitBcondR2()
942 CHECK_EQ(rt, ZERO); in EmitBcondR2()
946 CHECK_EQ(rt, ZERO); in EmitBcondR2()
950 Beq(rs, rt, imm16); in EmitBcondR2()
953 Bne(rs, rt, imm16); in EmitBcondR2()
956 CHECK_EQ(rt, ZERO); in EmitBcondR2()
960 CHECK_EQ(rt, ZERO); in EmitBcondR2()
1265 void Mips64Assembler::Mfc1(GpuRegister rt, FpuRegister fs) { in Mfc1() argument
1266 EmitFR(0x11, 0x00, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0); in Mfc1()
1269 void Mips64Assembler::Mfhc1(GpuRegister rt, FpuRegister fs) { in Mfhc1() argument
1270 EmitFR(0x11, 0x03, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0); in Mfhc1()
1273 void Mips64Assembler::Mtc1(GpuRegister rt, FpuRegister fs) { in Mtc1() argument
1274 EmitFR(0x11, 0x04, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0); in Mtc1()
1277 void Mips64Assembler::Mthc1(GpuRegister rt, FpuRegister fs) { in Mthc1() argument
1278 EmitFR(0x11, 0x07, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0); in Mthc1()
1281 void Mips64Assembler::Dmfc1(GpuRegister rt, FpuRegister fs) { in Dmfc1() argument
1282 EmitFR(0x11, 0x01, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0); in Dmfc1()
1285 void Mips64Assembler::Dmtc1(GpuRegister rt, FpuRegister fs) { in Dmtc1() argument
1286 EmitFR(0x11, 0x05, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0); in Dmtc1()
2325 void Mips64Assembler::Addiu32(GpuRegister rt, GpuRegister rs, int32_t value) { in Addiu32() argument
2327 Addiu(rt, rs, value); in Addiu32()
2332 Aui(rt, rs, high); in Addiu32()
2334 Addiu(rt, rt, low); in Addiu32()
2340 void Mips64Assembler::Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp) { in Daddiu64() argument
2343 Daddiu(rt, rs, value); in Daddiu64()
2346 Daddu(rt, rs, rtmp); in Daddiu64()
3280 void Mips64Assembler::Bltc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Bltc() argument
3281 Bcond(label, /* is_r6= */ true, is_bare, kCondLT, rs, rt); in Bltc()
3284 void Mips64Assembler::Bltzc(GpuRegister rt, Mips64Label* label, bool is_bare) { in Bltzc() argument
3285 Bcond(label, /* is_r6= */ true, is_bare, kCondLTZ, rt); in Bltzc()
3288 void Mips64Assembler::Bgtzc(GpuRegister rt, Mips64Label* label, bool is_bare) { in Bgtzc() argument
3289 Bcond(label, /* is_r6= */ true, is_bare, kCondGTZ, rt); in Bgtzc()
3292 void Mips64Assembler::Bgec(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Bgec() argument
3293 Bcond(label, /* is_r6= */ true, is_bare, kCondGE, rs, rt); in Bgec()
3296 void Mips64Assembler::Bgezc(GpuRegister rt, Mips64Label* label, bool is_bare) { in Bgezc() argument
3297 Bcond(label, /* is_r6= */ true, is_bare, kCondGEZ, rt); in Bgezc()
3300 void Mips64Assembler::Blezc(GpuRegister rt, Mips64Label* label, bool is_bare) { in Blezc() argument
3301 Bcond(label, /* is_r6= */ true, is_bare, kCondLEZ, rt); in Blezc()
3304 void Mips64Assembler::Bltuc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Bltuc() argument
3305 Bcond(label, /* is_r6= */ true, is_bare, kCondLTU, rs, rt); in Bltuc()
3308 void Mips64Assembler::Bgeuc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Bgeuc() argument
3309 Bcond(label, /* is_r6= */ true, is_bare, kCondGEU, rs, rt); in Bgeuc()
3312 void Mips64Assembler::Beqc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Beqc() argument
3313 Bcond(label, /* is_r6= */ true, is_bare, kCondEQ, rs, rt); in Beqc()
3316 void Mips64Assembler::Bnec(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Bnec() argument
3317 Bcond(label, /* is_r6= */ true, is_bare, kCondNE, rs, rt); in Bnec()
3336 void Mips64Assembler::Bltz(GpuRegister rt, Mips64Label* label, bool is_bare) { in Bltz() argument
3338 Bcond(label, /* is_r6= */ false, is_bare, kCondLTZ, rt); in Bltz()
3341 void Mips64Assembler::Bgtz(GpuRegister rt, Mips64Label* label, bool is_bare) { in Bgtz() argument
3343 Bcond(label, /* is_r6= */ false, is_bare, kCondGTZ, rt); in Bgtz()
3346 void Mips64Assembler::Bgez(GpuRegister rt, Mips64Label* label, bool is_bare) { in Bgez() argument
3348 Bcond(label, /* is_r6= */ false, is_bare, kCondGEZ, rt); in Bgez()
3351 void Mips64Assembler::Blez(GpuRegister rt, Mips64Label* label, bool is_bare) { in Blez() argument
3353 Bcond(label, /* is_r6= */ false, is_bare, kCondLEZ, rt); in Blez()
3356 void Mips64Assembler::Beq(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Beq() argument
3358 Bcond(label, /* is_r6= */ false, is_bare, kCondEQ, rs, rt); in Beq()
3361 void Mips64Assembler::Bne(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Bne() argument
3363 Bcond(label, /* is_r6= */ false, is_bare, kCondNE, rs, rt); in Bne()