Lines Matching refs:scratch
3737 Mips64ManagedRegister scratch = mscratch.AsMips64(); in StoreImmediateToFrame() local
3738 CHECK(scratch.IsGpuRegister()) << scratch; in StoreImmediateToFrame()
3739 LoadConst32(scratch.AsGpuRegister(), imm); in StoreImmediateToFrame()
3740 StoreToOffset(kStoreWord, scratch.AsGpuRegister(), SP, dest.Int32Value()); in StoreImmediateToFrame()
3746 Mips64ManagedRegister scratch = mscratch.AsMips64(); in StoreStackOffsetToThread() local
3747 CHECK(scratch.IsGpuRegister()) << scratch; in StoreStackOffsetToThread()
3748 Daddiu64(scratch.AsGpuRegister(), SP, fr_offs.Int32Value()); in StoreStackOffsetToThread()
3749 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value()); in StoreStackOffsetToThread()
3759 Mips64ManagedRegister scratch = mscratch.AsMips64(); in StoreSpanning() local
3761 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), SP, in_off.Int32Value()); in StoreSpanning()
3762 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, dest.Int32Value() + 8); in StoreSpanning()
3836 Mips64ManagedRegister scratch = mscratch.AsMips64(); in CopyRef() local
3837 CHECK(scratch.IsGpuRegister()) << scratch; in CopyRef()
3838 LoadFromOffset(kLoadWord, scratch.AsGpuRegister(), SP, src.Int32Value()); in CopyRef()
3839 StoreToOffset(kStoreWord, scratch.AsGpuRegister(), SP, dest.Int32Value()); in CopyRef()
3845 Mips64ManagedRegister scratch = mscratch.AsMips64(); in CopyRawPtrFromThread() local
3846 CHECK(scratch.IsGpuRegister()) << scratch; in CopyRawPtrFromThread()
3847 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value()); in CopyRawPtrFromThread()
3848 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, fr_offs.Int32Value()); in CopyRawPtrFromThread()
3854 Mips64ManagedRegister scratch = mscratch.AsMips64(); in CopyRawPtrToThread() local
3855 CHECK(scratch.IsGpuRegister()) << scratch; in CopyRawPtrToThread()
3856 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), in CopyRawPtrToThread()
3858 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), in CopyRawPtrToThread()
3864 Mips64ManagedRegister scratch = mscratch.AsMips64(); in Copy() local
3865 CHECK(scratch.IsGpuRegister()) << scratch; in Copy()
3868 LoadFromOffset(kLoadWord, scratch.AsGpuRegister(), SP, src.Int32Value()); in Copy()
3869 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, dest.Int32Value()); in Copy()
3871 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), SP, src.Int32Value()); in Copy()
3872 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, dest.Int32Value()); in Copy()
3880 GpuRegister scratch = mscratch.AsMips64().AsGpuRegister(); in Copy() local
3883 LoadFromOffset(kLoadWord, scratch, src_base.AsMips64().AsGpuRegister(), in Copy()
3885 StoreToOffset(kStoreDoubleword, scratch, SP, dest.Int32Value()); in Copy()
3887 LoadFromOffset(kLoadDoubleword, scratch, src_base.AsMips64().AsGpuRegister(), in Copy()
3889 StoreToOffset(kStoreDoubleword, scratch, SP, dest.Int32Value()); in Copy()
3897 GpuRegister scratch = mscratch.AsMips64().AsGpuRegister(); in Copy() local
3900 LoadFromOffset(kLoadWord, scratch, SP, src.Int32Value()); in Copy()
3901 StoreToOffset(kStoreDoubleword, scratch, dest_base.AsMips64().AsGpuRegister(), in Copy()
3904 LoadFromOffset(kLoadDoubleword, scratch, SP, src.Int32Value()); in Copy()
3905 StoreToOffset(kStoreDoubleword, scratch, dest_base.AsMips64().AsGpuRegister(), in Copy()
3923 GpuRegister scratch = mscratch.AsMips64().AsGpuRegister(); in Copy() local
3926 LoadFromOffset(kLoadWord, scratch, src.AsMips64().AsGpuRegister(), src_offset.Int32Value()); in Copy()
3927 …StoreToOffset(kStoreDoubleword, scratch, dest.AsMips64().AsGpuRegister(), dest_offset.Int32Value()… in Copy()
3929 LoadFromOffset(kLoadDoubleword, scratch, src.AsMips64().AsGpuRegister(), in Copy()
3931 StoreToOffset(kStoreDoubleword, scratch, dest.AsMips64().AsGpuRegister(), in Copy()
3985 Mips64ManagedRegister scratch = mscratch.AsMips64(); in CreateHandleScopeEntry() local
3986 CHECK(scratch.IsGpuRegister()) << scratch; in CreateHandleScopeEntry()
3989 LoadFromOffset(kLoadUnsignedWord, scratch.AsGpuRegister(), SP, in CreateHandleScopeEntry()
3994 Beqzc(scratch.AsGpuRegister(), &null_arg); in CreateHandleScopeEntry()
3995 Daddiu64(scratch.AsGpuRegister(), SP, handle_scope_offset.Int32Value()); in CreateHandleScopeEntry()
3998 Daddiu64(scratch.AsGpuRegister(), SP, handle_scope_offset.Int32Value()); in CreateHandleScopeEntry()
4000 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, out_off.Int32Value()); in CreateHandleScopeEntry()
4032 Mips64ManagedRegister scratch = mscratch.AsMips64(); in Call() local
4034 CHECK(scratch.IsGpuRegister()) << scratch; in Call()
4035 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), in Call()
4037 Jalr(scratch.AsGpuRegister()); in Call()
4043 Mips64ManagedRegister scratch = mscratch.AsMips64(); in Call() local
4044 CHECK(scratch.IsGpuRegister()) << scratch; in Call()
4046 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), in Call()
4048 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), in Call()
4049 scratch.AsGpuRegister(), offset.Int32Value()); in Call()
4050 Jalr(scratch.AsGpuRegister()); in Call()
4070 Mips64ManagedRegister scratch = mscratch.AsMips64(); in ExceptionPoll() local
4071 exception_blocks_.emplace_back(scratch, stack_adjust); in ExceptionPoll()
4073 scratch.AsGpuRegister(), in ExceptionPoll()
4076 Bnezc(scratch.AsGpuRegister(), exception_blocks_.back().Entry()); in ExceptionPoll()