assembler_mips64.h - OpenGrok cross reference for /art/compiler/utils/mips64/assembler

Lines Matching refs:rt
446   void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
447   void Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
448   void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
449   void Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);  // MIPS64
450   void Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
451   void Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
453   void MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
454   void MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
455   void DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
456   void ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
457   void DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
458   void ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
459   void Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
460   void Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
461   void Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
462   void Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
463   void Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
464   void Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
466   void And(GpuRegister rd, GpuRegister rs, GpuRegister rt);
467   void Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16);
468   void Or(GpuRegister rd, GpuRegister rs, GpuRegister rt);
469   void Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16);
470   void Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt);
471   void Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16);
472   void Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt);
474   void Bitswap(GpuRegister rd, GpuRegister rt);
475   void Dbitswap(GpuRegister rd, GpuRegister rt);  // MIPS64
476   void Seb(GpuRegister rd, GpuRegister rt);
477   void Seh(GpuRegister rd, GpuRegister rt);
478   void Dsbh(GpuRegister rd, GpuRegister rt);  // MIPS64
479   void Dshd(GpuRegister rd, GpuRegister rt);  // MIPS64
480   void Dext(GpuRegister rs, GpuRegister rt, int pos, int size);  // MIPS64
481   void Ins(GpuRegister rt, GpuRegister rs, int pos, int size);
482   void Dins(GpuRegister rt, GpuRegister rs, int pos, int size);  // MIPS64
483   void Dinsm(GpuRegister rt, GpuRegister rs, int pos, int size);  // MIPS64
484   void Dinsu(GpuRegister rt, GpuRegister rs, int pos, int size);  // MIPS64
485   void DblIns(GpuRegister rt, GpuRegister rs, int pos, int size);  // MIPS64
486   void Lsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne);
487   void Dlsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne);  // MIPS64
488   void Wsbh(GpuRegister rd, GpuRegister rt);
489   void Sc(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
490   void Scd(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);  // MIPS64
491   void Ll(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
492   void Lld(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);  // MIPS64
494   void Sll(GpuRegister rd, GpuRegister rt, int shamt);
495   void Srl(GpuRegister rd, GpuRegister rt, int shamt);
496   void Rotr(GpuRegister rd, GpuRegister rt, int shamt);
497   void Sra(GpuRegister rd, GpuRegister rt, int shamt);
498   void Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
499   void Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
500   void Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
501   void Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs);
502   void Dsll(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
503   void Dsrl(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
504   void Drotr(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
505   void Dsra(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
506   void Dsll32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
507   void Dsrl32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
508   void Drotr32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
509   void Dsra32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
510   void Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
511   void Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
512   void Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
513   void Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
515   void Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16);
516   void Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16);
517   void Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16);
518   void Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16);  // MIPS64
519   void Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
520   void Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
521   void Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16);  // MIPS64
525   void Lui(GpuRegister rt, uint16_t imm16);
526   void Aui(GpuRegister rt, GpuRegister rs, uint16_t imm16);
527   void Daui(GpuRegister rt, GpuRegister rs, uint16_t imm16);  // MIPS64
532   void Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16);
533   void Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16);
534   void Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16);
535   void Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16);  // MIPS64
537   void Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt);
538   void Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
539   void Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16);
540   void Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
541   void Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt);
542   void Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt);
555   void Jic(GpuRegister rt, uint16_t imm16);
556   void Jialc(GpuRegister rt, uint16_t imm16);
557   void Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16);
558   void Bltzc(GpuRegister rt, uint16_t imm16);
559   void Bgtzc(GpuRegister rt, uint16_t imm16);
560   void Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16);
561   void Bgezc(GpuRegister rt, uint16_t imm16);
562   void Blezc(GpuRegister rt, uint16_t imm16);
563   void Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16);
564   void Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16);
565   void Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16);
566   void Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16);
571   void Beq(GpuRegister rs, GpuRegister rt, uint16_t imm16);  // R2
572   void Bne(GpuRegister rs, GpuRegister rt, uint16_t imm16);  // R2
573   void Beqz(GpuRegister rt, uint16_t imm16);  // R2
574   void Bnez(GpuRegister rt, uint16_t imm16);  // R2
575   void Bltz(GpuRegister rt, uint16_t imm16);  // R2
576   void Bgez(GpuRegister rt, uint16_t imm16);  // R2
577   void Blez(GpuRegister rt, uint16_t imm16);  // R2
578   void Bgtz(GpuRegister rt, uint16_t imm16);  // R2
654   void Mfc1(GpuRegister rt, FpuRegister fs);
655   void Mfhc1(GpuRegister rt, FpuRegister fs);
656   void Mtc1(GpuRegister rt, FpuRegister fs);
657   void Mthc1(GpuRegister rt, FpuRegister fs);
658   void Dmfc1(GpuRegister rt, FpuRegister fs);  // MIPS64
659   void Dmtc1(GpuRegister rt, FpuRegister fs);  // MIPS64
882   void Addiu32(GpuRegister rt, GpuRegister rs, int32_t value);
883   void Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp = AT);  // MIPS64
1008   void Bltc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare = false);
1009   void Bltzc(GpuRegister rt, Mips64Label* label, bool is_bare = false);
1010   void Bgtzc(GpuRegister rt, Mips64Label* label, bool is_bare = false);
1011   void Bgec(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare = false);
1012   void Bgezc(GpuRegister rt, Mips64Label* label, bool is_bare = false);
1013   void Blezc(GpuRegister rt, Mips64Label* label, bool is_bare = false);
1014   void Bltuc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare = false);
1015   void Bgeuc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare = false);
1016   void Beqc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare = false);
1017   void Bnec(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare = false);
1027   void Bltz(GpuRegister rt, Mips64Label* label, bool is_bare = false);  // R2
1028   void Bgtz(GpuRegister rt, Mips64Label* label, bool is_bare = false);  // R2
1029   void Bgez(GpuRegister rt, Mips64Label* label, bool is_bare = false);  // R2
1030   void Blez(GpuRegister rt, Mips64Label* label, bool is_bare = false);  // R2
1031   void Beq(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare = false);  // R2
1032   void Bne(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare = false);  // R2
1654   void EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, int shamt, int funct);
1656   void EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, int shamt, int funct);
1657   void EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm);
1661   void EmitFI(int opcode, int fmt, FpuRegister rt, uint16_t imm);
1662   void EmitBcondR6(BranchCondition cond, GpuRegister rs, GpuRegister rt, uint32_t imm16_21);
1663   void EmitBcondR2(BranchCondition cond, GpuRegister rs, GpuRegister rt, uint16_t imm16);