Lines Matching refs:imm
199 void X86_64Assembler::pushq(const Immediate& imm) { in pushq() argument
201 CHECK(imm.is_int32()); // pushq only supports 32b immediate. in pushq()
202 if (imm.is_int8()) { in pushq()
204 EmitUint8(imm.value() & 0xFF); in pushq()
207 EmitImmediate(imm); in pushq()
227 void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) { in movq() argument
229 if (imm.is_int32()) { in movq()
234 EmitInt32(static_cast<int32_t>(imm.value())); in movq()
238 EmitInt64(imm.value()); in movq()
243 void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) { in movl() argument
244 CHECK(imm.is_int32()); in movl()
248 EmitImmediate(imm); in movl()
252 void X86_64Assembler::movq(const Address& dst, const Immediate& imm) { in movq() argument
253 CHECK(imm.is_int32()); in movq()
258 EmitImmediate(imm); in movq()
310 void X86_64Assembler::movl(const Address& dst, const Immediate& imm) { in movl() argument
315 EmitImmediate(imm); in movl()
413 void X86_64Assembler::movb(const Address& dst, const Immediate& imm) { in movb() argument
418 CHECK(imm.is_int8()); in movb()
419 EmitUint8(imm.value() & 0xFF); in movb()
473 void X86_64Assembler::movw(const Address& dst, const Immediate& imm) { in movw() argument
479 CHECK(imm.is_uint16() || imm.is_int16()); in movw()
480 EmitUint8(imm.value() & 0xFF); in movw()
481 EmitUint8(imm.value() >> 8); in movw()
1452 void X86_64Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) { in roundsd() argument
1460 EmitUint8(imm.value()); in roundsd()
1464 void X86_64Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) { in roundss() argument
1472 EmitUint8(imm.value()); in roundss()
1986 void X86_64Assembler::shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm) { in shufpd() argument
1993 EmitUint8(imm.value()); in shufpd()
1997 void X86_64Assembler::shufps(XmmRegister dst, XmmRegister src, const Immediate& imm) { in shufps() argument
2003 EmitUint8(imm.value()); in shufps()
2007 void X86_64Assembler::pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm) { in pshufd() argument
2014 EmitUint8(imm.value()); in pshufd()
2379 void X86_64Assembler::cmpb(const Address& address, const Immediate& imm) { in cmpb() argument
2381 CHECK(imm.is_int32()); in cmpb()
2385 EmitUint8(imm.value() & 0xFF); in cmpb()
2389 void X86_64Assembler::cmpw(const Address& address, const Immediate& imm) { in cmpw() argument
2391 CHECK(imm.is_int32()); in cmpw()
2394 EmitComplex(7, address, imm, /* is_16_op= */ true); in cmpw()
2398 void X86_64Assembler::cmpl(CpuRegister reg, const Immediate& imm) { in cmpl() argument
2400 CHECK(imm.is_int32()); in cmpl()
2402 EmitComplex(7, Operand(reg), imm); in cmpl()
2430 void X86_64Assembler::cmpl(const Address& address, const Immediate& imm) { in cmpl() argument
2432 CHECK(imm.is_int32()); in cmpl()
2434 EmitComplex(7, address, imm); in cmpl()
2446 void X86_64Assembler::cmpq(CpuRegister reg, const Immediate& imm) { in cmpq() argument
2448 CHECK(imm.is_int32()); // cmpq only supports 32b immediate. in cmpq()
2450 EmitComplex(7, Operand(reg), imm); in cmpq()
2462 void X86_64Assembler::cmpq(const Address& address, const Immediate& imm) { in cmpq() argument
2463 CHECK(imm.is_int32()); // cmpq only supports 32b immediate. in cmpq()
2466 EmitComplex(7, address, imm); in cmpq()
2544 void X86_64Assembler::testb(const Address& dst, const Immediate& imm) { in testb() argument
2549 CHECK(imm.is_int8()); in testb()
2550 EmitUint8(imm.value() & 0xFF); in testb()
2554 void X86_64Assembler::testl(const Address& dst, const Immediate& imm) { in testl() argument
2559 EmitImmediate(imm); in testl()
2579 void X86_64Assembler::andl(CpuRegister dst, const Immediate& imm) { in andl() argument
2582 EmitComplex(4, Operand(dst), imm); in andl()
2586 void X86_64Assembler::andq(CpuRegister reg, const Immediate& imm) { in andq() argument
2588 CHECK(imm.is_int32()); // andq only supports 32b immediate. in andq()
2590 EmitComplex(4, Operand(reg), imm); in andq()
2626 void X86_64Assembler::orl(CpuRegister dst, const Immediate& imm) { in orl() argument
2629 EmitComplex(1, Operand(dst), imm); in orl()
2633 void X86_64Assembler::orq(CpuRegister dst, const Immediate& imm) { in orq() argument
2635 CHECK(imm.is_int32()); // orq only supports 32b immediate. in orq()
2637 EmitComplex(1, Operand(dst), imm); in orq()
2673 void X86_64Assembler::xorl(CpuRegister dst, const Immediate& imm) { in xorl() argument
2676 EmitComplex(6, Operand(dst), imm); in xorl()
2688 void X86_64Assembler::xorq(CpuRegister dst, const Immediate& imm) { in xorq() argument
2690 CHECK(imm.is_int32()); // xorq only supports 32b immediate. in xorq()
2692 EmitComplex(6, Operand(dst), imm); in xorq()
2756 void X86_64Assembler::addl(CpuRegister reg, const Immediate& imm) { in addl() argument
2759 EmitComplex(0, Operand(reg), imm); in addl()
2763 void X86_64Assembler::addq(CpuRegister reg, const Immediate& imm) { in addq() argument
2765 CHECK(imm.is_int32()); // addq only supports 32b immediate. in addq()
2767 EmitComplex(0, Operand(reg), imm); in addq()
2796 void X86_64Assembler::addl(const Address& address, const Immediate& imm) { in addl() argument
2799 EmitComplex(0, address, imm); in addl()
2803 void X86_64Assembler::addw(const Address& address, const Immediate& imm) { in addw() argument
2805 CHECK(imm.is_uint16() || imm.is_int16()) << imm.value(); in addw()
2808 EmitComplex(0, address, imm, /* is_16_op= */ true); in addw()
2820 void X86_64Assembler::subl(CpuRegister reg, const Immediate& imm) { in subl() argument
2823 EmitComplex(5, Operand(reg), imm); in subl()
2827 void X86_64Assembler::subq(CpuRegister reg, const Immediate& imm) { in subq() argument
2829 CHECK(imm.is_int32()); // subq only supports 32b immediate. in subq()
2831 EmitComplex(5, Operand(reg), imm); in subq()
2896 void X86_64Assembler::imull(CpuRegister dst, CpuRegister src, const Immediate& imm) { in imull() argument
2898 CHECK(imm.is_int32()); // imull only supports 32b immediate. in imull()
2903 int32_t v32 = static_cast<int32_t>(imm.value()); in imull()
2913 EmitImmediate(imm); in imull()
2918 void X86_64Assembler::imull(CpuRegister reg, const Immediate& imm) { in imull() argument
2919 imull(reg, reg, imm); in imull()
2941 void X86_64Assembler::imulq(CpuRegister reg, const Immediate& imm) { in imulq() argument
2942 imulq(reg, reg, imm); in imulq()
2945 void X86_64Assembler::imulq(CpuRegister dst, CpuRegister reg, const Immediate& imm) { in imulq() argument
2947 CHECK(imm.is_int32()); // imulq only supports 32b immediate. in imulq()
2952 int64_t v64 = imm.value(); in imulq()
2962 EmitImmediate(imm); in imulq()
3015 void X86_64Assembler::shll(CpuRegister reg, const Immediate& imm) { in shll() argument
3016 EmitGenericShift(false, 4, reg, imm); in shll()
3020 void X86_64Assembler::shlq(CpuRegister reg, const Immediate& imm) { in shlq() argument
3021 EmitGenericShift(true, 4, reg, imm); in shlq()
3035 void X86_64Assembler::shrl(CpuRegister reg, const Immediate& imm) { in shrl() argument
3036 EmitGenericShift(false, 5, reg, imm); in shrl()
3040 void X86_64Assembler::shrq(CpuRegister reg, const Immediate& imm) { in shrq() argument
3041 EmitGenericShift(true, 5, reg, imm); in shrq()
3055 void X86_64Assembler::sarl(CpuRegister reg, const Immediate& imm) { in sarl() argument
3056 EmitGenericShift(false, 7, reg, imm); in sarl()
3065 void X86_64Assembler::sarq(CpuRegister reg, const Immediate& imm) { in sarq() argument
3066 EmitGenericShift(true, 7, reg, imm); in sarq()
3075 void X86_64Assembler::roll(CpuRegister reg, const Immediate& imm) { in roll() argument
3076 EmitGenericShift(false, 0, reg, imm); in roll()
3085 void X86_64Assembler::rorl(CpuRegister reg, const Immediate& imm) { in rorl() argument
3086 EmitGenericShift(false, 1, reg, imm); in rorl()
3095 void X86_64Assembler::rolq(CpuRegister reg, const Immediate& imm) { in rolq() argument
3096 EmitGenericShift(true, 0, reg, imm); in rolq()
3105 void X86_64Assembler::rorq(CpuRegister reg, const Immediate& imm) { in rorq() argument
3106 EmitGenericShift(true, 1, reg, imm); in rorq()
3147 void X86_64Assembler::enter(const Immediate& imm) { in enter() argument
3150 CHECK(imm.is_uint16()) << imm.value(); in enter()
3151 EmitUint8(imm.value() & 0xFF); in enter()
3152 EmitUint8((imm.value() >> 8) & 0xFF); in enter()
3169 void X86_64Assembler::ret(const Immediate& imm) { in ret() argument
3172 CHECK(imm.is_uint16()); in ret()
3173 EmitUint8(imm.value() & 0xFF); in ret()
3174 EmitUint8((imm.value() >> 8) & 0xFF); in ret()
3352 void X86_64Assembler::AddImmediate(CpuRegister reg, const Immediate& imm) { in AddImmediate() argument
3353 int value = imm.value(); in AddImmediate()
3356 addl(reg, imm); in AddImmediate()
3645 void X86_64Assembler::EmitImmediate(const Immediate& imm, bool is_16_op) { in EmitImmediate() argument
3647 EmitUint8(imm.value() & 0xFF); in EmitImmediate()
3648 EmitUint8(imm.value() >> 8); in EmitImmediate()
3649 } else if (imm.is_int32()) { in EmitImmediate()
3650 EmitInt32(static_cast<int32_t>(imm.value())); in EmitImmediate()
3652 EmitInt64(imm.value()); in EmitImmediate()
3717 const Immediate& imm) { in EmitGenericShift() argument
3719 CHECK(imm.is_int8()); in EmitGenericShift()
3725 if (imm.value() == 1) { in EmitGenericShift()
3731 EmitUint8(imm.value() & 0xFF); in EmitGenericShift()