Lines Matching refs:dst
374 void movq(CpuRegister dst, const Immediate& src);
375 void movl(CpuRegister dst, const Immediate& src);
376 void movq(CpuRegister dst, CpuRegister src);
377 void movl(CpuRegister dst, CpuRegister src);
379 void movntl(const Address& dst, CpuRegister src);
380 void movntq(const Address& dst, CpuRegister src);
382 void movq(CpuRegister dst, const Address& src);
383 void movl(CpuRegister dst, const Address& src);
384 void movq(const Address& dst, CpuRegister src);
385 void movq(const Address& dst, const Immediate& imm);
386 void movl(const Address& dst, CpuRegister src);
387 void movl(const Address& dst, const Immediate& imm);
389 void cmov(Condition c, CpuRegister dst, CpuRegister src); // This is the 64b version.
390 void cmov(Condition c, CpuRegister dst, CpuRegister src, bool is64bit);
391 void cmov(Condition c, CpuRegister dst, const Address& src, bool is64bit);
393 void movzxb(CpuRegister dst, CpuRegister src);
394 void movzxb(CpuRegister dst, const Address& src);
395 void movsxb(CpuRegister dst, CpuRegister src);
396 void movsxb(CpuRegister dst, const Address& src);
397 void movb(CpuRegister dst, const Address& src);
398 void movb(const Address& dst, CpuRegister src);
399 void movb(const Address& dst, const Immediate& imm);
401 void movzxw(CpuRegister dst, CpuRegister src);
402 void movzxw(CpuRegister dst, const Address& src);
403 void movsxw(CpuRegister dst, CpuRegister src);
404 void movsxw(CpuRegister dst, const Address& src);
405 void movw(CpuRegister dst, const Address& src);
406 void movw(const Address& dst, CpuRegister src);
407 void movw(const Address& dst, const Immediate& imm);
409 void leaq(CpuRegister dst, const Address& src);
410 void leal(CpuRegister dst, const Address& src);
412 void movaps(XmmRegister dst, XmmRegister src); // move
413 void movaps(XmmRegister dst, const Address& src); // load aligned
414 void movups(XmmRegister dst, const Address& src); // load unaligned
415 void movaps(const Address& dst, XmmRegister src); // store aligned
416 void movups(const Address& dst, XmmRegister src); // store unaligned
418 void movss(XmmRegister dst, const Address& src);
419 void movss(const Address& dst, XmmRegister src);
420 void movss(XmmRegister dst, XmmRegister src);
422 void movsxd(CpuRegister dst, CpuRegister src);
423 void movsxd(CpuRegister dst, const Address& src);
425 void movd(XmmRegister dst, CpuRegister src); // Note: this is the r64 version, formally movq.
426 void movd(CpuRegister dst, XmmRegister src); // Note: this is the r64 version, formally movq.
427 void movd(XmmRegister dst, CpuRegister src, bool is64bit);
428 void movd(CpuRegister dst, XmmRegister src, bool is64bit);
430 void addss(XmmRegister dst, XmmRegister src);
431 void addss(XmmRegister dst, const Address& src);
432 void subss(XmmRegister dst, XmmRegister src);
433 void subss(XmmRegister dst, const Address& src);
434 void mulss(XmmRegister dst, XmmRegister src);
435 void mulss(XmmRegister dst, const Address& src);
436 void divss(XmmRegister dst, XmmRegister src);
437 void divss(XmmRegister dst, const Address& src);
439 void addps(XmmRegister dst, XmmRegister src); // no addr variant (for now)
440 void subps(XmmRegister dst, XmmRegister src);
441 void mulps(XmmRegister dst, XmmRegister src);
442 void divps(XmmRegister dst, XmmRegister src);
444 void movapd(XmmRegister dst, XmmRegister src); // move
445 void movapd(XmmRegister dst, const Address& src); // load aligned
446 void movupd(XmmRegister dst, const Address& src); // load unaligned
447 void movapd(const Address& dst, XmmRegister src); // store aligned
448 void movupd(const Address& dst, XmmRegister src); // store unaligned
450 void movsd(XmmRegister dst, const Address& src);
451 void movsd(const Address& dst, XmmRegister src);
452 void movsd(XmmRegister dst, XmmRegister src);
454 void addsd(XmmRegister dst, XmmRegister src);
455 void addsd(XmmRegister dst, const Address& src);
456 void subsd(XmmRegister dst, XmmRegister src);
457 void subsd(XmmRegister dst, const Address& src);
458 void mulsd(XmmRegister dst, XmmRegister src);
459 void mulsd(XmmRegister dst, const Address& src);
460 void divsd(XmmRegister dst, XmmRegister src);
461 void divsd(XmmRegister dst, const Address& src);
463 void addpd(XmmRegister dst, XmmRegister src); // no addr variant (for now)
464 void subpd(XmmRegister dst, XmmRegister src);
465 void mulpd(XmmRegister dst, XmmRegister src);
466 void divpd(XmmRegister dst, XmmRegister src);
468 void movdqa(XmmRegister dst, XmmRegister src); // move
469 void movdqa(XmmRegister dst, const Address& src); // load aligned
470 void movdqu(XmmRegister dst, const Address& src); // load unaligned
471 void movdqa(const Address& dst, XmmRegister src); // store aligned
472 void movdqu(const Address& dst, XmmRegister src); // store unaligned
474 void paddb(XmmRegister dst, XmmRegister src); // no addr variant (for now)
475 void psubb(XmmRegister dst, XmmRegister src);
477 void paddw(XmmRegister dst, XmmRegister src);
478 void psubw(XmmRegister dst, XmmRegister src);
479 void pmullw(XmmRegister dst, XmmRegister src);
481 void paddd(XmmRegister dst, XmmRegister src);
482 void psubd(XmmRegister dst, XmmRegister src);
483 void pmulld(XmmRegister dst, XmmRegister src);
485 void paddq(XmmRegister dst, XmmRegister src);
486 void psubq(XmmRegister dst, XmmRegister src);
488 void paddusb(XmmRegister dst, XmmRegister src);
489 void paddsb(XmmRegister dst, XmmRegister src);
490 void paddusw(XmmRegister dst, XmmRegister src);
491 void paddsw(XmmRegister dst, XmmRegister src);
492 void psubusb(XmmRegister dst, XmmRegister src);
493 void psubsb(XmmRegister dst, XmmRegister src);
494 void psubusw(XmmRegister dst, XmmRegister src);
495 void psubsw(XmmRegister dst, XmmRegister src);
497 void cvtsi2ss(XmmRegister dst, CpuRegister src); // Note: this is the r/m32 version.
498 void cvtsi2ss(XmmRegister dst, CpuRegister src, bool is64bit);
499 void cvtsi2ss(XmmRegister dst, const Address& src, bool is64bit);
500 void cvtsi2sd(XmmRegister dst, CpuRegister src); // Note: this is the r/m32 version.
501 void cvtsi2sd(XmmRegister dst, CpuRegister src, bool is64bit);
502 void cvtsi2sd(XmmRegister dst, const Address& src, bool is64bit);
504 void cvtss2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version.
505 void cvtss2sd(XmmRegister dst, XmmRegister src);
506 void cvtss2sd(XmmRegister dst, const Address& src);
508 void cvtsd2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version.
509 void cvtsd2ss(XmmRegister dst, XmmRegister src);
510 void cvtsd2ss(XmmRegister dst, const Address& src);
512 void cvttss2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version.
513 void cvttss2si(CpuRegister dst, XmmRegister src, bool is64bit);
514 void cvttsd2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version.
515 void cvttsd2si(CpuRegister dst, XmmRegister src, bool is64bit);
517 void cvtdq2ps(XmmRegister dst, XmmRegister src);
518 void cvtdq2pd(XmmRegister dst, XmmRegister src);
529 void roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm);
530 void roundss(XmmRegister dst, XmmRegister src, const Immediate& imm);
532 void sqrtsd(XmmRegister dst, XmmRegister src);
533 void sqrtss(XmmRegister dst, XmmRegister src);
535 void xorpd(XmmRegister dst, const Address& src);
536 void xorpd(XmmRegister dst, XmmRegister src);
537 void xorps(XmmRegister dst, const Address& src);
538 void xorps(XmmRegister dst, XmmRegister src);
539 void pxor(XmmRegister dst, XmmRegister src); // no addr variant (for now)
541 void andpd(XmmRegister dst, const Address& src);
542 void andpd(XmmRegister dst, XmmRegister src);
543 void andps(XmmRegister dst, XmmRegister src); // no addr variant (for now)
544 void pand(XmmRegister dst, XmmRegister src);
546 void andn(CpuRegister dst, CpuRegister src1, CpuRegister src2);
547 void andnpd(XmmRegister dst, XmmRegister src); // no addr variant (for now)
548 void andnps(XmmRegister dst, XmmRegister src);
549 void pandn(XmmRegister dst, XmmRegister src);
551 void orpd(XmmRegister dst, XmmRegister src); // no addr variant (for now)
552 void orps(XmmRegister dst, XmmRegister src);
553 void por(XmmRegister dst, XmmRegister src);
555 void pavgb(XmmRegister dst, XmmRegister src); // no addr variant (for now)
556 void pavgw(XmmRegister dst, XmmRegister src);
557 void psadbw(XmmRegister dst, XmmRegister src);
558 void pmaddwd(XmmRegister dst, XmmRegister src);
559 void phaddw(XmmRegister dst, XmmRegister src);
560 void phaddd(XmmRegister dst, XmmRegister src);
561 void haddps(XmmRegister dst, XmmRegister src);
562 void haddpd(XmmRegister dst, XmmRegister src);
563 void phsubw(XmmRegister dst, XmmRegister src);
564 void phsubd(XmmRegister dst, XmmRegister src);
565 void hsubps(XmmRegister dst, XmmRegister src);
566 void hsubpd(XmmRegister dst, XmmRegister src);
568 void pminsb(XmmRegister dst, XmmRegister src); // no addr variant (for now)
569 void pmaxsb(XmmRegister dst, XmmRegister src);
570 void pminsw(XmmRegister dst, XmmRegister src);
571 void pmaxsw(XmmRegister dst, XmmRegister src);
572 void pminsd(XmmRegister dst, XmmRegister src);
573 void pmaxsd(XmmRegister dst, XmmRegister src);
575 void pminub(XmmRegister dst, XmmRegister src); // no addr variant (for now)
576 void pmaxub(XmmRegister dst, XmmRegister src);
577 void pminuw(XmmRegister dst, XmmRegister src);
578 void pmaxuw(XmmRegister dst, XmmRegister src);
579 void pminud(XmmRegister dst, XmmRegister src);
580 void pmaxud(XmmRegister dst, XmmRegister src);
582 void minps(XmmRegister dst, XmmRegister src); // no addr variant (for now)
583 void maxps(XmmRegister dst, XmmRegister src);
584 void minpd(XmmRegister dst, XmmRegister src);
585 void maxpd(XmmRegister dst, XmmRegister src);
587 void pcmpeqb(XmmRegister dst, XmmRegister src);
588 void pcmpeqw(XmmRegister dst, XmmRegister src);
589 void pcmpeqd(XmmRegister dst, XmmRegister src);
590 void pcmpeqq(XmmRegister dst, XmmRegister src);
592 void pcmpgtb(XmmRegister dst, XmmRegister src);
593 void pcmpgtw(XmmRegister dst, XmmRegister src);
594 void pcmpgtd(XmmRegister dst, XmmRegister src);
595 void pcmpgtq(XmmRegister dst, XmmRegister src); // SSE4.2
597 void shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm);
598 void shufps(XmmRegister dst, XmmRegister src, const Immediate& imm);
599 void pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm);
601 void punpcklbw(XmmRegister dst, XmmRegister src);
602 void punpcklwd(XmmRegister dst, XmmRegister src);
603 void punpckldq(XmmRegister dst, XmmRegister src);
604 void punpcklqdq(XmmRegister dst, XmmRegister src);
606 void punpckhbw(XmmRegister dst, XmmRegister src);
607 void punpckhwd(XmmRegister dst, XmmRegister src);
608 void punpckhdq(XmmRegister dst, XmmRegister src);
609 void punpckhqdq(XmmRegister dst, XmmRegister src);
625 void fstps(const Address& dst);
626 void fsts(const Address& dst);
629 void fstpl(const Address& dst);
630 void fstl(const Address& dst);
636 void fnstcw(const Address& dst);
639 void fistpl(const Address& dst);
640 void fistps(const Address& dst);
652 void xchgl(CpuRegister dst, CpuRegister src);
653 void xchgq(CpuRegister dst, CpuRegister src);
680 void andl(CpuRegister dst, const Immediate& imm);
681 void andl(CpuRegister dst, CpuRegister src);
683 void andq(CpuRegister dst, const Immediate& imm);
684 void andq(CpuRegister dst, CpuRegister src);
687 void orl(CpuRegister dst, const Immediate& imm);
688 void orl(CpuRegister dst, CpuRegister src);
690 void orq(CpuRegister dst, CpuRegister src);
691 void orq(CpuRegister dst, const Immediate& imm);
694 void xorl(CpuRegister dst, CpuRegister src);
695 void xorl(CpuRegister dst, const Immediate& imm);
697 void xorq(CpuRegister dst, const Immediate& imm);
698 void xorq(CpuRegister dst, CpuRegister src);
701 void addl(CpuRegister dst, CpuRegister src);
709 void addq(CpuRegister dst, CpuRegister src);
710 void addq(CpuRegister dst, const Address& address);
712 void subl(CpuRegister dst, CpuRegister src);
717 void subq(CpuRegister dst, CpuRegister src);
718 void subq(CpuRegister dst, const Address& address);
726 void imull(CpuRegister dst, CpuRegister src);
728 void imull(CpuRegister dst, CpuRegister src, const Immediate& imm);
732 void imulq(CpuRegister dst, CpuRegister src);
735 void imulq(CpuRegister dst, CpuRegister reg, const Immediate& imm);
790 void setcc(Condition condition, CpuRegister dst);
792 void bswapl(CpuRegister dst);
793 void bswapq(CpuRegister dst);
795 void bsfl(CpuRegister dst, CpuRegister src);
796 void bsfl(CpuRegister dst, const Address& src);
797 void bsfq(CpuRegister dst, CpuRegister src);
798 void bsfq(CpuRegister dst, const Address& src);
800 void blsi(CpuRegister dst, CpuRegister src); // no addr variant (for now)
801 void blsmsk(CpuRegister dst, CpuRegister src); // no addr variant (for now)
802 void blsr(CpuRegister dst, CpuRegister src); // no addr variant (for now)
804 void bsrl(CpuRegister dst, CpuRegister src);
805 void bsrl(CpuRegister dst, const Address& src);
806 void bsrq(CpuRegister dst, CpuRegister src);
807 void bsrq(CpuRegister dst, const Address& src);
809 void popcntl(CpuRegister dst, CpuRegister src);
810 void popcntl(CpuRegister dst, const Address& src);
811 void popcntq(CpuRegister dst, CpuRegister src);
812 void popcntq(CpuRegister dst, const Address& src);
837 void LoadDoubleConstant(XmmRegister dst, double value);
937 void EmitOptionalRex32(CpuRegister dst, CpuRegister src);
938 void EmitOptionalRex32(XmmRegister dst, XmmRegister src);
939 void EmitOptionalRex32(CpuRegister dst, XmmRegister src);
940 void EmitOptionalRex32(XmmRegister dst, CpuRegister src);
942 void EmitOptionalRex32(CpuRegister dst, const Operand& operand);
943 void EmitOptionalRex32(XmmRegister dst, const Operand& operand);
949 void EmitRex64(CpuRegister dst, CpuRegister src);
950 void EmitRex64(CpuRegister dst, const Operand& operand);
951 void EmitRex64(XmmRegister dst, const Operand& operand);
952 void EmitRex64(XmmRegister dst, CpuRegister src);
953 void EmitRex64(CpuRegister dst, XmmRegister src);
956 void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src);
957 void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand);