Lines Matching refs:bakery

2043 The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory
2053          *                choosing its bakery number.
2054          * Bits[1 - 15] : number. This is the bakery number allocated.
2078 To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure
2080 algorithm mentioned earlier. The bakery\_lock structure only allocates the memory
2081 for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks
2083 for other cores by using the total size allocated for the bakery\_lock section
2088 The bakery lock data structure ``bakery_info_t`` is defined for use when
2097          *                choosing its bakery number.
2098          * Bits[1 - 15] : number. This is the bakery number allocated.
2105 system represents the complete bakery lock. The view in memory for a system
2106 with n bakery locks are:
2145 Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an
2150 On ARM Platforms, bakery locks are used in psci (``psci_locks``) and power controller
2161 There is however a performance impact for bakery locks, due to:
2164 -  Multiple cache line reads for each lock operation, since the bakery locks
2168 Measurements indicate that when bakery locks are allocated in Normal memory, the
2176 ``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can