Lines Matching refs:TSP

294    (TSP) which runs only in Secure-EL1.
440    initialisation. The TSP provides the address of the vector table
442    interrupts in the ``sel1_intr_entry`` field. The TSPD passes control to the TSP at
445    The handover agreement between the TSP and the TSPD requires that the TSPD
447    ``tsp_sel1_intr_entry()``. The TSP has to preserve the callee saved general
580 The routing model for Secure-EL1 and non-secure interrupts chosen by the TSP is
583 The TSP implements an entrypoint (``tsp_sel1_intr_entry()``) for handling Secure-EL1
588 The TSP also replaces the default exception vector table referenced through the
594 The TSP also programs the Secure Physical Timer in the ARM Generic Timer block
747 Secure-EL1 interrupts are handled in S-EL1 by TSP. Its handler
761    ``TSP_HANDLE_SEL1_INTR_AND_RETURN``. If the TSP was preempted earlier by a non
764    to re-enter TSP for Secure-EL1 interrupt processing. It does not need to
765    save any other secure context since the TSP is expected to preserve it
785 The TSP issues an SMC with ``TSP_HANDLED_S_EL1_INTR`` as the function identifier to
795    the secure CPU context (see step 3 above) in case the TSP had been preempted
810 The TSP in Secure-EL1 can be preempted by a non-secure interrupt during
813 cause preemption of TSP since there are no EL3 interrupts in the
816 It should be noted that while TSP is preempted, the TSPD only allows entry into
817 the TSP either for Secure-EL1 interrupt handling or for resuming the preempted
830 interrupt) when TSP is reentered for handling Secure-EL1 interrupts that
839 trigger at Secure-EL1 IRQ exception vector. The TSP saves the general purpose
841 identifier to signal preemption of TSP. The TSPD SMC handler,
862 The Normal World is expected to resume the TSP after the ``yielding`` SMC preemption
870 #. Checks whether the TSP needs a resume i.e check if it was preempted. It
883 The figure below describes how the TSP/TSPD handle a non-secure interrupt when
884 it is generated during execution in the TSP with ``PSTATE.I`` = 0 when the
916 The TSPD hands control of a Secure-EL1 interrupt to the TSP at the
917 ``tsp_sel1_intr_entry()``. The TSP handles the interrupt while ensuring that the
935 The TSP passes control back to the TSPD by issuing an SMC64 with
938 The TSP handles interrupts under the asynchronous model as follows.
947    control to the TSP in response to an SMC with ``TSP_FID_RESUME`` as the
993 TSP by returning ``SMC_UNK`` error.