Lines Matching refs:handled

14 #. It should be possible to route interrupts meant to be handled by secure
23 #. It should be possible to route interrupts meant to be handled by
39 the exception level(s) it is handled in.
43    context. It is always handled in Secure-EL1.
47    current execution context. It is always handled in either Non-secure EL1
52    always handled in EL3.
139    is handled by non-secure software.
209    handled in Secure-EL1. They can be delivered to Secure-EL1 via EL3 but they
210    cannot be handled in EL3.
499    non-secure state. Any non-secure interrupts will be handled as described
525    If ``PSTATE.F=1`` then Secure-EL1 interrupts will be handled as per the
535    non-secure state. They should be handled through the synchronous interrupt
551    non-secure state where the interrupt should be handled e.g the SP could
565    the non-secure state where the interrupt will be handled. The Secure-EL1
568 #. **CSS=1, TEL3=0**. Non-secure interrupts are handled in the FEL in
616    lower exception level using AArch64 or AArch32 are handled.
723    the interrupt has been successfully validated and ready to be handled at a
731 so that the interrupt can be handled.
747 Secure-EL1 interrupts are handled in S-EL1 by TSP. Its handler
775    now be handled by the SP. ``x1`` is written with the value of ``elr_el3``
910 level. This will allow the non-secure interrupt to be handled in the non-secure
940 #. Secure-EL1 interrupts are handled by calling the ``tsp_common_int_handler()``
943 #. Non-secure interrupts are handled by by calling the ``tsp_common_int_handler()``
977     /* The pending non-secure interrupt is handled by the interrupt handler