Lines Matching refs:the
11 allows EL3 software to configure the interrupt routing behavior. Its main
12 objective is to implement the following two requirements.
17 the interrupt to either software in EL3 or Secure-EL1 depending upon the
18 software configuration and the GIC implementation. This requirement ensures
19 that secure interrupts are under the control of the secure software with
20 respect to their delivery and handling without the possibility of
24 non-secure software (Non-secure interrupts) to the last executed exception
25 level in the normal world when the execution is in secure world at
26 exception levels lower than EL3. This could be done with or without the
28 approach should be governed by the secure software. This requirement
29 ensures that non-secure software is able to execute in tandem with the
38 The framework categorises an interrupt to be one of the following depending upon
39 the exception level(s) it is handled in.
42 Secure-EL1 depending upon the security state of the current execution
46 Secure-EL1, Non-secure EL1 or EL2 depending upon the security state of the
51 depending upon the security state of the current execution context. It is
54 The following constants define the various interrupt types in the framework
67 exception level of an interrupt type is configured through the FIQ and IRQ bits
68 in the Secure Configuration Register at EL3 (``SCR_EL3.FIQ`` and ``SCR_EL3.IRQ``
70 to the First Exception Level (FEL) capable of handling interrupts. When
71 ``SCR_EL3.IRQ``\ =1, IRQs are routed to EL3. Otherwise they are routed to the
77 single bit for each security state. A value of ``0`` means that the interrupt
78 should be routed to the FEL. A value of ``1`` means that the interrupt should be
81 The default routing model for an interrupt type is to route it to the FEL in
88 incorrect as they conflict with the requirements mentioned in Section 1. The
89 following sub-sections describe all the possible routing models and specify
91 for GIC version 3.0 (ARM GICv3) and only the Secure-EL1 and Non-secure interrupt
93 used in the following sub-sections is explained below.
97 #. **TEL3**. Target Exception Level 3. ``0`` when targeted to the FEL. ``1`` when
103 #. **CSS=0, TEL3=0**. Interrupt is routed to the FEL when execution is in
109 handover the interrupt to Secure-EL1 for handling.
111 #. **CSS=1, TEL3=0**. Interrupt is routed to the FEL when execution is in
113 is not visible to the secure software which violates the motivation behind
114 the ARM Security Extensions.
118 can handover the interrupt to Secure-EL1 for handling.
123 #. **CSS=0, TEL3=0**. Interrupt is routed to the FEL when execution is in
124 secure state. This allows the secure software to trap non-secure
125 interrupts, perform its book-keeping and hand the interrupt to the
132 the state of software in Secure-EL1/Secure-EL0 before handing the
134 coordination between Secure-EL1 and EL3 software to ensure that the
135 former's state is correctly saved by the latter.
143 reason to route the interrupt to EL3 software and then hand it back to
149 #. **CSS=0, TEL3=0**. Interrupt is routed to the FEL when execution is in
152 by EL3 interrupt and can handover the interrupt to EL3 for handling.
156 in EL3 can handle the interrupt.
158 #. **CSS=1, TEL3=0**. Interrupt is routed to the FEL when execution is in
160 is not visible to the secure software which violates the motivation behind
161 the ARM Security Extensions.
165 can handle the interrupt.
172 FIQ or IRQ signal to the CPU depending upon the current security state. The
173 mapping between the type and signal is known only to the platform. The framework
174 uses this information to determine whether the IRQ or the FIQ bit should be
175 programmed in ``SCR_EL3`` while applying the routing model for a type of
176 interrupt. The platform provides this information through the
177 ``plat_interrupt_type_to_line()`` API (described in the
178 `Porting Guide`_). For example, on the FVP port when the platform uses an ARM GICv2
179 interrupt controller, Secure-EL1 interrupts are signaled through the FIQ signal
180 while Non-secure interrupts are signaled through the IRQ signal. This applies
187 interrupt signal, and if any one of the interrupt type sets **TEL3=1** for a
189 that security state. This means that all the other interrupt types using the
190 same interrupt signal will be forced to the same routing model. This should be
191 borne in mind when choosing the routing model for an interrupt type.
193 For example, in ARM GICv3, when the execution context is Secure-EL1/
194 Secure-EL0, both the EL3 and the non secure interrupt types map to the FIQ
195 signal. So if either one of the interrupt type sets the routing model so
196 that **TEL3=1** when **CSS=0**, the FIQ bit in ``SCR_EL3`` will be programmed to
197 route the FIQ signal to EL3 when executing in Secure-EL1/Secure-EL0, thereby
198 effectively routing the other interrupt type also to EL3.
203 The framework makes the following assumptions to simplify its implementation.
205 #. Although the framework has support for 2 types of secure interrupts (EL3
207 like ARM GICv3 has architectural support for EL3 interrupts in the form of
218 The following sections describe how interrupts are managed by the interrupt
222 of the routing model for a type of interrupt.
225 handler when the interrupt is generated.
227 Both aspects of interrupt management involve various components in the secure
229 in the section 2.1. The framework stores information associated with each type
230 of interrupt in the following data structure.
240 The ``flags`` field stores the routing model for the interrupt type in
241 bits[1:0]. Bit[0] stores the routing model when execution is in the secure
242 state. Bit[1] stores the routing model when execution is in the non-secure
243 state. As mentioned in Section 1.2.2, a value of ``0`` implies that the interrupt
244 should be targeted to the FEL. A value of ``1`` implies that it should be targeted
246 ``set_interrupt_rm_flag()`` should be used to set the bits in the ``flags``
249 The ``scr_el3[2]`` field also stores the routing model but as a mapping of the
250 model in the ``flags`` field to the corresponding bit in the ``SCR_EL3`` for each
253 The framework also depends upon the platform port to configure the interrupt
255 is expected to be aware of the secure devices present in the system and their
256 associated interrupt numbers. It should configure the interrupt controller to
257 enable the secure interrupts, ensure that their priority is always higher than
258 the non-secure interrupts and target them to the primary CPU. It should also
259 export the interface described in the `Porting Guide`_ to enable
262 In the remainder of this document, for the sake of simplicity a ARM GICv2 system
263 is considered and it is assumed that the FIQ signal is used to generate Secure-EL1
264 interrupts and the IRQ signal is used to generate non-secure interrupts in either
270 Roles and responsibilities for interrupt management are sub-divided between the
274 #. EL3 Runtime Firmware. This component is common to all ports of the ARM
277 #. Secure Payload Dispatcher (SPD) service. This service interfaces with the
280 A switch is triggered by a Secure Monitor Call and it uses the APIs
281 exported by the Context management library to implement this functionality.
282 Switching execution between the two security states is a requirement for
284 the SPD service. ARM Trusted firmware implements an example Test Secure
287 An SPD service plugs into the EL3 runtime firmware and could be common to
288 some ports of the ARM Trusted Firmware.
290 #. Secure Payload (SP). On a production system, the Secure Payload corresponds
291 to a Secure OS which runs in Secure-EL1/Secure-EL0. It interfaces with the
296 A Secure payload implementation could be common to some ports of the ARM
297 Trusted Firmware just like the SPD service.
302 This section describes in detail the role of each software component (see 2.1)
303 during the registration of a handler for an interrupt type.
308 This component declares the following prototype for a handler of an interrupt type.
317 The ``id`` is parameter is reserved and could be used in the future for passing
318 the interrupt id of the highest pending interrupt only if there is a foolproof
319 way of determining the id. Currently it contains ``INTR_ID_UNAVAILABLE``.
323 #. Security state, bit[0]. This bit indicates the security state of the lower
324 exception level when the interrupt was generated. A value of ``1`` means
325 that it was in the non-secure state. A value of ``0`` indicates that it was
326 in the secure state. This bit can be used by the handler to ensure that
327 interrupt was generated and routed as per the routing model specified
332 The ``handle`` parameter points to the ``cpu_context`` structure of the current CPU
333 for the security state specified in the ``flags`` parameter.
335 Once the handler routine completes, execution will return to either the secure
337 ``cpu_context`` structure of the current CPU for the target security state. On
338 AArch64, this return value is currently ignored by the caller as the
339 appropriate ``cpu_context`` to be used is expected to be set by the handler
340 via the context management library APIs.
341 A portable interrupt handler implementation must set the target context both in
342 the structure pointed to by the returned pointer and via the context management
347 The runtime firmware provides the following API for registering a handler for a
350 interrupts. This API also requires the caller to specify the routing model for
351 the type of interrupt.
359 The ``type`` parameter can be one of the three interrupt types listed above i.e.
364 ``-EALREADY`` in case a handler for the interrupt type has already been
365 registered. If the ``type`` is unrecognised or the ``flags`` or the ``handler`` are
368 Interrupt routing is governed by the configuration of the ``SCR_EL3.FIQ/IRQ`` bits
370 context management library maintains a copy of the ``SCR_EL3`` system register for
371 each security state in the ``cpu_context`` structure of each CPU. It exports the
372 following APIs to let EL3 Runtime Firmware program and retrieve the routing
373 model for each security state for the current CPU. The value of ``SCR_EL3`` stored
374 in the ``cpu_context`` is used by the ``el3_exit()`` function to program the
375 ``SCR_EL3`` register prior to returning from the EL3 exception level.
384 ``cm_get_scr_el3()`` returns the value of the ``SCR_EL3`` register for the specified
385 security state of the current CPU. ``cm_write_scr_el3()`` writes a ``0`` or ``1`` to
386 the bit specified by ``bit_pos``. ``register_interrupt_type_handler()`` invokes
387 ``set_routing_model()`` API which programs the ``SCR_EL3`` according to the routing
388 model using the ``cm_get_scr_el3()`` and ``cm_write_scr_el3_bit()`` APIs.
390 It is worth noting that in the current implementation of the framework, the EL3
391 runtime firmware is responsible for programming the routing model. The SPD is
392 responsible for ensuring that the routing model has been adhered to upon
398 A SPD service is responsible for determining and maintaining the interrupt
399 routing model supported by itself and the Secure Payload. It is also responsible
401 the routing model. It could determine the routing model at build time or at
403 type using the ``register_interrupt_type_handler()`` API in EL3 runtime firmware.
405 If the routing model is not known to the SPD service at build time, then it must
406 be provided by the SP as the result of its initialisation. The SPD should
407 program the routing model only after SP initialisation has completed e.g. in the
408 SPD initialisation function pointed to by the ``bl32_init`` variable.
410 The SPD should determine the mechanism to pass control to the Secure Payload
411 after receiving an interrupt from the EL3 runtime firmware. This information
412 could either be provided to the SPD service at build time or by the SP at
418 The TSPD only handles Secure-EL1 interrupts and is provided with the following
422 state and are routed to the FEL when execution is in the secure state
425 - When the build flag ``TSP_NS_INTR_ASYNC_PREEMPT`` is zero, the default routing
426 model is used for non-secure interrupts. They are routed to the FEL in
430 - When the build flag ``TSP_NS_INTR_ASYNC_PREEMPT`` is defined to 1, then the
436 It performs the following actions in the ``tspd_init()`` function to fulfill the
439 #. It passes control to the Test Secure Payload to perform its
440 initialisation. The TSP provides the address of the vector table
441 ``tsp_vectors`` in the SP which also includes the handler for Secure-EL1
442 interrupts in the ``sel1_intr_entry`` field. The TSPD passes control to the TSP at
445 The handover agreement between the TSP and the TSPD requires that the TSPD
447 ``tsp_sel1_intr_entry()``. The TSP has to preserve the callee saved general
452 function is registered with the EL3 runtime firmware using the
467 #. When the build flag ``TSP_NS_INTR_ASYNC_PREEMPT`` is defined to 1, the TSPD
469 registered with the EL3 runtime firmware using the
489 execution will alternate between the below cases.
491 #. In the code where IRQ, FIQ or both interrupts are enabled, if an interrupt
492 type is targeted to the FEL, then it will be routed to the Secure-EL1
493 exception vector table. This is defined as the **asynchronous mode** of
497 #. In the code where both interrupts are disabled, if an interrupt type is
498 targeted to the FEL, then execution will eventually migrate to the
500 in the routing model where **CSS=1 and TEL3=0**. Secure-EL1 interrupts
501 will be routed to EL3 (as per the routing model where **CSS=1 and
502 TEL3=1**) where the SPD service will hand them to the SP. This is defined
503 as the **synchronous mode** of handling interrupts.
505 The interrupt handling framework implemented by the SP should support one or
506 both these interrupt handling models depending upon the chosen routing model.
508 The following list briefly describes how the choice of a valid routing model
509 (See 1.2.3) effects the implementation of the Secure-EL1 IHF. If the choice of
510 the interrupt routing model is not known to the SPD service at compile time,
511 then the SP should pass this information to the SPD service at runtime during
515 the FIQ signal is used to generate Secure-EL1 interrupts and the IRQ signal
522 triggered at one of the Secure-EL1 FIQ exception vectors. The Secure-EL1
525 If ``PSTATE.F=1`` then Secure-EL1 interrupts will be handled as per the
527 by exporting a separate entrypoint for Secure-EL1 interrupts to the SPD
528 service during the registration phase. The SPD service would also need to
529 know the state of the system, general purpose and the ``PSTATE`` registers
530 in which it should arrange to return execution to the SP. The SP should
531 provide this information in an implementation defined way during the
532 registration phase if it is not known to the SPD service at build time.
535 non-secure state. They should be handled through the synchronous interrupt
539 is in secure state. They will not be visible to the SP. The ``PSTATE.F`` bit
541 call the handler registered by the SPD service for Secure-EL1 interrupts.
542 Secure-EL1 IHF should then handle all Secure-EL1 interrupt through the
549 triggered at one of the Secure-EL1 IRQ exception vectors . The Secure-EL1
550 IHF should co-ordinate with the SPD service to transfer execution to the
551 non-secure state where the interrupt should be handled e.g the SP could
552 allocate a function identifier to issue a SMC64 or SMC32 to the SPD
553 service which indicates that the SP execution has been preempted by a
554 non-secure interrupt. If this function identifier is not known to the SPD
555 service at compile time then the SP could provide it during the
558 If ``PSTATE.I=1`` then the non-secure interrupt will pend until execution
559 resumes in the non-secure state.
562 be visible to the SP. The ``PSTATE.I`` bit in Secure-EL1/Secure-EL0 will
564 handler which should save the SP state correctly and resume execution in
565 the non-secure state where the interrupt will be handled. The Secure-EL1
568 #. **CSS=1, TEL3=0**. Non-secure interrupts are handled in the FEL in
569 non-secure state (EL1/EL2) and are not visible to the SP. This routing
570 model does not affect the SP behavior.
573 configured at the interrupt controller by the platform port of the EL3 runtime
574 firmware. It should configure any additional Secure-EL1 interrupts which the EL3
580 The routing model for Secure-EL1 and non-secure interrupts chosen by the TSP is
581 described in Section 2.2.2. It is known to the TSPD service at build time.
584 interrupts taken in non-secure state and routed through the TSPD service
585 (synchronous handling model). It passes the reference to this entrypoint via
586 ``tsp_vectors`` to the TSPD service.
588 The TSP also replaces the default exception vector table referenced through the
590 exceptions taken at the same (Secure-EL1) exception level. This table is
591 referenced through the ``tsp_exceptions`` variable and programmed into the
592 VBAR\_EL1. It caters for the asynchronous handling model.
594 The TSP also programs the Secure Physical Timer in the ARM Generic Timer block
595 to raise a periodic interrupt (every half a second) for the purpose of testing
596 interrupt management across all the software components listed in 2.1
601 This section describes in detail the role of each software component (see
607 The EL3 runtime firmware populates the IRQ and FIQ exception vectors referenced
608 by the ``runtime_exceptions`` variable as follows.
610 #. IRQ and FIQ exceptions taken from the current exception level with
612 mentioned earlier, EL3 runtime firmware always executes with the
615 #. The following text describes how the IRQ and FIQ exceptions taken from a
618 When an interrupt is generated, the vector for each interrupt type is
621 #. Saving the entire general purpose register context (x0-x30) immediately
622 upon exception entry. The registers are saved in the per-cpu ``cpu_context``
623 data structure referenced by the ``SP_EL3``\ register.
625 #. Saving the ``ELR_EL3``, ``SP_EL0`` and ``SPSR_EL3`` system registers in the
626 per-cpu ``cpu_context`` data structure referenced by the ``SP_EL3`` register.
628 #. Switching to the C runtime stack by restoring the ``CTX_RUNTIME_SP`` value
629 from the per-cpu ``cpu_context`` data structure in ``SP_EL0`` and
630 executing the ``msr spsel, #0`` instruction.
632 #. Determining the type of interrupt. Secure-EL1 interrupts will be signaled
633 at the FIQ vector. Non-secure interrupts will be signaled at the IRQ
634 vector. The platform should implement the following API to determine the
635 type of the pending interrupt.
643 #. Determining the handler for the type of interrupt that has been generated.
650 It returns the reference to the registered handler for this interrupt
651 type. The ``handler`` is retrieved from the ``intr_type_desc_t`` structure as
656 #. Calling the registered handler function for the interrupt type generated.
658 with the current security state and a reference to the ``cpu_context_t``
659 structure for the current security state are passed to the handler function
662 The handler function returns a reference to the per-cpu ``cpu_context_t``
663 structure for the target security state.
666 the security state determined by the handler routine. The ``el3_exit()``
667 function is responsible for restoring the register context from the
668 ``cpu_context_t`` data structure for the target security state.
676 The SPD service begins handling an interrupt when the EL3 runtime firmware calls
677 the handler function for that type of interrupt. The SPD service is responsible
678 for the following:
680 #. Validating the interrupt. This involves ensuring that the interrupt was
681 generating according to the interrupt routing model specified by the SPD
682 service during registration. It should use the security state of the
683 exception level (passed in the ``flags`` parameter of the handler) where
684 the interrupt was taken from to determine this. If the interrupt is not
685 recognised then the handler should treat it as an irrecoverable error
693 could use the security state flag to check this.
695 #. Determining whether a context switch is required. This depends upon the
697 if the security state of the execution context where the interrupt was
698 generated is not the same as the security state required for handling
699 the interrupt, a context switch is required. The following 2 cases
702 #. A Secure-EL1 interrupt taken from the non-secure state should be
703 routed to the Secure Payload.
705 #. A non-secure interrupt taken from the secure state should be routed
706 to the last known non-secure exception level.
708 The SPD service must save the system register context of the current
709 security state. It must then restore the system register context of the
710 target security state. It should use the ``cm_set_next_eret_context()`` API
711 to ensure that the next ``cpu_context`` to be restored is of the target
714 If the target state is secure then execution should be handed to the SP as
715 per the synchronous interrupt handling model it implements. A Secure-EL1
716 interrupt can be routed to EL3 while execution is in the SP. This implies
720 priorities before handing control to the SP.
722 #. Setting the return value of the handler to the per-cpu ``cpu_context`` if
723 the interrupt has been successfully validated and ready to be handled at a
727 secure state if it has been configured to do so. The SPD service and the SP
728 should implement a mechanism for routing these interrupts to the last known
729 exception level in the non-secure state. The former should save the SP context,
730 restore the non-secure context and arrange for entry into the non-secure state
731 so that the interrupt can be handled.
736 When the Secure Payload has finished handling a Secure-EL1 interrupt, it could
737 return control back to the SPD service through a SMC32 or SMC64. The SPD service
738 should handle this secure monitor call so that execution resumes in the
739 exception level and the security state from where the Secure-EL1 interrupt was
746 from the non-secure state. During execution in S-EL1, the TSPD expects that the
749 originating from the non-secure state. It takes the following actions upon being
752 #. It uses the security state provided in the ``flags`` parameter to ensure
753 that the secure interrupt originated from the non-secure state. It asserts
754 if this is not the case.
756 #. It saves the system register context for the non-secure state by calling
759 #. It sets the ``ELR_EL3`` system register to ``tsp_sel1_intr_entry`` and sets the
760 ``SPSR_EL3.DAIF`` bits in the secure CPU context. It sets ``x0`` to
761 ``TSP_HANDLE_SEL1_INTR_AND_RETURN``. If the TSP was preempted earlier by a non
762 secure interrupt during ``yielding`` SMC processing, save the registers that
763 will be trashed, which is the ``ELR_EL3`` and ``SPSR_EL3``, in order to be able
765 save any other secure context since the TSP is expected to preserve it
768 #. It restores the system register context for the secure state by calling
771 #. It ensures that the secure CPU context is used to program the next
774 #. It returns the per-cpu ``cpu_context`` to indicate that the interrupt can
775 now be handled by the SP. ``x1`` is written with the value of ``elr_el3``
776 register for the non-secure state. This information is used by the SP for
779 The figure below describes how the interrupt handling is implemented by the TSPD
780 when a Secure-EL1 interrupt is generated when execution is in the non-secure
785 The TSP issues an SMC with ``TSP_HANDLED_S_EL1_INTR`` as the function identifier to
788 The TSPD service takes the following actions in ``tspd_smc_handler()`` function
789 upon receiving an SMC with ``TSP_HANDLED_S_EL1_INTR`` as the function identifier:
791 #. It ensures that the call originated from the secure state otherwise
792 execution returns to the non-secure state with ``SMC_UNK`` in ``x0``.
794 #. It restores the saved ``ELR_EL3`` and ``SPSR_EL3`` system registers back to
795 the secure CPU context (see step 3 above) in case the TSP had been preempted
798 #. It restores the system register context for the non-secure state by
801 #. It ensures that the non-secure CPU context is used to program the next
804 #. ``tspd_smc_handler()`` returns a reference to the non-secure ``cpu_context``
805 as the return value.
813 cause preemption of TSP since there are no EL3 interrupts in the
816 It should be noted that while TSP is preempted, the TSPD only allows entry into
817 the TSP either for Secure-EL1 interrupt handling or for resuming the preempted
818 ``yielding`` SMC in response to the ``TSP_FID_RESUME`` SMC from the normal world.
823 ``TSP_NS_INTR_ASYNC_PREEMPT`` (see Section 2.2.2.1). If the build option is set,
824 the TSPD will set the routing model for the non-secure interrupt to be routed to
826 ``tspd_ns_interrupt_handler()`` as the non-secure interrupt handler. The
827 ``tspd_ns_interrupt_handler()`` on being invoked ensures that the interrupt
828 originated from the secure state and disables routing of non-secure interrupts
831 triggered while execution was in the normal world. The
835 If the ``TSP_NS_INTR_ASYNC_PREEMPT`` build option is zero (default), the default
837 i.e. **TEL3=0, CSS=0**. During ``yielding`` SMC processing, the IRQ
839 trigger at Secure-EL1 IRQ exception vector. The TSP saves the general purpose
840 register context and issues an SMC with ``TSP_PREEMPTED`` as the function
842 ``tspd_smc_handler()``, ensures that the SMC call originated from the
843 secure state otherwise execution returns to the non-secure state with
847 The ``tspd_handle_sp_preemption()`` takes the following actions upon being
850 #. It saves the system register context for the secure state by calling
853 #. It restores the system register context for the non-secure state by
856 #. It ensures that the non-secure CPU context is used to program the next
862 The Normal World is expected to resume the TSP after the ``yielding`` SMC preemption
863 by issuing an SMC with ``TSP_FID_RESUME`` as the function identifier (see section 3).
864 The TSPD service takes the following actions in ``tspd_smc_handler()`` function
867 #. It ensures that the call originated from the non secure state. An
870 #. Checks whether the TSP needs a resume i.e check if it was preempted. It
871 then saves the system register context for the non-secure state by calling
874 #. Restores the secure context by calling
877 #. It ensures that the secure CPU context is used to program the next
880 #. ``tspd_smc_handler()`` returns a reference to the secure ``cpu_context`` as the
883 The figure below describes how the TSP/TSPD handle a non-secure interrupt when
884 it is generated during execution in the TSP with ``PSTATE.I`` = 0 when the
892 The SP should implement one or both of the synchronous and asynchronous
893 interrupt handling models depending upon the interrupt routing model it has
896 In the synchronous model, it should begin handling a Secure-EL1 interrupt after
897 receiving control from the SPD service at an entrypoint agreed upon during build
898 time or during the registration phase. Before handling the interrupt, the SP
900 normal execution in the SP later e.g. ``SPSR_EL1,``\ ELR\_EL1\`. After handling the
901 interrupt, the SP could return control back to the exception level and security
902 state where the interrupt was originally taken from. The SP should use an SMC32
903 or SMC64 to ask the SPD service to do this.
905 In the asynchronous model, the Secure Payload is responsible for handling
906 non-secure and Secure-EL1 interrupts at the IRQ and FIQ vectors in its exception
908 when a non-secure interrupt is generated, the SP should coordinate with the SPD
909 service to pass control back to the non-secure state in the last known exception
910 level. This will allow the non-secure interrupt to be handled in the non-secure
916 The TSPD hands control of a Secure-EL1 interrupt to the TSP at the
917 ``tsp_sel1_intr_entry()``. The TSP handles the interrupt while ensuring that the
922 #. Checks whether the interrupt is the secure physical timer interrupt. It
923 uses the platform API ``plat_ic_get_pending_interrupt_id()`` to get the
924 interrupt number. If it is not the secure physical timer interrupt, then
927 an SMC with ``TSP_PREEMPTED`` as the function identifier.
929 #. Handles the secure timer interrupt interrupt by acknowledging it using the
931 ``tsp_generic_timer_handler()`` to reprogram the secure physical generic
932 timer and calling the ``plat_ic_end_of_interrupt()`` platform API to signal
935 The TSP passes control back to the TSPD by issuing an SMC64 with
936 ``TSP_HANDLED_S_EL1_INTR`` as the function identifier.
938 The TSP handles interrupts under the asynchronous model as follows.
940 #. Secure-EL1 interrupts are handled by calling the ``tsp_common_int_handler()``
943 #. Non-secure interrupts are handled by by calling the ``tsp_common_int_handler()``
945 SMC64 with ``TSP_PREEMPTED`` as the function identifier. Execution resumes at
946 the instruction that follows this SMC instruction when the TSPD hands
947 control to the TSP in response to an SMC with ``TSP_FID_RESUME`` as the
948 function identifier from the non-secure state (see section 2.3.2.4).
957 interrupt and the execution can return to the non-secure world for handling
958 the interrupt (For details on ``yielding`` SMC refer `SMC calling convention`_).
959 In this case, the SMC call has not completed its execution and the execution
960 must return back to the secure payload to resume the preempted SMC call.
961 This can be achieved by issuing an SMC call which instructs to resume the
967 In the Test Secure Payload implementation, ``TSP_FID_RESUME`` is designated
968 as the resume SMC FID. It is important to note that ``TSP_FID_RESUME`` is a
971 assuming ``P.STATE.I=0`` in the non secure state :
977 /* The pending non-secure interrupt is handled by the interrupt handler
979 while (rc == SMC_PREEMPTED) { /* Check if the SMC call is preempted */
983 The ``TSP_YIELD_SMC_FID`` is any ``yielding`` SMC function identifier and the smc()
984 function invokes a SMC call with the required arguments. The pending non-secure
985 interrupt causes an IRQ exception and the IRQ handler registered at the
986 exception vector handles the non-secure interrupt and returns. The return value
987 from the SMC call is tested for ``SMC_PREEMPTED`` to check whether it is
988 preempted. If it is, then the resume SMC call ``TSP_FID_RESUME`` is issued. The
989 return value of the SMC call is tested again to check if it is preempted.
990 This is done in a loop till the SMC call succeeds or fails. If a ``yielding``
992 completed, the current TSPD prevents any other SMC call from re-entering