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15 Please note that this document has been updated for the new platform API
16 as required by the PSCI v1.0 implementation. Please refer to the
17 `Migration Guide`_ for the previous platform API.
19 Porting the ARM Trusted Firmware to a new platform involves making some
20 mandatory and optional modifications for both the cold and warm boot paths.
24 - Setting up the execution context in a certain way, or
29 of variables and functions to fulfill the optional requirements. These
30 implementations are all weakly defined; they are provided to ease the porting
31 effort. Each platform port can override them with its own implementation if the
35 FVP and Juno) may also use `include/plat/arm/common/plat\_arm.h`_ and the
37 implementations for some of the required platform porting functions. However,
38 using these functions requires the platform port to implement additional
43 discusses these in detail. The subsequent sections discuss the remaining
46 This document should be read in conjunction with the ARM Trusted Firmware
52 This section covers the modifications that should be made by the platform for
53 each BL stage to correctly port the firmware stack. They are categorized as
59 A platform port must enable the Memory Management Unit (MMU) as well as the
60 instruction and data caches for each BL stage. Setting up the translation
61 tables is the responsibility of the platform port because memory maps differ
70 Also, the only translation granule size supported in Trusted Firmware is 4KB, as
71 various parts of the code assume that is the case. It is not possible to switch
72 to 16 KB or 64 KB granule sizes at the moment.
74 In ARM standard platforms, each BL stage configures the MMU in the
78 If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a
83 possible for the firmware to place variables in it using the following C code
90 Or alternatively the following assembler code directive:
101 The following variables, functions and constants must be defined by the platform
102 for the firmware to work correctly.
107 Each platform must ensure that a header file of this name is in the system
108 include path with the following constants defined. This may require updating the
109 list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. In the ARM development
112 Platform ports may optionally use the file `include/plat/common/common\_def.h`_,
113 which provides typical values for some of the constants below. These values are
118 standard values for some of the constants below. However, this requires the
124 Defines the linker format used by the platform, for example
129 Defines the processor architecture for the linker by the platform, for
134 Defines the normal stack memory available to each CPU. This constant is used
140 Defines the size in bits of the largest cache line across all the cache
141 levels in the platform.
145 Defines the character string printed by BL1 upon entry into the ``bl1_main()``
150 Defines the total number of CPUs implemented by the platform across all
151 clusters in the system.
155 Defines the total number of nodes in the power domain topology
156 tree at all the power domain levels used by the platform.
157 This macro is used by the PSCI implementation to allocate
162 Defines the maximum power domain level that the power management operations
163 should apply to. More often, but not always, the power domain level
164 corresponds to affinity level. This macro allows the PSCI implementation
165 to know the highest power domain level that it should consider for power
166 management operations in the system that the platform implements. For
167 example, the Base AEM FVP implements two clusters with a configurable
168 number of CPUs and it reports the maximum power domain level as 1.
172 Defines the local power state corresponding to the deepest power down
173 possible at every power domain level in the platform. The local power
175 with 0 being reserved for the RUN state. The PSCI implementation uses this
176 value to initialize the local power states of the power domain nodes and
177 to specify the requested power state for a PSCI\_CPU\_OFF call.
181 Defines the local power state corresponding to the deepest retention state
182 possible at every power domain level in the platform. This macro should be
183 a value less than PLAT\_MAX\_OFF\_STATE and greater than 0. It is used by the
189 Defines the maximum number of local power states per power domain level
190 that the platform supports. The default value of this macro is 2 since
192 power domain level (power-down and retention). If the platform needs to
195 Currently, this macro is used by the Generic PSCI implementation to size
196 the array used for PSCI\_STAT\_COUNT/RESIDENCY accounting.
200 Defines the base address in secure ROM where BL1 originally lives. Must be
205 Defines the maximum address in secure ROM that BL1's actual content (i.e.
210 Defines the base address in secure RAM where BL1's read-write data will live
215 Defines the maximum address in secure RAM that BL1's read-write data can
220 Defines the base address in secure RAM where BL1 loads the BL2 binary image.
225 Defines the maximum address in secure RAM that the BL2 image can occupy.
229 Defines the base address in secure RAM where BL2 loads the BL31 binary
234 Defines the maximum address in secure RAM that the BL31 image can occupy.
236 For every image, the platform must define individual identifiers that will be
237 used by BL1 or BL2 to load the corresponding image into memory from non-volatile
238 storage. For the sake of performance, integer numbers will be used as
239 identifiers. The platform will use those identifiers to return the relevant
240 information about the image to be loaded (file handler, load address,
256 If Trusted Board Boot is enabled, the following certificate identifiers must
261 BL2 content certificate identifier, used by BL1 to load the BL2 content
266 Trusted key certificate identifier, used by BL2 to load the trusted key
271 BL31 key certificate identifier, used by BL2 to load the BL31 key
276 BL31 content certificate identifier, used by BL2 to load the BL31 content
281 BL33 key certificate identifier, used by BL2 to load the BL33 key
286 BL33 content certificate identifier, used by BL2 to load the BL33 content
291 Firmware Update (FWU) certificate identifier, used by NS\_BL1U to load the
296 This defines the base address of ARM® TrustZone® CryptoCell and must be
301 If the AP Firmware Updater Configuration image, BL2U is used, the following
306 Defines the base address in secure memory where BL1 copies the BL2U binary
311 Defines the maximum address in secure memory that the BL2U image can occupy.
318 If the SCP Firmware Update Configuration Image, SCP\_BL2U is used, the following
327 If the Non-Secure Firmware Updater ROM, NS\_BL1U is used, the following must
332 Defines the base address in non-secure ROM where NS\_BL1U executes.
341 If the Non-Secure Firmware Updater, NS\_BL2U is used, the following must also
346 Defines the base address in non-secure memory where NS\_BL2U executes.
355 For the the Firmware update capability of TRUSTED BOARD BOOT, the following
360 Total number of images that can be loaded simultaneously. If the platform
363 If a SCP\_BL2 image is supported by the platform, the following constants must
369 from platform storage before being transfered to the SCP.
373 SCP\_BL2 key certificate identifier, used by BL2 to load the SCP\_BL2 key
378 SCP\_BL2 content certificate identifier, used by BL2 to load the SCP\_BL2
381 If a BL32 image is supported by the platform, the following constants must
390 BL32 key certificate identifier, used by BL2 to load the BL32 key
395 BL32 content certificate identifier, used by BL2 to load the BL32 content
400 Defines the base address in secure memory where BL2 loads the BL32 binary
405 Defines the maximum address that the BL32 image can occupy.
407 If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the
408 platform, the following constants must also be defined:
412 Defines the base address of the secure memory used by the TSP image on the
413 platform. This must be at the same address or below ``BL32_BASE``.
417 Defines the size of the secure memory used by the BL32 image on the
419 the memory required by the BL32 image, defined by ``BL32_BASE`` and
424 Defines the ID of the secure physical generic timer interrupt used by the
427 If the platform port uses the translation table library code, the following
432 Optional flag that can be set per-image to enable the dynamic allocation of
433 regions even when the MMU is enabled. If not defined, only static
435 include the dynamic functionality.
439 Defines the maximum number of translation tables that are allocated by the
440 translation table library code. To minimize the amount of runtime memory
441 used, choose the smallest value needed to map the required virtual addresses
443 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions
448 Defines the maximum number of regions that are allocated by the translation
451 defined in the ``mmap_region_t`` structure. The platform defines the regions
452 that should be mapped. Then, the translation table library will create the
453 corresponding tables and descriptors at runtime. To minimize the amount of
454 runtime memory used, choose the smallest value needed to register the
457 the dynamic regions as well.
461 Defines the total size of the address space in bytes. For example, for a 32
468 Defines the total size of the virtual address space in bytes. For example,
473 Defines the total size of the physical address space in bytes. For example,
476 If the platform port uses the IO storage framework, the following constants
481 Defines the maximum number of registered IO devices. Attempting to register
487 Defines the maximum number of open IO handles. Attempting to open more IO
492 Defines the maximum number of registered IO block devices. Attempting to
495 With this macro, multiple block devices could be supported at the same
498 If the platform needs to allocate data within the per-cpu data framework in
499 BL31, it should define the following macro. Currently this is only required if
500 the platform decides not to use the coherent memory section by undefining the
501 ``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
502 required memory within the the per-cpu data to minimize wastage.
506 Defines the memory (in bytes) to be reserved within the per-cpu data
507 structure for use by the platform layer.
509 The following constants are optional. They should be defined when the platform
514 Defines the maximum address in secure RAM that the BL31's progbits sections
519 Defines the maximum address that the TSP's progbits sections can occupy.
521 If the platform port uses the PL061 GPIO driver, the following constant may
525 Maximum number of GPIOs required by the platform. This allows control how
530 If the platform port uses the partition driver, the following constant may
534 Maximum number of partition entries required by the platform. This allows
537 `For example, define the build flag in platform.mk`_:
541 The following constant is optional. It should be defined to override the default
542 behaviour of the ``assert()`` function (for example, to save memory).
546 ``assert()`` prints the name of the file, the line number and the asserted
547 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file
548 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it
549 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't
555 Each platform must ensure a file of this name is in the system include path with
556 the following macro defined. In the ARM development platforms, this file is
561 This macro allows the crash reporting routine to print relevant platform
572 BL1 by default implements the reset vector where execution starts from a cold
573 or warm boot. BL31 can be optionally set as a reset vector using the
576 For each CPU, the reset vector code is responsible for the following tasks:
580 #. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
581 the CPU is placed in a platform-specific state until the primary CPU
582 performs the necessary steps to remove it from this state.
584 #. In the case of a warm boot, ensuring that the CPU jumps to a platform-
585 specific address in the BL31 image in the same processor mode as it was
588 The following functions need to be implemented by the platform port to enable
589 reset vector code to perform the above tasks.
599 This function is called with the MMU and caches disabled
601 distinguishing between a warm and cold reset for the current CPU using
602 platform-specific means. If it's a warm reset, then it returns the warm
606 This function does not follow the Procedure Call Standard used by the
607 Application Binary Interface for the ARM 64-bit architecture. The caller should
613 Note that for platforms that support programming the reset address, it is
614 expected that a CPU will start executing code directly at the right address,
615 both on a cold and warm reset. In this case, there is no need to identify the
616 type of reset nor to query the warm reset entrypoint. Therefore, implementing
626 This function is called with the MMU and data caches disabled. It is responsible
627 for placing the executing secondary CPU in a platform-specific state until the
628 primary CPU performs the necessary actions to bring it out of that state and
629 allow entry into the OS. This function must not return.
631 In the ARM FVP port, when using the normal boot flow, each secondary CPU powers
632 itself off. The primary CPU is responsible for powering up the secondary CPUs
639 Note that for platforms that can't release secondary CPUs out of reset, only the
640 primary CPU will execute the cold boot code. Therefore, implementing this
651 This function identifies whether the current CPU is the primary CPU or a
652 secondary CPU. A return value of zero indicates that the CPU is not the
653 primary CPU, while a non-zero return value indicates that the CPU is the
656 Note that for platforms that can't release secondary CPUs out of reset, only the
657 primary CPU will execute the cold boot code. Therefore, there is no need to
669 This function is called before any access to data is made by the firmware, in
681 pointer to the ROTPK stored in the platform (or a hash of it) and its length.
682 The ROTPK must be encoded in DER format according to the following ASN.1
697 In case the function returns a hash of the key:
706 The function returns 0 on success. Any other value is treated as error by the
708 to the ROTPK in the flags parameter:
712 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a
714 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK
715 verification while the platform ROTPK is not deployed.
716 When this flag is set, the function does not need to
717 return a platform ROTPK, and the authentication
718 framework uses the ROTPK in the certificate without
719 verifying it against the platform value. This flag
730 This function is mandatory when Trusted Board Boot is enabled. It returns the
731 non-volatile counter value stored in the platform in the second argument. The
732 cookie in the first argument may be used to select the counter in case the
733 platform provides more than one (for example, on platforms that use the default
734 TBBR CoT, the cookie will correspond to the OID values defined in
737 The function returns 0 on success. Any other value means the counter value could
738 not be retrieved from the platform.
749 counter value in the platform. The cookie in the first argument may be used to
750 select the counter (as explained in plat\_get\_nv\_ctr()). The second argument is
751 the updated counter value to be written to the NV counter.
753 The function returns 0 on success. Any other value means the counter value could
769 descriptor and may be used to decide if the counter is allowed to be
770 updated or not. The third argument is the updated counter value to
771 be written to the NV counter.
773 The function returns 0 on success. Any other value means the counter value
774 either could not be updated or the authentication image descriptor indicates
781 by the platform port.
791 This funtion returns the index of the calling CPU which is used as a
793 per-CPU stacks). This function will be invoked very early in the
795 implemented in assembly and should not rely on the avalability of a C
799 This function plays a crucial role in the power domain topology framework in
810 This function validates the ``MPIDR`` of a CPU and converts it to an index,
812 case the ``MPIDR`` is invalid, this function returns -1. This function will only
813 be invoked by BL31 after the power domain topology is initialized and can
814 utilize the C runtime environment. For further details about how ARM Trusted
815 Firmware represents the power domain topology and how this relates to the
821 The following are helper functions implemented by the firmware that perform
833 This function sets the current stack pointer to the normal memory stack that
834 has been allocated for the current CPU. For BL images that only require a
835 stack for the primary CPU, the UP version of the function is used. The size
836 of the stack allocated to each CPU is specified by the platform defined
839 Common implementations of this function for the UP and MP BL images are
851 This function returns the base address of the normal memory stack that
852 has been allocated for the current CPU. For BL images that only require a
853 stack for the primary CPU, the UP version of the function is used. The size
854 of the stack allocated to each CPU is specified by the platform defined
857 Common implementations of this function for the UP and MP BL images are
870 exception is taken, for example the current exception level, the CPU security
871 state (secure/non-secure), the exception type, and so on. This function is
872 called in the following circumstances:
878 about the way the platform displays its status information.
880 For AArch64, this function receives the exception type as its argument.
881 Possible values for exceptions types are listed in the
886 For AArch32, this function receives the exception mode as its argument.
887 Possible values for exception modes are listed in the
899 allows the platform to do the platform specific intializations. Platform
901 preserve the values of callee saved registers x19 to x29.
904 the default implementation, refer to the `Firmware Design`_ for general
915 This api allows a platform to disable the Accelerator Coherency Port (if
917 doesn't do anything. Since this api is called during the power down sequence,
918 it has restrictions for stack usage and it can use the registers x0 - x17 as
919 scratch registers. It should preserve the value in x18 register as it is used
920 by the caller to store the return address.
930 This API is called when the generic code encounters an error situation from
931 which it cannot continue. It allows the platform to perform error reporting or
932 recovery actions (for example, reset the system). This function must not return.
934 The parameter indicates the type of error using standard codes from ``errno.h``.
935 Possible errors reported by the generic code are:
939 - ``-ENOENT``: the requested image or certificate could not be found or an IO
954 This API is called when the generic code encounters an unexpected error
956 and must be implemented in assembly because it may be called before the C
970 This function returns pointer to the list of images that the platform has
971 populated to load. This function is currently invoked in BL2 to load the
982 This function returns a pointer to the shared memory that the platform has
985 the next BL image, when LOAD\_IMAGE\_V2 is enabled.
995 This function returns a random value that is used to initialize the canary used
996 when the stack protector is enabled with ENABLE\_STACK\_PROTECTOR. A predictable
997 value will weaken the protection as the attacker could easily write the right
998 value as part of the attack most of the time. Therefore, it should return a
1001 Note: For the protection to be effective, the global data need to be placed at
1002 a lower address than the stack bases. Failure to do so would allow an attacker
1003 to overwrite the canary as part of the stack buffer overflow attack.
1013 This function flushes to main memory all the image params that are passed to
1015 to the next BL image, when LOAD\_IMAGE\_V2 is enabled.
1025 This function defines the prefix string corresponding to the `log_level` to be
1026 prepended to all the log output from ARM Trusted Firmware. The `log_level`
1027 (argument) will correspond to one of the standard log levels defined in
1028 debug.h. The platform can override the common implementation to define a
1029 different prefix string for the log output. The implementation should be
1030 robust to future changes that increase the number of log levels.
1038 BL1 implements the reset vector where execution starts from after a cold or
1039 warm boot. For each CPU, BL1 is responsible for the following tasks:
1041 #. Handling the reset as described in section 2.2
1043 #. In the case of a cold boot and the CPU being the primary CPU, ensuring that
1044 only this CPU executes the remaining BL1 code, including loading and passing
1045 control to the BL2 stage.
1047 #. Identifying and starting the Firmware Update process (if required).
1049 #. Loading the BL2 image from non-volatile storage into secure memory at the
1050 address specified by the platform defined constant ``BL2_BASE``.
1052 #. Populating a ``meminfo`` structure with the following information in memory,
1063 BL1 places this ``meminfo`` structure at the beginning of the free memory
1064 available for its use. Since BL1 cannot allocate memory dynamically at the
1066 means that BL2 must read the ``meminfo`` structure before it starts using its
1069 In future releases of the ARM Trusted Firmware it will be possible for
1070 the platform to decide where it wants to place the ``meminfo`` structure for
1073 BL1 implements the ``bl1_init_bl2_mem_layout()`` function to populate the
1075 example if the platform wants to restrict the amount of memory visible to
1078 The following functions need to be implemented by the platform port to enable
1079 BL1 to perform the above tasks.
1089 This function executes with the MMU and data caches disabled. It is only called
1090 by the primary CPU.
1094 - Enables a secure instance of SP805 to act as the Trusted Watchdog.
1096 - Initializes a UART (PL011 console), which enables access to the ``printf``
1100 the CCI slave interface corresponding to the cluster that includes the
1111 This function performs any platform-specific and architectural setup that the
1113 memory controllers and the interconnect.
1115 In ARM standard platforms, this function enables the MMU.
1127 This function executes with the MMU and data caches enabled. It is responsible
1128 for performing any remaining platform-specific setup that can occur after the
1131 In ARM standard platforms, this function initializes the storage abstraction
1132 layer used to load the next bootloader image.
1144 This function should only be called on the cold boot path. It executes with the
1146 a ``meminfo`` structure containing the extents and availability of secure RAM for
1147 the BL1 stage.
1157 This information is used by BL1 to load the BL2 image in secure RAM. BL1 also
1158 populates a similar structure to tell BL2 the extents of memory available for
1171 BL1 needs to tell the next stage the amount of secure RAM available
1176 ``BL2_BASE``), BL1 calculates the amount of free memory available for BL2 to use.
1179 in the **Memory layout on ARM development platforms** section in the
1190 This function is called prior to exiting BL1 in response to the
1193 control to the next image. It receives the address of the ``entry_point_info_t``
1204 This function allows platforms to override ``ep_info`` for the given ``image_id``.
1216 This and the following function must be overridden to enable the FWU feature.
1218 BL1 calls this function after platform setup to identify the next image to be
1219 loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds
1220 with the normal boot sequence, which loads and executes BL2. If the platform
1225 if so, return the first image in the firmware update process.
1235 BL1 calls this function to get the image descriptor information ``image_desc_t``
1236 for the provided ``image_id`` from the platform.
1240 the firmware update images defined in the Trusted Board Boot Requirements
1252 BL1 calls this function when the FWU process is complete. It must not return.
1254 example to initiate the normal boot flow.
1268 copying or authenticating an image. Its responsibility is to ensure that the
1271 indicated by the security state of the ``flags`` argument.
1273 This function can safely assume that the value resulting from the addition of
1280 override it when using the FWU feature.
1285 The BL2 stage is executed only by the primary CPU, which is determined in BL1
1286 using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at
1289 #. (Optional) Loading the SCP\_BL2 binary image (if present) from platform
1290 provided non-volatile storage. To load the SCP\_BL2 image, BL2 makes use of
1291 the ``meminfo`` returned by the ``bl2_plat_get_scp_bl2_meminfo()`` function.
1292 The platform also defines the address in memory where SCP\_BL2 is loaded
1293 through the optional constant ``SCP_BL2_BASE``. BL2 uses this information
1294 to determine if there is enough memory to load the SCP\_BL2 image.
1295 Subsequent handling of the SCP\_BL2 image is platform-specific and is
1296 implemented in the ``bl2_plat_handle_scp_bl2()`` function.
1299 #. Loading the BL31 binary image into secure RAM from non-volatile storage. To
1300 load the BL31 image, BL2 makes use of the ``meminfo`` structure passed to it
1302 available for its use. The platform also defines the address in secure RAM
1303 where BL31 is loaded through the constant ``BL31_BASE``. BL2 uses this
1304 information to determine if there is enough memory to load the BL31 image.
1306 #. (Optional) Loading the BL32 binary image (if present) from platform
1307 provided non-volatile storage. To load the BL32 image, BL2 makes use of
1308 the ``meminfo`` returned by the ``bl2_plat_get_bl32_meminfo()`` function.
1309 The platform also defines the address in memory where BL32 is loaded
1310 through the optional constant ``BL32_BASE``. BL2 uses this information
1311 to determine if there is enough memory to load the BL32 image.
1312 If ``BL32_BASE`` is not defined then this and the next step is not performed.
1314 #. (Optional) Arranging to pass control to the BL32 image (if present) that
1316 structure in memory provided by the platform with information about how
1317 BL31 should pass control to the BL32 image.
1319 #. (Optional) Loading the normal world BL33 binary image (if not loaded by
1321 BL31 to pass control to this image. This address is determined using the
1324 #. BL2 populates an ``entry_point_info`` structure in memory provided by the
1325 platform with information about how BL31 should pass control to the
1328 The following functions must be implemented by the platform port to enable BL2
1329 to perform the above tasks.
1339 This function executes with the MMU and data caches disabled. It is only called
1340 by the primary CPU. The arguments to this function is the address of the
1343 The platform may copy the contents of the ``meminfo`` structure into a private
1344 variable as the original memory may be subsequently overwritten by BL2. The
1345 copied structure is made available to all BL2 code through the
1350 - Initializes a UART (PL011 console), which enables access to the ``printf``
1353 - Initializes the storage abstraction layer used to load further bootloader
1355 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded.
1365 This function executes with the MMU and data caches disabled. It is only called
1366 by the primary CPU.
1371 On ARM standard platforms, this function enables the MMU.
1381 This function may execute with the MMU and data caches enabled if the platform
1382 port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only
1383 called by the primary CPU.
1389 configuration of the TrustZone controller to allow non-secure masters access
1400 This function should only be called on the cold boot path. It may execute with
1401 the MMU and data caches enabled if the platform port does the necessary
1402 initialization in ``bl2_plat_arch_setup()``. It is only called by the primary CPU.
1405 populated with the extents of secure RAM available for BL2 to use. See
1418 This function can be used by the platforms to update/use image information
1420 BL image specific information based on the ``image_id`` passed, when
1433 This function is used to get the memory limits where BL2 can load the
1435 validate whether the SCP\_BL2 image can be loaded within the given
1436 memory from the given base.
1447 any platform-specific actions required to handle the SCP firmware. Typically it
1448 transfers the image into SCP memory using a platform-specific protocol and waits
1449 until SCP executes it and signals to the Application Processor (AP) for BL2
1464 the following information.
1465 - Header describing the version information for interpreting the bl31\_param
1467 - Information about executing the BL33 image in the ``bl33_ep_info`` field
1468 - Information about executing the BL32 image in the ``bl32_ep_info`` field
1469 - Information about the type and extents of BL31 image in the
1471 - Information about the type and extents of BL32 image in the
1473 - Information about the type and extents of BL33 image in the
1477 accessible from BL31 initialisation code. BL31 might choose to copy the
1478 necessary content, or maintain the structures until BL33 is initialised.
1488 BL2 platform code returns a pointer which is used to populate the entry point
1490 accessible from BL1 while processing the synchronous exception to run to BL31.
1503 In the normal boot flow, this function is called after loading BL31 image and
1504 it can be used to overwrite the entry point set by loader and also set the
1505 security state and SPSR which represents the entry point system state for BL31.
1508 its entry point address and can be used for the same purpose for the payload
1520 overwrite the entry point set by loader and also set the security state
1521 and SPSR which represents the entry point system state for BL32.
1532 overwrite the entry point set by loader and also set the security state
1533 and SPSR which represents the entry point system state for BL33.
1535 In the preloaded BL33 alternative boot flow, this function is called after
1547 This function is used to get the memory limits where BL2 can load the
1549 validate whether the BL32 image can be loaded with in the given
1550 memory from the given base.
1560 This function is used to get the memory limits where BL2 can load the
1562 validate whether the BL33 image can be loaded with in the given
1563 memory from the given base.
1576 Once BL2 has populated all the structures that needs to be read by BL1
1577 and BL31 including the bl31\_params structures and its sub-structures,
1578 the bl31\_ep\_info structure and any platform specific data. It flushes
1579 all these data to the main memory so that it is available when we jump to
1591 passed to a normal world BL image through BL31. This function returns the
1594 BL2 is responsible for loading the normal world BL33 image (e.g. UEFI).
1609 boot sources is required, it initializes the boot sequence used by
1619 This optional function passes to the next boot source in the redundancy
1622 This function moves the current boot redundancy source to the next
1623 element in the boot sequence. If there are no more boot sources then it
1630 The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU
1631 process and is executed only by the primary CPU. BL1 passes control to BL2U at
1634 #. (Optional) Transfering the optional SCP\_BL2U binary image from AP secure
1635 memory to SCP RAM. BL2U uses the SCP\_BL2U ``image_info`` passed by BL1.
1636 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP\_BL2U
1637 should be copied from. Subsequent handling of the SCP\_BL2U image is
1638 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function.
1641 #. Any platform specific setup required to perform the FWU process. For
1642 example, ARM standard platforms initialize the TZC controller so that the
1645 The following functions must be implemented by the platform port to enable
1646 BL2U to perform the tasks mentioned above.
1656 This function executes with the MMU and data caches disabled. It is only
1657 called by the primary CPU. The arguments to this function is the address
1658 of the ``meminfo`` structure and platform specific info provided by BL1.
1660 The platform may copy the contents of the ``mem_info`` and ``plat_info`` into
1661 private storage as the original memory may be subsequently overwritten by BL2U.
1675 This function executes with the MMU and data caches disabled. It is only
1676 called by the primary CPU.
1679 that varies across platforms, for example enabling the MMU (since the memory
1690 This function may execute with the MMU and data caches enabled if the platform
1691 port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only
1692 called by the primary CPU.
1698 configuration of the TrustZone controller to allow non-secure masters access
1710 handle the SCP firmware. Typically it transfers the image into SCP memory using
1711 a platform-specific protocol and waits until SCP executes it and signals to the
1720 During cold boot, the BL31 stage is executed only by the primary CPU. This is
1721 determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes
1728 should make no assumptions about the system state when it receives control.
1731 specific address by BL2. BL31 uses the ``entry_point_info`` structure that BL2
1735 subset of the Power State Coordination Interface (PSCI) API as a runtime
1736 service. See Section 3.3 below for details of porting the PSCI
1739 #. Optionally passing control to the BL32 image, pre-loaded at a platform-
1741 services to specify the security state in which the next image should be
1742 executed and run the corresponding image. BL31 uses the ``entry_point_info``
1745 If BL31 is a reset vector, It also needs to handle the reset as specified in
1746 section 2.2 before the tasks described above.
1748 The following functions must be implemented by the platform port to enable BL31
1749 to perform the above tasks.
1759 This function executes with the MMU and data caches disabled. It is only called
1760 by the primary CPU. The arguments to this function are:
1762 - The address of the ``bl31_params`` structure populated by BL2.
1763 - An opaque pointer that the platform may use as needed.
1765 The platform can copy the contents of the ``bl31_params`` structure and its
1766 sub-structures into private variables if the original memory may be
1767 subsequently overwritten by BL31 and similarly the ``void *`` pointing
1768 to the platform data also needs to be saved.
1771 in BL2 memory. BL31 copies the information in this pointer to internal data
1772 structures. It also performs the following:
1774 - Initialize a UART (PL011 console), which enables access to the ``printf``
1777 - Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the
1778 CCI slave interface corresponding to the cluster that includes the primary
1789 This function executes with the MMU and data caches disabled. It is only called
1790 by the primary CPU.
1795 On ARM standard platforms, this function enables the MMU.
1805 This function may execute with the MMU and data caches enabled if the platform
1806 port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only
1807 called by the primary CPU.
1812 On ARM standard platforms, this function does the following:
1814 - Initialize the generic interrupt controller.
1816 Depending on the GIC driver selected by the platform, the appropriate GICv2
1819 - Enable secure interrupts in the GIC CPU interface.
1820 - Disable the legacy interrupt bypass mechanism.
1821 - Configure the priority mask register to allow interrupts of all priorities
1822 to be signaled to the CPU interface.
1823 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure.
1825 - Enable these secure interrupts in the GIC distributor.
1827 - Enable signaling of secure interrupts in the GIC distributor.
1829 - Enable system-level implementation of the generic timer counter through the
1832 - Grant access to the system counter timer module
1834 - Initialize the power controller device.
1836 In particular, initialise the locks that prevent concurrent accesses to the
1847 The purpose of this function is allow the platform to perform any BL31 runtime
1852 In ARM Standard platforms, this function will initialize the BL31 runtime
1853 console which will cause all further BL31 logs to be output to the
1864 This function may execute with the MMU and data caches enabled if the platform
1865 port does the necessary initializations in ``bl31_plat_arch_setup()``.
1868 BL2 for the next image in the security state specified by the argument. BL31
1869 uses this information to pass control to that image in the specified security
1870 state. This function must return a pointer to the ``entry_point_info`` structure
1871 (that was copied during ``bl31_early_platform_setup()``) if the image exists. It
1882 This function is used by the architecture setup code to retrieve the counter
1883 frequency for the CPU's generic timer. This value will be programmed into the
1884 ``CNTFRQ_EL0`` register. In ARM standard platforms, it returns the base frequency
1885 of the system counter, which is retrieved from the first entry in the frequency
1891 When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in
1892 bytes) aligned to the cache line boundary that should be allocated per-cpu to
1893 accommodate all the bakery locks.
1895 If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker
1896 calculates the size of the ``bakery_lock`` input section, aligns it to the
1898 and stores the result in a linker symbol. This constant prevents a platform
1899 from relying on the linker and provide a more efficient mechanism for
1902 If this constant is defined and its value is not equal to the value
1903 calculated by the linker then a link time assertion is raised. A compile time
1904 assertion is raised if the value of the constant is not aligned to the cache
1910 The ARM Trusted Firmware's implementation of the PSCI API is based around the
1913 performed as specified by `PSCI`_. Each CPU in the system is assigned a cpu
1916 each *power domain* can be identified in a system by the cpu index of any CPU
1918 (for example, a CPU) is at level 0. If the *power domain* node above a CPU is
1921 (for example, the system). More details on the power domain topology and its
1924 BL31's platform initialization code exports a pointer to the platform-specific
1925 power management operations required for the PSCI implementation to function
1926 correctly. This information is populated in the ``plat_psci_ops`` structure. The
1927 PSCI implementation calls members of the ``plat_psci_ops`` structure for performing
1928 power management operations on the power domains. For example, the target
1930 handler (if present) is called for the CPU power domain.
1934 defines a generic representation of the power-state parameter viz which is an
1936 level. Each entry contains the local power state the power domain at that power
1937 level could enter. It depends on the ``validate_power_state()`` handler to
1938 convert the power-state parameter (possibly encoding a composite power state)
1954 differently at CPU level versus higher levels. As an example, if the element at
1955 index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
1956 state, special hardware logic may be programmed in order to keep track of the
1957 residency statistics. For higher levels (array indices > 0), the residency
1958 statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
1972 differently at CPU level versus higher levels. As an example, if the element at
1973 index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
1974 state, special hardware logic may be programmed in order to keep track of the
1975 residency statistics. For higher levels (array indices > 0), the residency
1976 statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
1988 state and provides the time spent resident in that low power state by the power
1992 identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second
1993 argument) describes the low power state that the power domain has resumed from.
1994 The current CPU is the first CPU in the power domain to resume from the low
1995 power state and the ``last_cpu_idx`` (third parameter) is the index of the last
1996 CPU in the power domain to suspend and may be needed to calculate the residency
2007 The PSCI generic code uses this function to let the platform participate in
2010 argument) which contains the requested power state for each CPU at a particular
2011 power domain level ``lvl`` (first argument) within the power domain. The function
2013 a coordinated target power state by the comparing all the requested power
2014 states. The target power state should not be deeper than any of the requested
2018 that the platform assigns a local state value in order of increasing depth
2019 of the power state i.e. for two power states X & Y, if X < Y
2020 then X represents a shallower power state than Y. As a result, the
2021 coordinated target local power state for a power domain will be the minimum
2022 of the requested local power state values.
2032 This function returns a pointer to the byte array containing the power domain
2035 requires this array to be described by the platform, either statically or
2036 dynamically, to initialize the power domain topology tree. In case the array
2038 plat\_my\_core\_pos() should also be implemented suitably so that the topology
2039 tree description matches the CPU indices returned by these APIs. These APIs
2040 together form the platform interface for the PSCI topology framework.
2050 This function may execute with the MMU and data caches enabled if the platform
2051 port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
2052 called by the primary CPU.
2055 the platform layer know about the warm boot entrypoint through the
2057 platform-specific psci power management actions by populating the passed
2061 the ARM FVP specific implementation of these handlers in
2062 `plat/arm/board/fvp/fvp\_pm.c`_ as an example. For each PSCI function that the
2063 platform wants to support, the associated operation or operations in this
2065 `Firmware Design`_ for the PSCI API supported in Trusted Firmware). To disable
2066 a PSCI function in a platform port, the operation should be removed from this
2072 Perform the platform-specific actions to enter the standby state for a cpu
2073 indicated by the passed argument. This provides a fast path for CPU standby
2075 For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation,
2076 the suspend state type specified in the ``power-state`` parameter should be
2077 STANDBY and the target power domain level specified should be the CPU. The
2078 handler should put the CPU into a low power retention state (usually by
2080 state by a normal interrupt. The generic code expects the handler to succeed.
2085 Perform the platform specific actions to power on a CPU, specified
2086 by the ``MPIDR`` (first argument). The generic code expects the platform to
2092 Perform the platform specific actions to prepare to power off the calling CPU
2093 and its higher parent power domain levels as indicated by the ``target_state``
2094 (first argument). It is called by the PSCI ``CPU_OFF`` API implementation.
2096 The ``target_state`` encodes the platform coordinated target local power states
2097 for the CPU power domain and its parent power domain levels. The handler
2098 needs to perform power management operation corresponding to the local state
2101 For this handler, the local power state for the CPU power domain will be a
2103 for the higher power domain levels depending on the result of state
2104 coordination. The generic code expects the handler to succeed.
2111 are identical to pwr_domain_suspend(), except the PSCI implementation only
2115 When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches
2116 before calling pwr_domain_suspend(). If the target_state corresponds to a
2117 power down state and it is safe to perform some or all of the platform
2126 Perform the platform specific actions to prepare to suspend the calling
2127 CPU and its higher parent power domain levels as indicated by the
2128 ``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND``
2132 the ``pwr_domain_off()`` operation. It encodes the platform coordinated
2133 target local power states for the CPU power domain and its parent
2135 corresponding to the local state at each power level. The generic code
2136 expects the handler to succeed.
2139 in the former case, the power domain is expected to re-initialize its state
2140 when it is next powered on (see ``pwr_domain_on_finish()``). In the latter
2141 case, the power domain is expected to save enough state so that it can resume
2145 When suspending a core, the platform can also choose to power off the GICv3
2147 this safely, the ITS context must be saved first. The architectural part is
2148 implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed
2149 sequence is implementation defined and it is therefore the responsibility of
2150 the platform code to implement the necessary sequence. Then the GIC
2151 Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper.
2152 Powering off the Redistributor requires the implementation to support it and it
2153 is the responsibility of the platform code to execute the right implementation
2156 When a system suspend is requested, the platform can also make use of the
2157 ``gicv3_distif_save()`` helper to save the context of the GIC Distributor after
2158 it has saved the context of the Redistributors and ITS of all the cores in the
2159 system. The context of the Distributor can be large and may require it to be
2160 allocated in a special area if it cannot fit in the platform's global static
2168 platform specific actions including the ``wfi`` invocation which allows the
2169 CPU to powerdown. Since this function is invoked outside the PSCI locks,
2170 the actions performed in this hook must be local to the CPU or the platform
2173 The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()``
2174 operation and it encodes the platform coordinated target local power states for
2175 the CPU power domain and its parent power domain levels. This function must
2176 not return back to the caller.
2178 If this function is not implemented by the platform, PSCI generic
2184 This function is called by the PSCI implementation after the calling CPU is
2186 It performs the platform-specific setup required to initialize enough state for
2187 this CPU to enter the normal world and also provide secure runtime firmware
2190 The ``target_state`` (first argument) is the prior state of the power domains
2191 immediately before the CPU was turned on. It indicates which power domains
2192 above the CPU might require initialization due to having previously been in
2193 low power states. The generic code expects the handler to succeed.
2198 This function is called by the PSCI implementation after the calling CPU is
2200 event, for example a timer interrupt that was programmed by the CPU during the
2201 ``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
2202 setup required to restore the saved state for this CPU to resume execution
2203 in the normal world and also provide secure runtime firmware services.
2206 the ``pwr_domain_on_finish()`` operation. The generic code expects the platform
2209 If the Distributor, Redistributors or ITS have been powered off as part of a
2210 suspend, their context must be restored in this function in the reverse order
2217 call. It performs the platform-specific system poweroff sequence after
2218 notifying the Secure Payload Dispatcher.
2224 call. It performs the platform-specific system reset sequence after
2225 notifying the Secure Payload Dispatcher.
2230 This function is called by the PSCI implementation during the ``CPU_SUSPEND``
2231 call to validate the ``power_state`` parameter of the PSCI API and if valid,
2233 specific local states. If the ``power_state`` is invalid, the platform must
2234 return PSCI\_E\_INVALID\_PARAMS as error, which is propagated back to the
2240 This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
2241 ``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point``
2242 parameter passed by the normal world. If the ``entry_point`` is invalid,
2243 the platform must return PSCI\_E\_INVALID\_ADDRESS as error, which is
2244 propagated back to the normal world PSCI client.
2249 This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
2250 call to get the ``req_state`` parameter from platform which encodes the power
2252 ``req_state`` will be utilized to do the PSCI state coordination and
2253 ``pwr_domain_suspend()`` will be invoked with the coordinated target state to
2259 This is an optional function and, if implemented, is invoked by the PSCI
2260 implementation to convert the ``local_state`` (first argument) at a specified
2262 ``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform
2270 This is an optional function and, if implemented, verifies the ``power_state``
2271 (second argument) parameter of the PSCI API corresponding to a target power
2273 argument) and the power domain level encoded in ``power_state``. The power domain
2275 populated in the ``output_state`` (third argument) array. The functionality
2276 is similar to the ``validate_power_state`` function described above and is
2277 envisaged to be used in case the validity of ``power_state`` depend on the
2278 targeted power domain. If the ``power_state`` is invalid for the targeted power
2279 domain, the platform must return PSCI\_E\_INVALID\_PARAMS as error. If this
2280 function is not implemented, then the generic implementation relies on
2281 ``validate_power_state`` function to translate the ``power_state``.
2283 This function can also be used in case the platform wants to support local
2291 the power state of a node (identified by the first parameter, the ``MPIDR``) in
2292 the power domain topology (identified by the second parameter, ``power_level``),
2293 as retrieved from a power controller or equivalent component on the platform.
2294 Upon successful completion, the implementation must map and return the final
2306 called during the ``SYSTEM_RESET2`` call to perform a reset
2307 based on the first parameter ``reset_type`` as specified in
2309 reset information. If the ``reset_type`` is not supported, the
2318 This is an optional function. If implemented it enables or disables the
2319 ``MEM_PROTECT`` functionality based on the value of ``val``.
2327 This is an optional function. If implemented it returns the current
2328 state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering
2337 bytes is protected by ``MEM_PROTECT``. If the region is protected
2344 generated in either security state and targeted to EL1 or EL2 in the non-secure
2345 state or EL3/S-EL1 in the secure state. The design of this framework is
2346 described in the `IMF Design Guide`_
2348 A platform should export the following APIs to support the IMF. The following
2350 platforms. The API implementation depends upon the type of interrupt controller
2351 present in the platform. ARM standard platform layer supports both
2353 and `3.0 (GICv3)`_. Juno builds the ARM
2354 Standard layer to use GICv2 and the FVP can be configured to use either GICv2 or
2355 GICv3 depending on the build flag ``FVP_USE_GIC_DRIVER`` (See FVP platform
2370 The ARM processor signals an interrupt exception either through the IRQ or FIQ
2371 interrupt line. The specific line that is signaled depends on how the interrupt
2374 the platform IC uses to signal each type of interrupt supported by the framework
2377 The first parameter will be one of the ``INTR_TYPE_*`` values (see
2378 `IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the
2379 security state of the originating execution context. The return result is the
2380 bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1,
2383 In the case of ARM standard platforms using GICv2, S-EL1 interrupts are
2387 In the case of ARM standard platforms using GICv3, the interrupt line to be
2388 configured depends on the security state of the execution context when the
2394 in the NS-EL0/1/2 context.
2406 This API returns the type of the highest priority pending interrupt at the
2407 platform IC. The IMF uses the interrupt type to retrieve the corresponding
2412 In the case of ARM standard platforms using GICv2, the *Highest Priority
2413 Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of
2414 the pending interrupt. The type of interrupt depends upon the id value as
2421 In the case of ARM standard platforms using GICv3, the system register
2423 is read to determine the id of the pending interrupt. The type of interrupt
2424 depends upon the id value as follows.
2439 This API returns the id of the highest priority pending interrupt at the
2443 In the case of ARM standard platforms using GICv2, the *Highest Priority
2444 Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the
2445 pending interrupt. The id that is returned by API depends upon the value of
2446 the id read from the interrupt controller as follows.
2450 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt.
2451 This id is returned by the API.
2454 In the case of ARM standard platforms using GICv3, if the API is invoked from
2455 EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt
2456 group 0 Register*, is read to determine the id of the pending interrupt. The id
2457 that is returned by API depends upon the value of the id read from the
2463 Register* is read to determine the id of the group 1 interrupt. This id
2464 is returned by the API as long as it is a valid interrupt id
2465 #. If the id is any of the special interrupt identifiers,
2468 When the API invoked from S-EL1 for GICv3 systems, the id read from system
2481 This API is used by the CPU to indicate to the platform IC that processing of
2482 the highest pending interrupt has begun. It should return the id of the
2485 This function in ARM standard platforms using GICv2, reads the *Interrupt
2486 Acknowledge Register* (``GICC_IAR``). This changes the state of the highest
2487 priority pending interrupt from pending to active in the interrupt controller.
2488 It returns the value read from the ``GICC_IAR``. This value is the id of the
2491 In the case of ARM standard platforms using GICv3, if the API is invoked
2492 from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt
2493 Acknowledge Register group 0*. If the API is invoked from S-EL1, the function
2494 reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register
2495 group 1*. The read changes the state of the highest pending interrupt from
2496 pending to active in the interrupt controller. The value read is returned
2497 and is the id of the interrupt whose state has been changed.
2499 The TSP uses this API to start processing of the secure physical timer
2510 This API is used by the CPU to indicate to the platform IC that processing of
2511 the interrupt corresponding to the id (passed as the parameter) has
2512 finished. The id should be the same as the id returned by the
2515 ARM standard platforms write the id to the *End of Interrupt Register*
2517 system register in case of GICv3 depending on where the API is invoked from,
2518 EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt
2521 The TSP uses this API to finish processing of the secure physical timer
2532 This API returns the type of the interrupt id passed as the parameter.
2533 ``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid
2535 returned depending upon how the interrupt has been configured by the platform
2539 and Non-secure interrupts as Group1 interrupts. It reads the group value
2540 corresponding to the interrupt id from the relevant *Interrupt Group Register*
2541 (``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt.
2543 In the case of ARM standard platforms using GICv3, both the *Interrupt Group
2545 (``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured
2551 BL31 implements a crash reporting mechanism which prints the various registers
2552 of the CPU to enable quick crash analysis and debugging. It requires that a
2553 console is designated as the crash console by the platform which will be used to
2554 print the register dump.
2556 The following functions must be implemented by the platform if it wants crash
2568 This API is used by the crash reporting mechanism to initialize the crash
2569 console. It must only use the general purpose registers x0 to x4 to do the
2580 This API is used by the crash reporting mechanism to print a character on the
2582 x2 to do its work. The parameter and the return value are in general purpose
2593 This API is used by the crash reporting mechanism to force write of all buffered
2594 data on the designated crash console. It should only use general purpose
2596 completion; otherwise the return value is -1.
2602 All the platforms ports conforming to this API specification should define
2603 the build flag ``ENABLE_PLAT_COMPAT`` to 0 as the compatibility layer should
2607 There are some build flags which can be defined by the platform to control
2608 inclusion or exclusion of certain BL stages from the FIP image. These flags
2609 need to be defined in the platform makefile which will get included by the
2613 By default, this flag is defined ``yes`` by the build system and ``BL33``
2614 build option should be supplied as a build option. The platform has the
2615 option of excluding the BL33 image in the ``fip`` image by defining this flag
2616 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE``
2622 To avoid subtle toolchain behavioral dependencies, the header files provided
2623 by the compiler are not used. The software is built with the ``-nostdinc`` flag
2624 to ensure no headers are included from the toolchain inadvertently. Instead the
2625 required headers are included in the ARM Trusted Firmware source tree. The
2626 library only contains those C library definitions required by the local
2627 implementation. If more functionality is required, the needed library functions
2628 will need to be added to the local implementation.
2631 these headers have been cut down in order to simplify the implementation. In
2632 order to minimize changes to the header files, the `FreeBSD`_ layout has been
2638 extend the C library these files may need to be modified. It is recommended to
2641 The C library header files in the `FreeBSD`_ source tree are located in the
2643 can be found in the ``sys/<machine-type>`` directories. These files define things
2644 like 'the size of a pointer' and 'the range of an integer'. Since an AArch64
2645 port for `FreeBSD`_ does not yet exist, the machine specific definitions are
2649 as found in the ``lib/libc`` directory.
2651 A copy of the `FreeBSD`_ sources can be downloaded with ``git``.
2663 Each platform should register devices and their drivers via the Storage layer.
2667 function uses the storage layer to access non-volatile platform storage.
2669 It is mandatory to implement at least one storage driver. For the ARM
2670 development platforms the Firmware Image Package (FIP) driver is provided as
2671 the default means to load data from storage (see the "Firmware Image Package"
2672 section in the `User Guide`_). The storage layer is described in the header file
2673 ``include/drivers/io/io_storage.h``. The implementation of the common library
2674 is in ``drivers/io/io_storage.c`` and the driver files are located in
2683 IO operations are called. The basic operations supported by the layer
2689 The current implementation only allows for known images to be loaded by the
2693 to a device and a driver-specific ``spec`` which will be understood by the driver
2694 to allow access to the image data.
2699 drivers. In such a case, the file-system "binding" with the block device may
2700 be deferred until the file-system device is initialised.
2703 by the drivers and callers, as the system does not yet provide a means of
2704 dynamically allocating memory. This may also have the affect of limiting the
2719 .. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160