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10 This document describes the high-level design of the framework to handle CPU
11 resets in ARM Trusted Firmware. It also describes how the platform integrator
12 can tailor this code to the system configuration to some extent, resulting in a
15 This document should be used in conjunction with the `Firmware Design`_, which
16 provides greater implementation details around the reset code, specifically
17 for the cold boot path.
27 This diagram shows the default, unoptimised reset flow. Depending on the system
29 guide the platform integrator by indicating which build options exclude which
30 steps, depending on the capability of the platform.
32 Note: If BL31 is used as the Trusted Firmware entry point instead of BL1, the
34 this case. Please refer to section 6 "Using BL31 entrypoint as the reset
40 By default, the TF assumes that the CPU reset address is not programmable.
41 Therefore, all CPUs start at the same address (typically address 0) whenever
43 warm boot to direct CPUs to the right execution path.
45 If the reset vector address (reflected in the reset vector base address register
47 at the right address, both on a cold and warm reset. Therefore, the boot type
48 detection can be skipped, resulting in the following boot flow:
52 To enable this boot flow, compile the TF with ``PROGRAMMABLE_RESET_ADDRESS=1``.
53 This option only affects the TF reset image, which is BL1 by default or BL31 if
56 On both the FVP and Juno platforms, the reset vector address is not programmable
62 By default, the TF assumes that several CPUs may be released out of reset.
63 Therefore, the cold boot code has to arbitrate access to hardware resources
64 shared amongst CPUs. This is done by nominating one of the CPUs as the primary,
65 which is responsible for initialising shared hardware and coordinating the boot
66 flow with the other CPUs.
68 If the platform guarantees that only a single CPU will ever be brought up then
70 applies. This results in the following boot flow:
74 To enable this boot flow, compile the TF with ``COLD_BOOT_SINGLE_CPU=1``. This
75 option only affects the TF reset image, which is BL1 by default or BL31 if
78 On both the FVP and Juno platforms, although only one core is powered up by
87 This results in the following boot flow:
92 To enable this boot flow, compile the TF with both ``COLD_BOOT_SINGLE_CPU=1``
93 and ``PROGRAMMABLE_RESET_ADDRESS=1``. These options only affect the TF reset
96 Using BL31 entrypoint as the reset address
99 On some platforms the runtime firmware (BL3x images) for the application
101 on the SoC, rather than by BL1 and BL2 running on the primary application
102 processor. For this type of SoC it is desirable for the application processor
103 to always reset to BL31 which eliminates the need for BL1 and BL2.
106 logic in the BL31 entry point to support this use case.
108 In this configuration, the platform's Trusted Boot Firmware must ensure that
109 BL31 is loaded to its runtime address, which must match the CPU's ``RVBAR_EL3``
110 reset vector base address, before the application processor is powered on.
111 Additionally, platform software is responsible for loading the other BL3x images
113 images might be done by the Trusted Boot Firmware or by platform code in BL31.
115 Although the ARM FVP platform does not support programming the reset base
116 address dynamically at run-time, it is possible to set the initial value of the
117 ``RVBAR_EL3`` register at start-up. This feature is provided on the Base FVP only.
118 It allows the ARM FVP port to support the ``RESET_TO_BL31`` configuration, in
119 which case the ``bl31.bin`` image must be loaded to its run address in Trusted
120 SRAM and all CPU reset vectors be changed from the default ``0x0`` to this run
121 address. See the `User Guide`_ for details of running the FVP models in this way.
123 Although technically it would be possible to program the reset base address with
124 the right support in the SCP firmware, this is currently not implemented so the
125 Juno port doesn't support the ``RESET_TO_BL31`` configuration.
127 The ``RESET_TO_BL31`` configuration requires some additions and changes in the
133 In this configuration, BL31 uses the same reset framework and code as the one
134 described for BL1 above. Therefore, it is affected by the
135 ``PROGRAMMABLE_RESET_ADDRESS`` and ``COLD_BOOT_SINGLE_CPU`` build options in the
138 In the default, unoptimised BL31 reset flow, on a warm boot a CPU is directed
139 to the PSCI implementation via a platform defined mechanism. On a cold boot,
140 the platform must place any secondary CPUs into a safe state while the primary
146 In this configuration, when the CPU resets to BL31 there are no parameters that
147 can be passed in registers by previous boot stages. Instead, the platform code
148 in BL31 needs to know, or be able to determine, the location of the BL32 (if
149 required) and BL33 images and provide this information in response to the
154 This might be done by the Trusted Boot Firmware or by platform code in BL31.