Lines Matching refs:the
11 tested set of other software components using defined configurations on the Juno
14 is outside the scope of this document.
16 This document assumes that the reader has previous experience running a fully
17 bootable Linux software stack on Juno or FVP using the prebuilt binaries and
18 filesystems provided by `Linaro`_. Further information may be found in the
19 `Linaro instructions`_. It also assumes that the user understands the role of
20 the different software components required to boot a Linux system:
22 - Specific firmware images required by the platform (e.g. SCP firmware on Juno)
28 This document also assumes that the user is familiar with the `FVP models`_ and
29 the different command line options available to launch the model.
31 This document should be used in conjunction with the `Firmware Design`_.
36 The minimum recommended machine specification for building the software and
37 running the FVP models is a dual-core processor running at 2GHz with 12GB of
42 building the software were installed from that distribution unless otherwise
46 Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
51 Install the required packages to build Trusted Firmware with the following
60 Download and install the AArch32 or AArch64 little-endian GCC cross compiler.
61 The `Linaro Release Notes`_ documents which version of the compiler to use for a
67 See instructions below on how to switch the default compiler.
69 In addition, the following optional packages and tools may be needed:
71 - ``device-tree-compiler`` package if you need to rebuild the Flattened Device
76 - To create and modify the diagram files included in the documentation, `Dia`_.
78 generate the actual *.png files.
80 Getting the Trusted Firmware source code
83 Download the Trusted Firmware source code from Github:
89 Building the Trusted Firmware
92 - Before building Trusted Firmware, the environment variable ``CROSS_COMPILE``
93 must point to the Linaro cross compiler.
108 To do so ``CC`` needs to point to the clang or armclang binary. Only the
109 compiler is switched; the assembler and linker need to be provided by
110 the GNU toolchain, thus ``CROSS_COMPILE`` should be set as described above.
112 ARM Compiler 6 will be selected when the base name of the path assigned
113 to ``CC`` matches the string 'armclang'.
122 Clang will be selected when the base name of the path assigned to ``CC``
123 contains the string 'clang'. This is to allow both clang and clang-X.Y
133 - Change to the root directory of the Trusted Firmware source tree and build.
149 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
155 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
156 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp\_min, is
163 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
164 image, is not compiled in by default. Refer to the
165 `Building the Test Secure Payload`_ section below.
167 - By default this produces a release version of the build. To produce a
168 debug version instead, refer to the "Debugging options" section below.
171 the objects and binaries for each boot loader stage in separate
173 from the corresponding ELF files:
180 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
182 depending on the platform.
201 ARM Trusted Firmware build system supports the following build options. Unless
202 mentioned otherwise, these options are expected to be specified at the build
204 the build system doesn't track dependency for build options. Therefore, if any
205 of the build options are changed from a previous build, a clean build must be
211 - ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
212 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
213 directory containing the SP source, relative to the ``bl32/``; the directory
216 - ``ARCH`` : Choose the target build architecture for ARM Trusted Firmware.
228 - ``ARM_GIC_ARCH``: Choice of ARM GIC architecture version used by the ARM
229 Legacy GIC driver for implementing the platform GIC API. This API is used
230 by the interrupt management framework. Default is 2 (that is, version 2.0).
233 - ``ARM_PLAT_MT``: This flag determines whether the ARM platform layer has to
234 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
235 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
236 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
239 - ``BL2``: This is an optional build option which specifies the path to BL2
240 image for the ``fip`` target. In this case, the BL2 in the ARM Trusted
243 - ``BL2U``: This is an optional build option which specifies the path to
244 BL2U image. In this case, the BL2U in the ARM Trusted Firmware will not
247 - ``BL31``: This is an optional build option which specifies the path to
248 BL31 image for the ``fip`` target. In this case, the BL31 in the ARM
251 - ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
252 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
253 this file name will be used to save the key.
255 - ``BL32``: This is an optional build option which specifies the path to
256 BL32 image for the ``fip`` target. In this case, the BL32 in the ARM
259 - ``BL32_EXTRA1``: This is an optional build option which specifies the path to
260 Trusted OS Extra1 image for the ``fip`` target.
262 - ``BL32_EXTRA2``: This is an optional build option which specifies the path to
263 Trusted OS Extra2 image for the ``fip`` target.
265 - ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
266 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
267 this file name will be used to save the key.
269 - ``BL33``: Path to BL33 image in the host file system. This is mandatory for
270 ``fip`` target in case the BL2 from ARM Trusted Firmware is used.
272 - ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
273 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
274 this file name will be used to save the key.
276 - ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
278 where applicable). Defaults to a string that contains the time and date of
279 the compilation.
281 - ``BUILD_STRING``: Input string for VERSION\_STRING, which allows the TF build
282 to be uniquely identified. Defaults to the current git commit id.
284 - ``CFLAGS``: Extra user options appended on the compiler's command line in
285 addition to the options set by the build system.
287 - ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
290 Default is 0. If the platform always brings up a single CPU, there is no
291 need to distinguish between primary and secondary CPUs and the boot path can
298 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
299 this is only enabled for a debug build of the firmware.
301 - ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
306 the AArch32 system registers to be included when saving and restoring the
311 - ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
312 registers to be included when saving and restoring the CPU context. Default
316 (release) or 1 (debug) as values. 0 is the default.
319 the normal boot flow. It must specify the entry point address of the EL3
320 payload. Please refer to the "Booting an EL3 payload" section for more
328 that is only required for the assertion and does not fit in the assertion
336 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
337 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
344 the ``ENABLE_PMF`` build option as well. Default is 0.
349 disabled when the target architecture is AArch32 or AArch64 8.0/8.1.
351 - ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
353 "strong" is the recommended stack protection level if this feature is
354 desired. 0 disables the stack protection. For all values other than 0, the
356 The value is passed as the last component of the option
359 - ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
361 Firmware as error. It can take the value 1 (flag the use of deprecated
364 - ``FIP_NAME``: This is an optional build option which specifies the FIP
365 filename for the ``fip`` target. Default is ``fip.bin``.
367 - ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
368 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
370 - ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
371 tool to create certificates as per the Chain of Trust described in
373 include the certificates in the FIP and FWU\_FIP. Default value is '0'.
376 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
377 the corresponding certificates, and to include those certificates in the
380 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
382 include the corresponding certificates. This FIP can be used to verify the
383 Chain of Trust on the host machine through other mechanisms.
385 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
386 images will include support for Trusted Board Boot, but the FIP and FWU\_FIP
387 will not include the corresponding certificates, causing a boot failure.
389 - ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
395 the Secure Payload interrupts needs to be synchronously handed over to Secure
396 EL1 for handling. The default value of this option is ``0``, which means the
409 initiate the operations, and the rest is managed in hardware, minimizing
418 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
421 - ``KEY_ALG``: This build flag enables the user to select the algorithm to be
422 used for generating the PKCS keys and subsequent signing of the certificate.
424 the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is
426 which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
428 - ``LDFLAGS``: Extra user options appended to the linkers' command line in
429 addition to the one set by the build system.
437 - ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
438 output compiled into the build. This should be one of the following:
449 All log output up to and including the log level is compiled into the build.
453 specifies the file that contains the Non-Trusted World private key in PEM
454 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
456 - ``NS_BL2U``: Path to NS\_BL2U image in the host file system. This image is
457 optional. It is only needed if the platform makefile specifies that it
458 is required in order to build the ``fwu_fip`` target.
462 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
463 wants the timer registers to be saved and restored.
465 - ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
466 the underlying hardware is not a full PL011 UART but a minimally compliant
467 generic UART, which is a subset of the PL011. The driver will not access
468 any register that is not part of the SBSA generic UART specification.
477 instead of the normal boot flow. When defined, it must specify the entry
478 point address for the preloaded BL33 image. This option is incompatible with
482 - ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
483 vector address can be programmed or is fixed on the platform. It can take
484 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
486 code directly at the right address, both on a cold and warm reset. In this
487 case, there is no need to identify the entrypoint on boot and the boot path
492 possible for the PSCI power-state parameter viz original and extended
493 State-ID formats. This flag if set to 1, configures the generic PSCI layer
494 to use the extended format. The default value of this flag is 0, which
495 means by default the original power-state format is used by the PSCI
496 implementation. This flag should be specified by the platform makefile
497 and it governs the return value of PSCI\_FEATURES API for CPU\_SUSPEND
498 smc function id. When this option is enabled on ARM platforms, the
501 - ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
502 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
506 - ``RESET_TO_SP_MIN``: SP\_MIN is the minimal AArch32 Secure Payload provided in
507 ARM Trusted Firmware. This flag configures SP\_MIN entrypoint as the CPU
508 reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU
512 - ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
513 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
514 file name will be used to save the key.
516 - ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
517 certificate generation tool to save the keys used to establish the Chain of
520 - ``SCP_BL2``: Path to SCP\_BL2 image in the host file system. This image is optional.
521 If a SCP\_BL2 image is present then this option must be passed for the ``fip``
524 - ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
525 file that contains the SCP\_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
526 this file name will be used to save the key.
528 - ``SCP_BL2U``: Path to SCP\_BL2U image in the host file system. This image is
529 optional. It is only needed if the platform makefile specifies that it
530 is required in order to build the ``fwu_fip`` target.
538 - ``SPD``: Choose a Secure Payload Dispatcher component to be built into the
540 value should be the path to the directory containing the SPD source,
541 relative to ``services/spd/``; the directory is expected to
545 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
547 firmware images have been loaded in memory, and the MMU and caches are
548 turned off. Refer to the "Debugging options" section for more details.
550 - ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
551 secure interrupts (caught through the FIQ line). Platforms can enable
553 the FIQ are handled in monitor mode and non secure world is not allowed
555 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
557 - ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
559 and verify the certificates and images in a FIP, and BL1 includes support
560 for the Firmware Update. The default value is '0'. Generation and inclusion
561 of certificates in the FIP and FWU\_FIP depends upon the value of the
564 Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys
568 specifies the file that contains the Trusted World private key in PEM
569 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
573 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
577 - ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
580 for saving and restoring the TSP context in this routing model. The
581 default routing model (when the value is 0) is to route non-secure
585 - ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
586 memory region in the BL memory map or not (see "Use of Coherent memory in
587 Trusted Firmware" section in `Firmware Design`_). It can take the value 1
591 - ``V``: Verbose build. If assigned anything other than 0, the build commands
594 - ``VERSION_STRING``: String used in the log output for each TF image. Defaults
595 to a string formed by concatenating the version number, build type and build
599 the CPU after warm boot. This is applicable for platforms which do not
608 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
610 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
614 of the memory reserved for each image. This affects the maximum size of each
615 BL image as well as the number of allocated memory regions and translation
616 tables. By default this flag is 0, which means it uses the default
618 optimise memory usage need to set this flag to 1 and must override the
621 - ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
622 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
624 match the frame used by the Non-Secure image (normally the Linux kernel).
625 Default is true (access to the frame is allowed).
627 - ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
629 an error is encountered during the boot process (for example, when an image
630 could not be loaded or authenticated). The watchdog is enabled in the early
631 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
636 for the construction of composite state-ID in the power-state parameter.
638 State-ID yet. Hence this flag is used to configure whether to use the
640 in which case the platform is configured to expect NULL in the State-ID
643 - ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
644 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
645 for ARM platforms. Depending on the selected option, the proper private key
646 must be specified using the ``ROT_KEY`` option when building the Trusted
647 Firmware. This private key will be used by the certificate generation tool
648 to sign the BL2 and Trusted Key certificates. Available options for
651 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
654 - ``devel_rsa`` : return a development public key hash embedded in the BL1
655 and BL2 binaries. This hash has been obtained from the RSA public key
658 creating the certificates.
659 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
660 and BL2 binaries. This hash has been obtained from the ECDSA public key
663 when creating the certificates.
665 - ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
670 configured by the TrustZone controller)
672 - ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile the Trusted Firmware
673 with version 1 of the translation tables library instead of version 2. It is
678 ARM platforms. If this option is specified, then the path to the CryptoCell
681 For a better understanding of these options, the ARM development platform memory
682 map is explained in the `Firmware Design`_.
688 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
689 compatible change to the MTL protocol, used for AP/SCP communication.
695 SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded
699 instead of SCPI/BOM driver for communicating with the SCP during power
706 - ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
707 build the topology tree within Trusted Firmware. By default the
709 can be used to override the default value.
711 - ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
712 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
713 explained in the options below:
715 - ``FVP_CCI`` : The CCI driver is selected. This is the default
717 - ``FVP_CCN`` : The CCN driver is selected. This is the default
720 - ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
721 in the system. This option defaults to 1. Note that the build option
724 - ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
731 GICv3 hardware, then it configures the hardware to run in GICv2
734 - ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
741 To compile a debug version and make the build more verbose use
749 symbols to be emitted by GCC. This can be achieved by using the
750 ``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
757 might need to be recalculated (see the **Memory layout on ARM development
758 platforms** section in the `Firmware Design`_).
760 Extra debug options can be passed to the build system by setting ``CFLAGS`` or
769 ignored as the linker is called directly.
771 It is also possible to introduce an infinite loop to help in debugging the
772 post-BL2 phase of the Trusted Firmware. This can be done by rebuilding BL1 with
773 the ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
774 section. In this case, the developer may take control of the target using a
775 debugger when indicated by the console output. When using DS-5, the following
787 # Jump over the debug loop
793 Building the Test Secure Payload
796 The TSP is coupled with a companion runtime service in the BL31 firmware,
797 called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
798 must be recompiled as well. For more information on SPs and SPDs, see the
799 `Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
801 First clean the Trusted Firmware build directory to get rid of any previous
802 BL31 binary. Then to build the TSP image use:
808 An additional boot loader binary file is created in the ``build`` directory:
817 When making changes to the source for submission to the project, the source
818 must be in compliance with the Linux style guide, and to assist with this check
819 the project Makefile contains two targets, which both utilise the
820 ``checkpatch.pl`` script that ships with the Linux source tree.
822 To check the entire source tree, you must first download a copy of
823 ``checkpatch.pl`` (or the full Linux source), set the ``CHECKPATCH`` environment
824 variable to point to the script and build the target checkcodebase:
830 To just check the style on the files that differ between your local branch and
831 the remote master, use:
837 If you wish to check your patch against something other than the remote master,
838 set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
841 Building and using the FIP tool
844 Firmware Image Package (FIP) is a packaging format used by the Trusted Firmware
847 images and other firmware images required by the platform. For example, most
848 platforms require a BL33 image which corresponds to the normal world bootloader
851 The TF build system provides the make target ``fip`` to create a FIP file for the
852 specified platform using the FIP creation tool included in the TF project.
880 the tool and create or modify FIPs using this tool. To do this, follow these
883 It is recommended to remove old artifacts before building the tool:
889 Build the tool:
901 Invoking the tool with ``--help`` will print a help message with all available
913 Example 2: view the contents of an existing Firmware package:
919 Example 3: update the entries of an existing Firmware package:
923 # Change the BL2 from Debug to Release version
932 # Images will be unpacked to the working directory
942 Note that if the destination FIP file exists, the create, update and
945 The unpack operation will fail if the images already exist at the
948 More information about FIP can be found in the `Firmware Design`_ document.
954 that emulates the basic functionality of the previous fip\_create is provided.
959 - To dump the contents of a FIP file, replace "fip\_create --dump"
965 Trusted Board Boot primarily consists of the following two features:
973 #. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
974 modules by checking out a recent version of the `mbed TLS Repository`_. It
979 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
980 source files the modules depend upon.
981 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
982 options required to build the mbed TLS sources.
984 Note that the mbed TLS library is licensed under the Apache version 2.0
985 license. Using mbed TLS source code will affect the licensing of
988 #. To build the FIP image, ensure the following command line variables are set
991 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
995 In the case of ARM platforms, the location of the ROTPK hash must also be
999 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1000 root-key storage registers present in the platform. On Juno, this
1001 registers are read-only. On FVP Base and Cortex models, the registers
1002 are read-only, but the value can be specified using the command line
1003 option ``bp.trusted_key_storage.public_key`` when launching the model.
1004 On both Juno and FVP models, the default value corresponds to an
1008 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
1009 in the ARM platform port. The private/public RSA key pair may be
1012 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
1013 in the ARM platform port. The private/public ECDSA key pair may be
1020 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1027 The result of this build will be the bl1.bin and the fip.bin binaries. This
1028 FIP will include the certificates corresponding to the Chain of Trust
1029 described in the TBBR-client document. These certificates can also be found
1030 in the output build directory.
1033 Non-Volatile storage during the `Firmware Update`_ process. To build the
1034 FWU\_FIP, any FWU images required by the platform must be specified on the
1045 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1055 Note: The BL2U image will be built by default and added to the FWU\_FIP.
1057 to the command line above.
1059 Note: Building and installing the non-secure and SCP FWU images (NS\_BL1U,
1060 NS\_BL2U and SCP\_BL2U) is outside the scope of this document.
1063 Both the FIP and FWU\_FIP will include the certificates corresponding to the
1064 Chain of Trust described in the TBBR-client document. These certificates
1065 can also be found in the output build directory.
1067 Building the Certificate Generation Tool
1070 The ``cert_create`` tool is built as part of the TF build process when the ``fip``
1071 make target is specified and TBB is enabled (as described in the previous
1072 section), but it can also be built separately with the following command:
1079 the generic 'cert\_create' tool can be built with the following command:
1085 ``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1086 verbose. The following command should be used to obtain help about the tool:
1096 Firmware, obtain the additional required firmware, and pack it all together in
1102 Note: follow the full instructions for one platform before switching to a
1106 #. Clean the working directory
1114 Use the fiptool to extract the SCP\_BL2 and BL33 images from the FIP
1115 package included in the Linaro release:
1119 # Build the fiptool
1126 The unpack operation will result in a set of binary images extracted to the
1130 Note: the fiptool will complain if the images to be unpacked already
1131 exist in the current directory. If that is the case, either delete those
1132 files or use the ``--force`` option to overwrite.
1134 Note for AArch32, the instructions below assume that nt-fw.bin is a custom
1151 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1166 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1167 to the AArch32 Linaro cross compiler.
1180 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1181 must point to the AArch64 Linaro cross compiler.
1188 and point to the BL32 file.
1214 that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1221 an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1222 on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1223 Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1225 overlap with any other entries in the file.
1240 The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1241 In the same way, the address ns_bl2u_base_address is the value of
1254 The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1255 In the same way, the address ns_bl2u_base_address is the value of
1262 On a pre-production system, the ability to execute arbitrary, bare-metal code at
1263 the highest exception level is required. It allows full, direct access to the
1267 scratch, this is a complex task on some platforms, depending on the level of
1268 configuration required to put the system in the expected state.
1271 ``EL3 payloads`` through the Trusted Firmware instead. This is implemented as an
1273 loading the other BL images and passing control to BL31. It reduces the
1276 - putting the system into a known architectural state;
1278 - loading the SCP\_BL2 image if required by the platform.
1280 When booting an EL3 payload on ARM standard platforms, the configuration of the
1282 configured to permit secure access only. This gives full access to the whole
1283 DRAM to the EL3 payload.
1285 The system is left in the same state as when entering BL31 in the default boot
1298 The EL3 payload image is a standalone image and is not part of the FIP. It is
1299 not loaded by the Trusted Firmware. Therefore, there are 2 possible scenarios:
1302 place. In this case, booting it is just a matter of specifying the right
1303 address in NVM through ``EL3_PAYLOAD_BASE`` when building the TF.
1308 To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1309 used. The infinite loop that it introduces in BL1 stops execution at the right
1310 moment for a debugger to take control of the target and load the payload (for
1315 use any other platform-specific mechanism to load the EL3 payload, though.
1320 The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1321 the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1322 is undefined on the FVP platform and the FVP platform code doesn't clear it.
1323 Therefore, one must modify the way the model is normally invoked in order to
1324 clear the mailbox at start-up.
1327 the following command:
1333 and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1334 using the following model parameters:
1341 To provide the model with the EL3 payload image, the following methods may be
1344 #. If the EL3 payload is able to execute in place, it may be programmed into
1345 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1346 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1347 used for the FIP):
1353 On Foundation FVP, there is no flash loader component and the EL3 payload
1356 #. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1357 command may be used to load the EL3 payload ELF image over JTAG:
1363 #. The EL3 payload may be pre-loaded in volatile memory using the following
1371 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
1372 used when building the Trusted Firmware.
1377 If the EL3 payload is able to execute in place, it may be programmed in flash
1378 memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1379 on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1380 Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1383 Alternatively, the same DS-5 command mentioned in the FVP section above can
1384 be used to load the EL3 payload's ELF file over JTAG on Juno.
1389 Some platforms have the ability to preload BL33 into memory instead of relying
1390 on Trusted Firmware to load it. This may simplify packaging of the normal world
1395 For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
1396 used when compiling the Trusted Firmware. For example, the following command
1407 The following example uses the AArch64 boot wrapper. This simplifies normal
1415 After compiling it, an ELF file is generated. It can be loaded with the
1426 The ``-a cluster0.cpu0=<bootwrapped-kernel.elf>`` option loads the ELF file. It
1427 also sets the PC register to the ELF entry point address, which is not the
1428 desired behaviour, so the ``--start cluster0.cpu0=0x0`` option forces the PC back
1429 to 0x0 (the BL1 entry point address) on CPU #0. The ``PRELOADED_BL33_BASE`` define
1430 used when compiling the FIP must match the ELF entry point.
1435 The procedure to obtain and compile the boot wrapper is very similar to the case
1436 of the FVP. The execution must be stopped at the end of bl2\_main(), and the
1437 loading method explained above in the EL3 payload boot flow section may be used
1438 to load the ELF file over JTAG on Juno.
1440 Running the software on FVP
1443 The latest version of the AArch64 build of ARM Trusted Firmware has been tested
1444 on the following ARM FVPs (64-bit host machine only).
1446 NOTE: Unless otherwise stated, the model version is Version 11.1 Build 11.1.22.
1459 The latest version of the AArch32 build of ARM Trusted Firmware has been tested
1460 on the following ARM FVPs (64-bit host machine only).
1465 NOTE: The build numbers quoted above are those reported by launching the FVP
1466 with the ``--version`` parameter.
1474 NOTE: The software will not work on Version 1.0 of the Foundation FVP.
1482 the internal synchronisation timings changed compared to older versions of the
1484 to match the run time characteristics of the older versions.
1486 The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
1492 Please refer to the FVP documentation for a detailed description of the model
1493 parameter options. A brief description of the important ones that affect the ARM
1496 Obtaining the Flattened Device Trees
1499 Depending on the FVP configuration and Linux configuration used, different
1500 FDT files are required. FDTs for the Foundation and Base FVPs can be found in
1501 the Trusted Firmware source directory under ``fdts/``. The Foundation FVP has a
1502 subset of the Base FVP components. For example, the Foundation FVP lacks CLCD
1505 Note: It is not recommended to use the FDTs built along the kernel because not
1537 Running on the Foundation FVP with reset to BL1 entrypoint
1541 4 CPUs using the AArch64 build of ARM Trusted Firmware.
1558 - BL1 is loaded at the start of the Trusted ROM.
1559 - The Firmware Image Package is loaded at the start of NOR FLASH0.
1561 - The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1562 and enable the GICv3 device in the model. Note that without this option,
1563 the Foundation FVP defaults to legacy (Versatile Express) memory map which
1566 Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1570 with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1587 Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1591 with 8 CPUs using the AArch32 build of ARM Trusted Firmware.
1616 Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1620 boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1635 Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1639 boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware.
1654 Running on the AEMv8 Base FVP with reset to BL31 entrypoint
1658 with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1686 - Since a FIP is not loaded when using BL31 as reset entrypoint, the
1688 parameter is needed to load the individual bootloader images in memory.
1693 X and Y are the cluster and CPU numbers respectively, is used to set the
1696 - Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
1697 changing the value of
1698 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
1701 Running on the AEMv8 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1705 with 8 CPUs using the AArch32 build of ARM Trusted Firmware.
1738 Note: The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
1739 It should match the address programmed into the RVBAR register as well.
1741 Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
1745 boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1769 Running on the Cortex-A32 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1773 boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware.
1792 Running the software on Juno
1795 This version of the ARM Trusted Firmware has been tested on variants r0, r1 and
1798 To execute the software stack on Juno, the version of the Juno board recovery
1799 image indicated in the `Linaro Release Notes`_ must be installed. If you have an
1801 re-install the recovery image by following the
1807 After building Trusted Firmware, the files ``bl1.bin`` and ``fip.bin`` need copying
1808 to the ``SOFTWARE/`` directory of the Juno SD card.
1813 Please visit the `ARM Platforms Portal`_ to get support and obtain any other Juno
1814 software information. Please also refer to the `Juno Getting Started Guide`_ to
1815 get more detailed information about the Juno ARM development platform and how to
1823 on Juno, at the linux shell prompt, issue the following command:
1841 …//community.arm.com/dev-platforms/b/documents/posts/instructions-for-using-the-linaro-software-del…