Lines Matching refs:MCInst_getOperand
7078 …ss_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
7087 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7088 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7097 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7098 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7100 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7102 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7103 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7109 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7110 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7112 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7119 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7121 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7123 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7125 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7126 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7134 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7135 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7137 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7139 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7140 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) {
7146 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7147 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7149 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7156 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7158 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7160 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7162 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7163 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) {
7171 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7172 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7181 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7182 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7184 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7186 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7187 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7193 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7194 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7196 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7203 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7205 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7207 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7209 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7210 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7218 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7219 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7221 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7230 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7231 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7233 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7235 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7236 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) {
7242 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7243 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7245 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7252 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7254 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7256 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7258 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7259 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) {
7267 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7269 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7271 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
7272 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
7273 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7274 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7280 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7282 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7284 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
7285 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
7286 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7287 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7295 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7297 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7299 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7301 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7302 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7310 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7312 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7314 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7316 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7317 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) {
7323 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7325 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7327 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7329 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7330 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) {
7338 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7340 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7342 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
7343 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
7344 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7345 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7351 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7353 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7355 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
7356 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
7357 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7358 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7366 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7368 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7370 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7372 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7373 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7381 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7383 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7385 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7387 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7388 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) {
7394 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7396 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7398 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7400 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7401 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) {
7409 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7410 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7419 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7420 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7422 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7424 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7425 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7431 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7432 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7434 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7441 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7443 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7445 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7447 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7448 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7456 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7457 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7466 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7467 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7469 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7471 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7472 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7478 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7479 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7481 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7488 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7490 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7492 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7494 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7495 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7503 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7505 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7507 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7509 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7510 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7518 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7520 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7522 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7524 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7525 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7533 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7535 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7537 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7539 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7540 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7548 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7550 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7552 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7554 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7555 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7563 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7565 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7567 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7569 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7570 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7578 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7580 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7582 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7584 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7585 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7593 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7595 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
7596 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
7604 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7606 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
7607 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
7615 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7617 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
7618 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
7626 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7628 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
7629 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
7637 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
7638 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) {
7646 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7648 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
7649 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_WZR &&
7650 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) {
7656 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7658 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7660 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7661 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
7662 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) {
7670 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7672 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
7673 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR &&
7674 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) {
7680 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7682 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7684 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7685 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
7686 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) {
7694 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7696 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
7697 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_WZR &&
7698 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) {
7704 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7706 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7708 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7709 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
7710 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) {
7718 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7720 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
7721 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR &&
7722 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) {
7728 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7730 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7732 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7733 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
7734 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) {
7742 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7744 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7746 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7747 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
7748 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) {
7756 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7758 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7760 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7761 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
7762 AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) {
7770 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
7771 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
7779 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
7780 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
7788 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
7789 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
7797 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7799 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7801 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7803 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7804 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7812 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7814 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7816 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7818 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7819 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7827 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7829 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7831 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7833 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7834 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7842 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7844 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7846 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7848 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7849 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7857 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7859 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7861 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7862 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
7870 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7872 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7874 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7875 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
7883 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
7884 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
7890 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
7891 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) {
7897 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
7898 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) {
7904 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
7905 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3) {
7911 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
7912 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4) {
7918 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
7919 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5) {
7927 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7929 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7938 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7940 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7949 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7951 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7960 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7962 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7971 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7973 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7982 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7984 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7993 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
7995 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
8004 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8006 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
8015 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
8016 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) {
8024 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8026 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8028 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8036 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8038 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8040 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8048 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8050 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8052 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8060 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8062 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8064 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8072 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8074 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8076 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8084 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8086 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8088 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8096 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8098 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8100 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8108 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8110 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8112 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8120 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8122 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8124 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8132 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8134 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8136 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8144 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8146 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8148 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8156 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8158 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8160 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8168 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8170 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8172 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8180 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8182 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8184 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8192 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8194 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8196 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8204 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8206 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8208 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8216 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8218 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8220 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8228 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8230 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8232 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8240 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8242 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8244 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8252 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8254 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8256 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8264 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8266 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8268 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8276 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8278 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8280 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8288 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8290 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8292 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8300 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8302 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8304 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8312 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8314 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8316 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8324 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8326 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8328 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8336 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8338 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8340 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8348 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8350 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8352 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8360 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8362 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8364 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8372 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8374 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8376 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8384 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8386 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8388 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8396 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8398 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8400 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8408 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8410 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8412 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8420 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8422 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8424 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8432 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8434 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8436 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8444 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8446 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8448 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8456 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8458 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8460 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8468 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8470 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8472 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8480 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8482 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8484 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8492 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8494 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8496 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8504 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8506 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8508 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8516 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8518 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8520 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8528 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8530 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8532 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8540 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8542 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8544 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8552 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8554 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8556 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8564 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8566 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8568 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8576 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8578 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8580 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8588 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8590 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8592 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8600 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8602 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8604 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8612 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8614 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8616 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8624 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8626 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8628 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8636 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8638 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8640 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8648 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8650 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8652 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8660 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8662 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8664 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8672 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8674 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8676 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8684 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8686 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8688 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8696 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8698 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8700 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8708 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8710 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8712 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8720 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8722 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8724 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8732 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8734 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8736 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8744 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8746 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8748 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8756 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8758 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8760 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8768 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8770 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8772 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8780 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8782 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8784 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8792 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8794 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8796 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8804 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8806 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8808 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8816 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8818 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8820 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8828 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8830 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8832 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8840 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8842 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8844 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8852 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8854 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8856 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8864 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8866 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8868 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8876 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8878 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8880 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8888 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8890 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8892 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8900 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8902 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8904 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8912 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8914 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8916 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8924 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8926 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8928 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8936 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8938 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8940 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8948 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8950 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8952 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8960 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8962 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8964 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8972 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8974 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8976 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8984 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8986 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8988 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8996 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8998 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9000 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
9008 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9010 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9012 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9020 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9022 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9024 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9032 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9034 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9036 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9044 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9046 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9048 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9056 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9058 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9060 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9068 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9070 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9072 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9080 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9082 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9084 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9092 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9094 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9096 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9104 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9106 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9108 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9116 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9118 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9120 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9128 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9130 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9132 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9140 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9142 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9144 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9152 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9154 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9156 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9164 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9166 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9168 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9176 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9178 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9180 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9188 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9190 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9192 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
9200 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9202 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9204 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
9212 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9214 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9216 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
9224 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9226 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9228 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
9236 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9238 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9240 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9242 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9243 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
9251 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9253 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9255 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9257 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9258 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
9266 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9268 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9270 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9272 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9273 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
9281 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9283 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9285 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9287 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9288 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
9296 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9298 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9300 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9302 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9303 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
9311 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9313 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9315 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9317 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9318 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
9326 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9328 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9330 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9332 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9333 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
9341 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9343 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9345 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9347 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9348 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
9356 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9358 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9360 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9362 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9363 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
9371 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9373 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9375 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9377 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9378 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
9386 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9388 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9390 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9392 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9393 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
9401 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9403 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9405 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9407 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9408 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
9409 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
9410 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
9418 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9420 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9422 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9423 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9431 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9433 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9435 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9437 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9438 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
9439 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
9440 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
9448 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9450 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9452 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9453 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9461 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9463 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9465 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9467 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9468 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
9469 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
9470 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
9478 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9480 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9482 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9483 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9491 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9493 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9495 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9497 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9498 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
9499 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
9500 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
9508 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9510 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9512 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9513 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9521 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9523 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9525 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9527 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9528 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
9529 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
9530 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
9538 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9540 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9542 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9543 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9551 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9553 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9555 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9557 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9558 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
9559 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
9560 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
9568 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9570 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9572 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9573 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9581 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9583 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9585 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9587 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9588 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
9589 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
9590 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
9598 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9600 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9602 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9603 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9611 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9613 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9615 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9617 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9618 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
9619 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
9620 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
9628 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9630 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9632 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9633 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9641 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9643 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9645 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9647 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9648 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
9649 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
9650 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
9658 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9660 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9662 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9663 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9671 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9673 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9675 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9677 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9678 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
9679 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
9680 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
9688 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9690 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9692 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9693 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9701 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9703 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9705 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9707 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9708 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
9709 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
9710 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
9718 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9720 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9722 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9723 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9731 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9733 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9735 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9737 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9738 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
9739 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
9740 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
9748 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9750 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9752 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9753 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9761 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9763 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9765 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9767 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9768 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
9769 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
9770 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
9778 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9780 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9782 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9783 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9791 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9793 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9795 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
9797 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
9798 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
9799 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
9800 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
9808 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9810 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9812 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9813 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9821 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9823 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9825 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9826 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9834 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9836 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9838 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9839 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9847 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9849 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9851 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9852 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9860 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9862 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9864 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9865 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9873 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9875 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9877 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9878 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9886 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9888 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9890 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9891 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9899 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9901 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9903 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9904 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9912 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9914 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9916 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9917 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9925 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9927 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9929 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9930 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9938 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9940 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9942 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9943 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9951 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9953 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9955 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9956 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9964 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9966 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9968 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9969 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9977 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9979 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9981 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9982 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
9990 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
9992 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
9994 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
9995 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
10003 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10005 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10007 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10008 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
10016 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10018 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10020 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10021 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
10029 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10031 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10033 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10034 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
10042 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10044 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10046 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10047 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
10055 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10057 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10059 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10060 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
10068 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10070 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10072 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10073 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
10081 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10083 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10085 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10086 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
10094 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10096 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10098 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10099 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
10107 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10109 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10111 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10112 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
10120 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10122 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10124 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10126 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) {
10134 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10136 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10138 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10140 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
10148 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10150 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10151 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16) {
10159 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10161 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10162 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 48) {
10168 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10170 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10171 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32) {
10177 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10179 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10180 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16) {
10188 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10190 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10192 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10194 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) {
10202 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10204 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10206 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10208 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
10216 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10218 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10227 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10229 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10238 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10240 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
10241 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10243 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
10244 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
10250 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10252 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
10253 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10260 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10262 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10264 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10266 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
10267 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
10275 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10277 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
10278 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10280 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
10281 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
10287 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10289 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
10290 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10297 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10299 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10301 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10303 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
10304 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
10312 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10314 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
10315 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10317 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
10318 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
10324 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10326 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10328 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10330 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
10331 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
10339 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10341 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
10342 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10344 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
10345 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
10351 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10353 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10355 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10357 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
10358 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
10366 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10368 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10370 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10371 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
10379 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10381 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10382 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
10390 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10392 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10393 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
10401 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10403 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10404 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
10412 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10414 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10415 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
10423 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10425 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10427 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10428 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
10436 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10438 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10440 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
10441 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
10442 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
10443 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
10451 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10453 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10454 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
10462 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10464 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10465 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
10473 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_LR) {
10481 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10483 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
10484 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10493 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10495 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
10496 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10505 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10507 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
10508 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10517 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10519 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
10520 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10529 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10531 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10533 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
10534 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) {
10540 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10542 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10544 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10545 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
10546 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
10547 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
10553 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10555 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10557 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10558 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
10559 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
10560 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
10568 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10570 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10572 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
10573 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 63) {
10579 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10581 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10583 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10584 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
10585 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
10586 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
10592 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10594 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10596 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10597 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
10598 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
10599 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
10605 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10607 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10609 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
10610 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
10611 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
10612 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) {
10620 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10622 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10624 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10626 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
10634 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10636 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10638 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
10640 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
10648 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10650 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10652 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10660 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10662 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10664 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10672 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10674 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10676 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10684 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10686 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10688 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10696 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10698 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10700 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10708 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10710 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10712 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10720 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10722 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10724 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10732 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10734 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10736 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10744 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10746 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10748 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10756 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10758 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10760 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10768 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10770 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10772 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10780 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10782 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10784 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10792 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10794 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10796 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10804 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10806 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10808 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10816 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10818 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10820 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10828 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10830 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10832 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10840 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10842 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10844 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10852 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10854 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10856 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10864 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10866 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10868 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10876 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10878 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10880 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10888 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10890 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10892 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10900 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10902 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10904 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10912 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10914 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10916 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10924 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10926 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10928 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10936 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10938 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10940 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10948 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10950 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10952 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10960 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10962 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10964 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10972 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10974 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10976 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10984 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10986 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
10988 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10996 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
10998 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11000 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11008 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11010 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11012 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11020 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11022 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11024 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11032 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11034 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11036 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11044 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11046 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11048 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11056 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11058 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11060 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11068 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11070 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11072 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11080 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11082 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11084 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11092 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11094 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11096 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11104 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11106 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11108 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11116 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11118 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11120 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11128 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11130 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11132 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11140 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11142 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11144 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11152 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11154 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11156 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11164 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11166 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11168 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11176 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11178 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11180 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11188 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11190 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11192 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11200 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11202 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11204 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11212 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11214 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11216 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11224 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11226 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11228 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11236 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11238 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11240 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11248 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11250 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11252 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11260 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11262 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11264 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11272 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11274 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11276 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11284 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11286 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11288 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11296 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11298 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11300 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11308 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11310 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11312 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11320 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11322 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11324 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11332 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11334 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11336 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11344 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11346 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11348 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11356 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11358 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11360 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11368 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11370 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11372 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11380 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11382 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11384 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11392 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11394 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11396 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11404 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11406 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11408 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11416 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11418 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11420 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11428 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11430 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11432 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11440 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11442 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11444 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11452 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11454 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11456 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11464 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11466 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11468 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11476 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11478 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11480 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11482 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11483 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
11491 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11493 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11495 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11497 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11498 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
11506 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11508 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11510 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11512 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11513 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
11521 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11523 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11525 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11527 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11528 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
11536 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11538 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11540 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11542 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11543 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
11551 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11553 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11555 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11557 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11558 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
11566 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11568 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11570 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11572 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11573 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
11581 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11583 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11585 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11587 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11588 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
11596 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11598 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11600 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11602 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11603 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
11611 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11613 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11615 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11617 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11618 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
11626 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11628 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11630 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11632 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11633 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
11634 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
11635 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
11643 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11645 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11647 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11648 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
11656 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11658 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11660 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11662 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11663 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
11664 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
11665 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
11673 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11675 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11677 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11678 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
11686 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11688 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11690 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11692 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11693 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
11694 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
11695 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
11703 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11705 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11707 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11708 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
11716 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11718 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11720 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11722 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11723 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
11724 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
11725 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
11733 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11735 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11737 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11738 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
11746 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11748 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11750 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11752 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11753 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
11754 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
11755 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
11763 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11765 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11767 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11768 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
11776 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11778 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11780 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11782 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11783 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
11784 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
11785 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
11793 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11795 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11797 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11798 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
11806 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11808 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11810 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11812 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11813 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
11814 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
11815 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
11823 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11825 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11827 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11828 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
11836 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11838 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11840 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11842 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11843 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
11844 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
11845 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
11853 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11855 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11857 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11858 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
11866 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11868 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11870 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
11872 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
11873 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
11874 MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
11875 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) {
11883 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11885 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11887 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11888 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
11896 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11898 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11900 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11901 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
11909 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11911 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11913 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11914 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
11922 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11924 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11926 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11927 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
11935 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11937 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11939 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11940 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
11948 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11950 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11952 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11953 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
11961 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11963 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11965 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11966 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
11974 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11976 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11978 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11979 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
11987 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
11989 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
11991 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
11992 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
12000 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12002 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12004 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
12005 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
12013 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12015 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12017 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
12018 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
12026 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12028 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12030 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
12031 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
12039 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12041 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12043 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
12044 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
12052 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12054 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12056 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
12057 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
12065 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
12066 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12075 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
12076 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12078 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12080 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12081 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
12087 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
12088 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12090 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12097 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12099 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
12100 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12102 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12103 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
12109 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12111 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
12112 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12119 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12121 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12123 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12125 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12126 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
12134 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
12135 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12137 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12139 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12140 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) {
12146 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
12147 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12149 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12156 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12158 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12160 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12162 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12163 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) {
12171 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
12172 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12181 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
12182 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12184 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12186 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12187 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
12193 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
12194 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12196 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12203 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12205 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
12206 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12208 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12209 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
12215 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12217 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
12218 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12225 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12227 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12229 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12231 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12232 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
12240 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
12241 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12243 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12252 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
12253 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12255 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12257 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12258 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) {
12264 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
12265 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12267 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12274 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12276 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12278 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12280 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12281 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) {
12289 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12291 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
12292 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12294 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12295 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
12301 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12303 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
12304 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12311 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12313 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12315 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12317 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12318 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
12326 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12328 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12330 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12332 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12333 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) {
12339 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12341 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12343 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12345 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12346 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) {
12354 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12356 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
12357 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12359 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12360 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
12366 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12368 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
12369 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12376 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12378 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12380 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12382 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12383 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
12391 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12393 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12395 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12397 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12398 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) {
12404 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12406 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12408 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12410 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12411 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) {
12419 MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR) {
12427 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12429 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12431 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12432 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) {
12438 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12440 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12442 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
12443 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
12444 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12445 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
12451 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12453 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12455 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
12456 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
12457 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12458 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
12466 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12468 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12470 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12471 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 63) {
12477 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12479 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12481 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
12482 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
12483 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12484 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
12490 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12492 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12494 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
12495 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
12496 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12497 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
12503 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12505 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12507 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
12508 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
12509 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
12510 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) {
12518 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12520 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12522 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12524 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
12532 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12534 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12543 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12545 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12554 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
12556 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
12558 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
12560 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {