Lines Matching refs:MCOperand_getReg
7078 …) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOpe…
7087 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7097 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7109 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7134 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7146 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7171 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7181 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7193 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7218 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7230 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7242 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7409 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7419 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7431 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7456 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7466 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7478 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
7648 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
7649 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_WZR &&
7661 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
7672 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
7673 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR &&
7685 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
7696 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
7697 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_WZR &&
7709 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
7720 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
7721 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR &&
7733 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
7747 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
7761 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
7862 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
7875 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
8028 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8040 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8052 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8064 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8076 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8088 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8100 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8112 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8124 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8136 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8148 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8160 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8172 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8184 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8196 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8208 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8220 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8232 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8244 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8256 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8268 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8280 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8292 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8304 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8316 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8328 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8340 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8352 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8364 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8376 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8388 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8400 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8412 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8424 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8436 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8448 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8460 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8472 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8484 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8496 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8508 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8520 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8532 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8544 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8556 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8568 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8580 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8592 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8604 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8616 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8628 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8640 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8652 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8664 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8676 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8688 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8700 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8712 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8724 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8736 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8748 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8760 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8772 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8784 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8796 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8808 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8820 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8832 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8844 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8856 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8868 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8880 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8892 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8904 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8916 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8928 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8940 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8952 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
8964 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8976 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
8988 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
9000 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
9012 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9024 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9036 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9048 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9060 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9072 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9084 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9096 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9108 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9120 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9132 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9144 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9156 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9168 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9180 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
9192 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
9204 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
9216 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
9228 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
10126 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) {
10140 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
10194 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) {
10208 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
10240 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
10252 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
10277 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
10289 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
10314 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
10341 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
10371 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
10428 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
10473 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_LR) {
10483 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
10495 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
10507 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
10519 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
10626 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
10640 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
10652 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10664 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10676 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10688 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10700 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10712 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10724 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10736 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10748 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10760 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10772 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10784 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10796 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10808 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10820 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10832 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10844 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10856 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10868 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10880 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10892 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10904 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10916 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10928 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10940 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10952 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10964 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10976 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
10988 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11000 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11012 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11024 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11036 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11048 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11060 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11072 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11084 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11096 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11108 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11120 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11132 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11144 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11156 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11168 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11180 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11192 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11204 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11216 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11228 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11240 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11252 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11264 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11276 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11288 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11300 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11312 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11324 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11336 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11348 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11360 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11372 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11384 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11396 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11408 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11420 MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) {
11432 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11444 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11456 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
11468 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
12065 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
12075 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
12087 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
12099 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
12111 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
12134 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
12146 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
12171 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
12181 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
12193 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
12205 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
12217 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
12240 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
12252 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
12264 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
12291 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
12303 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
12356 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
12368 MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
12419 MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR) {
12524 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
12560 MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {