Lines Matching refs:__u64
101 __u64 bo_size;
103 __u64 alignment;
105 __u64 domains;
107 __u64 domain_flags;
138 __u64 bo_info_ptr;
207 __u64 flags;
232 __u64 flags;
266 __u64 addr;
267 __u64 size;
299 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
301 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
314 __u64 flags;
316 __u64 tiling_info;
330 __u64 addr_ptr;
344 __u64 timeout;
364 __u64 handle;
366 __u64 timeout;
375 __u64 status;
388 __u64 seq_no;
393 __u64 fences;
396 __u64 timeout_ns;
419 __u64 value;
461 __u64 va_address;
463 __u64 offset_in_bo;
465 __u64 map_size;
489 __u64 chunk_data;
500 __u64 chunks;
504 __u64 handle;
528 __u64 va_start;
544 __u64 handle;
701 __u64 return_pointer;
765 __u64 vram_size;
766 __u64 vram_cpu_accessible_size;
767 __u64 gtt_size;
772 __u64 total_heap_size;
775 __u64 usable_heap_size;
783 __u64 heap_usage;
789 __u64 max_allocation;
826 __u64 max_engine_clock;
827 __u64 max_memory_clock;
838 __u64 ids_flags;
840 __u64 virtual_address_offset;
842 __u64 virtual_address_max;
859 __u64 prim_buf_gpu_addr;
861 __u64 pos_buf_gpu_addr;
863 __u64 cntl_sb_buf_gpu_addr;
865 __u64 param_buf_gpu_addr;
888 __u64 high_va_offset;
890 __u64 high_va_max;
898 __u64 capabilities_flags;