Lines Matching refs:gb_tile_mode
1072 static void si_gb_tile_mode(uint32_t gb_tile_mode, in si_gb_tile_mode() argument
1081 switch (SI__GB_TILE_MODE__PIPE_CONFIG(gb_tile_mode)) { in si_gb_tile_mode()
1104 switch (SI__GB_TILE_MODE__NUM_BANKS(gb_tile_mode)) { in si_gb_tile_mode()
1121 switch (SI__GB_TILE_MODE__MACRO_TILE_ASPECT(gb_tile_mode)) { in si_gb_tile_mode()
1138 switch (SI__GB_TILE_MODE__BANK_WIDTH(gb_tile_mode)) { in si_gb_tile_mode()
1155 switch (SI__GB_TILE_MODE__BANK_HEIGHT(gb_tile_mode)) { in si_gb_tile_mode()
1172 switch (SI__GB_TILE_MODE__TILE_SPLIT(gb_tile_mode)) { in si_gb_tile_mode()
1290 uint32_t gb_tile_mode; in si_surface_sanity() local
1347 gb_tile_mode = surf_man->hw_info.tile_mode_array[*stencil_tile_mode]; in si_surface_sanity()
1348 si_gb_tile_mode(gb_tile_mode, NULL, NULL, NULL, NULL, NULL, &surf->stencil_tile_split); in si_surface_sanity()
1398 gb_tile_mode = surf_man->hw_info.tile_mode_array[*tile_mode]; in si_surface_sanity()
1399 …si_gb_tile_mode(gb_tile_mode, NULL, NULL, &surf->mtilea, &surf->bankw, &surf->bankh, &surf->tile_s… in si_surface_sanity()
1706 uint32_t gb_tile_mode; in si_surface_init_2d_miptrees() local
1710 gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode]; in si_surface_init_2d_miptrees()
1711 si_gb_tile_mode(gb_tile_mode, &num_pipes, &num_banks, NULL, NULL, NULL, NULL); in si_surface_init_2d_miptrees()
1867 uint32_t gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode]; in cik_get_2d_params() local
1874 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(gb_tile_mode)) { in cik_get_2d_params()
1900 switch (CIK__GB_TILE_MODE__TILE_SPLIT(gb_tile_mode)) { in cik_get_2d_params()
1924 switch (CIK__GB_TILE_MODE__SAMPLE_SPLIT(gb_tile_mode)) { in cik_get_2d_params()