Lines Matching refs:X1
67 COND_1: CMP X1, #0x400
73 COND_2: CMP X1, #0x200
79 COND_3: CMP X1, #0x100
85 COND_4: CMP X1, #0x80
91 COND_5: CMP X1, #0x40
136 LD2 {v0.S, v1.S}[0], [X5], X1
137 ADD X5, X5, X1
138 LD2 {v4.S, v5.S}[0], [X5], X1
139 SUB X5, X5, X1, LSL #1
140 LD2 {v2.S, v3.S}[0], [X5], X1
141 ADD X5, X5, X1
142 LD2 {v6.S, v7.S}[0], [X5], X1
143 SUB X5, X5, X1, LSL #2
147 LD2 {v0.S, v1.S}[1], [X6] , X1
148 ADD X6, X6, X1
149 LD2 {v4.S, v5.S}[1], [X6] , X1
150 SUB X6, X6, X1, LSL #1
151 LD2 {v2.S, v3.S}[1], [X6] , X1
152 ADD X6, X6, X1
153 LD2 {v6.S, v7.S}[1], [X6], X1
154 SUB X6, X6, X1, LSL #2
159 LD2 {v0.S, v1.S}[2], [X7] , X1
160 ADD X7, X7, X1
161 LD2 {v4.S, v5.S}[2], [X7] , X1
162 SUB X7, X7, X1, LSL #1
166 LD2 {v0.S, v1.S}[3], [X11] , X1
167 ADD X11, X11, X1
168 LD2 {v4.S, v5.S}[3], [X11] , X1
169 SUB X11, X11, X1, LSL #1
173 LD2 {v2.S, v3.S}[2], [X7] , X1
174 ADD X7, X7, X1
178 LD2 {v6.S, v7.S}[2], [X7], X1
179 SUB X7, X7, X1, LSL #2
183 LD2 {v2.S, v3.S}[3], [X11] , X1
184 ADD X11, X11, X1
187 LD2 {v6.S, v7.S}[3], [X11], X1
188 SUB X11, X11, X1, LSL #2
192 ADD X5, X5, X1, LSR #1
193 ADD X6, X6, X1, LSR #1
194 ADD X7, X7, X1, LSR #1
195 ADD X11, X11, X1, LSR #1
199 LD2 {v14.S, v15.S}[0], [X5] , X1
203 LD2 {v10.S, v11.S}[0], [X5] , X1
207 LD2 {v12.S, v13.S}[0], [X5] , X1
211 LD2 {v14.S, v15.S}[1], [X6] , X1
214 LD2 {v10.S, v11.S}[1], [X6] , X1
217 LD2 {v12.S, v13.S}[1], [X6] , X1
220 LD2 {v14.S, v15.S}[2], [X7] , X1
223 LD2 {v10.S, v11.S}[2], [X7] , X1
226 LD2 {v12.S, v13.S}[2], [X7] , X1
229 LD2 {v14.S, v15.S}[3], [X11] , X1
232 LD2 {v10.S, v11.S}[3], [X11] , X1
235 LD2 {v12.S, v13.S}[3], [X11] , X1
248 LD2 {v1.S, v2.S}[0], [X5], X1
252 LD2 {v1.S, v2.S}[1], [X6] , X1
256 LD2 {v1.S, v2.S}[2], [X7] , X1
260 LD2 {v1.S, v2.S}[3], [X11] , X1
454 LSR X1, X1, #1
455 LSL X15, X1, #3
460 LSR X15, X1, #5
493 LD2 {v0.S, v1.S}[0], [X5] , X1
494 ADD X5, X5, X1
495 LD2 {v8.S, v9.S}[0], [X5] , X1
496 SUB X5, X5, X1, LSL #1
497 LD2 {v4.S, v5.S}[0], [X5] , X1
498 ADD X5, X5, X1
499 LD2 {v12.S, v13.S}[0], [X5] , X1
503 LD2 {v0.S, v1.S}[1], [X6] , X1
504 ADD X6, X6, X1
505 LD2 {v8.S, v9.S}[1], [X6] , X1
506 SUB X6, X6, X1, LSL #1
507 LD2 {v4.S, v5.S}[1], [X6] , X1
508 ADD X6, X6, X1
509 LD2 {v12.S, v13.S}[1], [X6] , X1
514 LD2 {v0.S, v1.S}[2], [X7] , X1
515 ADD X7, X7, X1
516 LD2 {v8.S, v9.S}[2], [X7] , X1
523 LD2 {v0.S, v1.S}[3], [X11] , X1
524 ADD X11, X11, X1
525 LD2 {v8.S, v9.S}[3], [X11] , X1
527 SUB X7, X7, X1, LSL #1
529 LD2 {v4.S, v5.S}[2], [X7] , X1
530 ADD X7, X7, X1
532 LD2 {v12.S, v13.S}[2], [X7] , X1
534 SUB X11, X11, X1, LSL #1
536 LD2 {v4.S, v5.S}[3], [X11] , X1
537 ADD X11, X11, X1
539 LD2 {v12.S, v13.S}[3], [X11] , X1
602 LSR X1, X1, #1
603 SUB X3, X3, X1, LSL #3
606 LSR X6, X1, #4
800 SUB X14, X14, X1, LSL #3