100   assert(isReg() && "Wrong MachineOperand accessor");  in setIsDef()
120   if (!isReg() || !isOnRegUseList())  in removeRegFromUses()
135   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");  in ChangeToImmediate()
144   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");  in ChangeToFPImmediate()
153   assert((!isReg() || !isTied()) &&  in ChangeToES()
165   assert((!isReg() || !isTied()) &&  in ChangeToMCSymbol()
187   bool WasReg = isReg();  in ChangeToRegister()
732     if (MO.isReg())  in RemoveRegOperandsFromUseLists()
741     if (MO.isReg())  in AddRegOperandsToUseLists()
788   bool isImpReg = Op.isReg() && Op.isImplicit();  in addOperand()
790     while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {  in addOperand()
835   if (NewMO->isReg()) {  in addOperand()
870     if (Operands[i].isReg())  in RemoveOperand()
875   if (MRI && Operands[OpNo].isReg())  in RemoveOperand()
995     if (!MO.isReg()) {  in isIdenticalTo()
1058     if (!MO.isReg() || !MO.isDef())  in eraseFromParentAndMarkDBGValuesForRemoval()
1082     if (!MO.isReg() || !MO.isImplicit())  in getNumExplicitOperands()
1189   if (!getOperand(OpIdx).isReg())  in getRegClassConstraint()
1237   if (!MO.isReg() || MO.getReg() != Reg)  in getRegClassConstraintEffectForVRegImpl()
1248   assert(MO.isReg() &&  in getRegClassConstraintEffect()
1278     if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)  in hasRegisterImplicitUseOperand()
1291     if (!MO.isReg() || !MO.isUse())  in findRegisterUseOperandIdx()
1319     if (!MO.isReg() || MO.getReg() != Reg)  in readsWritesVirtualRegister()
1349     if (!MO.isReg() || !MO.isDef())  in findRegisterDefOperandIdx()
1440       if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)  in findTiedOperandIdx()
1483     if (MO.isReg() && MO.isUse())  in clearKillInfo()
1496       if (!MO.isReg() || MO.getReg() != FromReg)  in substituteRegister()
1502       if (!MO.isReg() || MO.getReg() != FromReg)  in substituteRegister()
1643     if (!MO.isReg() || MO.isUse())  in allDefsAreDead()
1658     if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())  in copyImplicitOps()
1700   for (; StartOp < e && getOperand(StartOp).isReg() &&  in print()
1768     if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))  in print()
1776         MO.isReg() && MO.isImplicit() && MO.isDef()) {  in print()
1950     if (!MO.isReg() || !MO.isUse() || MO.isUndef())  in addRegisterKilled()
2011     if (!MO.isReg() || !MO.isUse() || !MO.isKill())  in clearRegisterKills()
2029     if (!MO.isReg() || !MO.isDef())  in addRegisterDead()
2073     if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)  in clearRegisterDeads()
2081     if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)  in setRegisterDefReadUndef()
2095       if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&  in addRegisterDefined()
2113     if (!MO.isReg() || !MO.isDef()) continue;  in setPhysRegsDeadExcept()
2137     if (MO.isReg() && MO.isDef() &&  in getHashValue()