Lines Matching refs:getInstr
295 return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI(); in isBackedge()
302 return (!Source->getInstr()->isPHI() && in isOrder()
303 !Dep.getSUnit()->getInstr()->isPHI()); in isOrder()
313 if (Source->getInstr()->isPHI()) in getLatency()
315 if (Dep.getSUnit()->getInstr()->isPHI()) in getLatency()
327 if (V->getInstr()->isPHI() && Dep.getKind() == SDep::Anti) in getDistance()
515 os << " SU(" << I->NodeNum << ") " << *(I->getInstr()); in print()
999 MachineInstr &MI = *SU.getInstr(); in addLoopCarriedDependences()
1020 MachineInstr &LdMI = *Load->getInstr(); in addLoopCarriedDependences()
1085 MachineInstr *MI = I.getInstr(); in updatePhiDependences()
1140 MachineInstr *PMI = PI.getSUnit()->getInstr(); in updatePhiDependences()
1142 if (I.getInstr()->isPHI()) { in updatePhiDependences()
1165 if (!canUseLastOffsetValue(I.getInstr(), BasePos, OffsetPos, NewBase, in changeDependences()
1170 unsigned OrigBase = I.getInstr()->getOperand(BasePos).getReg(); in changeDependences()
1409 (SI.getKind() == SDep::Anti && !SI.getSUnit()->getInstr()->isPHI())) in createAdjacencyStructure()
1420 if (!SUnits[i].getInstr()->mayStore() || in createAdjacencyStructure()
1423 if (PI.getKind() == SDep::Order && PI.getSUnit()->getInstr()->mayLoad()) { in createAdjacencyStructure()
1699 const MachineInstr *MI = SU->getInstr(); in computeLiveOuts()
1713 for (ConstMIOperands MO(*SU->getInstr()); MO.isValid(); ++MO) in computeLiveOuts()
1751 MachineBasicBlock::const_iterator CurInstI = SU->getInstr(); in registerPressureFilter()
1756 RecRPTracker.getMaxUpwardPressureDelta(SU->getInstr(), nullptr, RPDelta, in registerPressureFilter()
2142 SU->getInstr()->dump(); in schedulePipeline()
2165 if (SU->getInstr()->isPHI()) in schedulePipeline()
2233 if (CI->getInstr()->isPHI()) in generatePipelinedLoop()
2235 unsigned StageNum = Schedule.stageScheduled(getSUnit(CI->getInstr())); in generatePipelinedLoop()
2236 MachineInstr *NewMI = cloneInstr(CI->getInstr(), MaxStageCount, StageNum); in generatePipelinedLoop()
2239 InstrMap[NewMI] = CI->getInstr(); in generatePipelinedLoop()
3280 (CyclePhi <= CycleSched || OrigMISU->getInstr()->isPHI())) in rewriteScheduledInstr()
3409 MachineInstr *SI = Source->getInstr(); in isLoopCarriedOrder()
3410 MachineInstr *DI = Dep.getSUnit()->getInstr(); in isLoopCarriedOrder()
3475 if (ST.getInstrInfo()->isZeroCost((*I)->getInstr()->getOpcode())) in insert()
3477 assert(Resources->canReserveResources(*(*I)->getInstr()) && in insert()
3479 Resources->reserveResources(*(*I)->getInstr()); in insert()
3482 if (ST.getInstrInfo()->isZeroCost(SU->getInstr()->getOpcode()) || in insert()
3483 Resources->canReserveResources(*SU->getInstr())) { in insert()
3486 SU->getInstr()->dump(); in insert()
3499 SU->getInstr()->dump(); in insert()
3556 if (DAG->isBackedge(SU, P) && P.getSUnit()->getInstr()->isPHI()) in multipleIterations()
3558 if (S.getKind() == SDep::Order && S.getSUnit()->getInstr()->isPHI()) in multipleIterations()
3597 if (BE && Dep.getSUnit() == BE && !SU->getInstr()->isPHI() && in computeStart()
3627 MachineInstr *MI = SU->getInstr(); in orderDependence()
3639 if (MI->isPHI() && (*I)->getInstr()->isPHI()) in orderDependence()
3653 (*I)->getInstr()->readsWritesVirtualRegister(Reg); in orderDependence()
3681 isLoopCarriedDefOfUse(SSD, (*I)->getInstr(), MO)) { in orderDependence()
3780 if (UseSU->getInstr()->isPHI()) in isLoopCarried()
3858 MachineInstr *MI = I.first->getInstr(); in finalizeSchedule()
3898 SSD->applyInstrChange(SU->getInstr(), *this, true); in finalizeSchedule()
3909 if (ST.getInstrInfo()->isZeroCost(SU->getInstr()->getOpcode())) in finalizeSchedule()
3916 if (!ST.getInstrInfo()->isZeroCost(SU->getInstr()->getOpcode())) in finalizeSchedule()
3936 CI->getInstr()->print(os); in print()