71       unsigned VirtReg;         // Virtual register number.  member
77         : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){}  in LiveReg()
80         return TargetRegisterInfo::virtReg2Index(VirtReg);  in getSparseSetIndex()
171     int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
176     void killVirtReg(unsigned VirtReg);
178     void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
184     LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {  in findLiveVirtReg()  argument
185       return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));  in findLiveVirtReg()
187     LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const {  in findLiveVirtReg()
188       return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));  in findLiveVirtReg()
194                                        unsigned VirtReg, unsigned Hint);
196                                        unsigned VirtReg, unsigned Hint);
205 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {  in getStackSpaceFor()  argument
207   int SS = StackSlotForVirtReg[VirtReg];  in getStackSpaceFor()
216   StackSlotForVirtReg[VirtReg] = FrameIdx;  in getStackSpaceFor()
251   assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg &&  in killVirtReg()
260 void RAFast::killVirtReg(unsigned VirtReg) {  in killVirtReg()  argument
261   assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&  in killVirtReg()
263   LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);  in killVirtReg()
270 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {  in spillVirtReg()  argument
271   assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&  in spillVirtReg()
273   LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);  in spillVirtReg()
282   assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping");  in spillVirtReg()
289     DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)  in spillVirtReg()
291     const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);  in spillVirtReg()
292     int FI = getStackSpaceFor(LRI->VirtReg, RC);  in spillVirtReg()
301       LiveDbgValueMap[LRI->VirtReg];  in spillVirtReg()
419   switch (unsigned VirtReg = PhysRegState[PhysReg]) {  in definePhysReg()  local
423     spillVirtReg(MI, VirtReg);  in definePhysReg()
435     switch (unsigned VirtReg = PhysRegState[Alias]) {  in definePhysReg()  local
439       spillVirtReg(MI, VirtReg);  in definePhysReg()
462   switch (unsigned VirtReg = PhysRegState[PhysReg]) {  in calcSpillCost()  local
468     DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding "  in calcSpillCost()
472     LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);  in calcSpillCost()
483     switch (unsigned VirtReg = PhysRegState[Alias]) {  in calcSpillCost()  local
492       LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);  in calcSpillCost()
508   DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to "  in assignVirtToPhysReg()
510   PhysRegState[PhysReg] = LR.VirtReg;  in assignVirtToPhysReg()
516 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {  in assignVirtToPhysReg()  argument
517   LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);  in assignVirtToPhysReg()
527   const unsigned VirtReg = LRI->VirtReg;  in allocVirtReg()  local
529   assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&  in allocVirtReg()
532   const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);  in allocVirtReg()
548       return assignVirtToPhysReg(VirtReg, Hint);  in allocVirtReg()
563   DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "  in allocVirtReg()
585     return assignVirtToPhysReg(VirtReg, BestReg);  in allocVirtReg()
594   return assignVirtToPhysReg(VirtReg, *AO.begin());  in allocVirtReg()
600                                                    unsigned VirtReg,  in defineVirtReg()  argument
602   assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&  in defineVirtReg()
606   std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));  in defineVirtReg()
610         MRI->hasOneNonDBGUse(VirtReg)) {  in defineVirtReg()
611       const MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(VirtReg);  in defineVirtReg()
634                                                    unsigned VirtReg,  in reloadVirtReg()  argument
636   assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&  in reloadVirtReg()
640   std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));  in reloadVirtReg()
644     const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);  in reloadVirtReg()
645     int FrameIndex = getStackSpaceFor(VirtReg, RC);  in reloadVirtReg()
646     DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into "  in reloadVirtReg()
850            assert(TargetRegisterInfo::isVirtualRegister(i->VirtReg) &&  in AllocateBasicBlock()
854            assert(PhysRegState[i->PhysReg] == i->VirtReg && "Bad inverse map");  in AllocateBasicBlock()