Lines Matching refs:VirtReg
212 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage()
213 return ExtraRegInfo[VirtReg.reg].Stage; in getStage()
216 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
218 ExtraRegInfo[VirtReg.reg].Stage = Stage; in setStage()
357 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
362 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
373 unsigned calculateRegionSplitCost(LiveInterval &VirtReg,
378 unsigned doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
383 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order,
494 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg() argument
495 if (VRM->hasPhys(VirtReg)) { in LRE_CanEraseVirtReg()
496 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_CanEraseVirtReg()
506 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg() argument
507 if (!VRM->hasPhys(VirtReg)) in LRE_WillShrinkVirtReg()
511 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_WillShrinkVirtReg()
618 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, in tryAssign() argument
624 if (!Matrix->checkInterference(VirtReg, PhysReg)) in tryAssign()
633 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg)) in tryAssign()
638 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) { in tryAssign()
639 evictInterference(VirtReg, Hint, NewVRegs); in tryAssign()
653 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost); in tryAssign()
662 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { in canReassign() argument
663 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); in canReassign()
672 LiveIntervalUnion::Query subQ(&VirtReg, &Matrix->getLiveUnions()[*Units]); in canReassign()
681 DEBUG(dbgs() << "can reassign: " << VirtReg << " from " in canReassign()
725 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference() argument
728 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg) in canEvictInterference()
731 bool IsLocal = LIS->intervalIsInOneMBB(VirtReg); in canEvictInterference()
740 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade; in canEvictInterference()
746 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in canEvictInterference()
765 bool Urgent = !VirtReg.isSpillable() && in canEvictInterference()
767 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) < in canEvictInterference()
789 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint)) in canEvictInterference()
807 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference() argument
812 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade; in evictInterference()
814 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++; in evictInterference()
822 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in evictInterference()
836 VirtReg.isSpillable() < Intf->isSpillable()) && in evictInterference()
858 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, in tryEvict() argument
874 BestCost.MaxWeight = VirtReg.weight; in tryEvict()
877 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg); in tryEvict()
906 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost)) in tryEvict()
920 evictInterference(VirtReg, BestPhys, NewVRegs); in tryEvict()
1353 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryRegionSplit() argument
1373 calculateRegionSplitCost(VirtReg, Order, BestCost, NumCands, in tryRegionSplit()
1380 return doRegionSplit(VirtReg, BestCand, HasCompact, NewVRegs); in tryRegionSplit()
1383 unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg, in calculateRegionSplitCost() argument
1465 unsigned RAGreedy::doRegionSplit(LiveInterval &VirtReg, unsigned BestCand, in doRegionSplit() argument
1470 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in doRegionSplit()
1513 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryBlockSplit() argument
1515 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed"); in tryBlockSplit()
1516 unsigned Reg = VirtReg.reg; in tryBlockSplit()
1518 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in tryBlockSplit()
1581 RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryInstructionSplit() argument
1583 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg); in tryInstructionSplit()
1590 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in tryInstructionSplit()
1610 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII, in tryInstructionSplit()
1628 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS); in tryInstructionSplit()
1725 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryLocalSplit() argument
1752 if (Matrix->checkRegMaskInterference(VirtReg)) { in tryLocalSplit()
1797 bool ProgressRequired = getStage(VirtReg) >= RS_Split2; in tryLocalSplit()
1816 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg)) in tryLocalSplit()
1913 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in tryLocalSplit()
1922 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS); in tryLocalSplit()
1952 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order, in trySplit() argument
1955 if (getStage(VirtReg) >= RS_Spill) in trySplit()
1959 if (LIS->intervalIsInOneMBB(VirtReg)) { in trySplit()
1961 SA->analyze(&VirtReg); in trySplit()
1962 unsigned PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs); in trySplit()
1965 return tryInstructionSplit(VirtReg, Order, NewVRegs); in trySplit()
1970 SA->analyze(&VirtReg); in trySplit()
1979 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) in trySplit()
1986 if (getStage(VirtReg) < RS_Split2) { in trySplit()
1987 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs); in trySplit()
1993 return tryBlockSplit(VirtReg, Order, NewVRegs); in trySplit()
2009 RAGreedy::mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg, in mayRecolorAllInterferences() argument
2012 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg); in mayRecolorAllInterferences()
2015 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in mayRecolorAllInterferences()
2079 unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg, in tryLastChanceRecoloring() argument
2084 DEBUG(dbgs() << "Try last chance recoloring for " << VirtReg << '\n'); in tryLastChanceRecoloring()
2086 assert((getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) && in tryLastChanceRecoloring()
2105 FixedRegisters.insert(VirtReg.reg); in tryLastChanceRecoloring()
2109 DEBUG(dbgs() << "Try to assign: " << VirtReg << " to " in tryLastChanceRecoloring()
2115 if (Matrix->checkInterference(VirtReg, PhysReg) > in tryLastChanceRecoloring()
2124 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates, in tryLastChanceRecoloring()
2151 Matrix->assign(VirtReg, PhysReg); in tryLastChanceRecoloring()
2161 Matrix->unassign(VirtReg); in tryLastChanceRecoloring()
2165 DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to " in tryLastChanceRecoloring()
2170 Matrix->unassign(VirtReg); in tryLastChanceRecoloring()
2218 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit() argument
2223 unsigned Reg = selectOrSplitImpl(VirtReg, NewVRegs, FixedRegisters); in selectOrSplit()
2248 unsigned RAGreedy::tryAssignCSRFirstTime(LiveInterval &VirtReg, in tryAssignCSRFirstTime() argument
2253 if (getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) { in tryAssignCSRFirstTime()
2256 SA->analyze(&VirtReg); in tryAssignCSRFirstTime()
2265 if (getStage(VirtReg) < RS_Split) { in tryAssignCSRFirstTime()
2268 SA->analyze(&VirtReg); in tryAssignCSRFirstTime()
2271 unsigned BestCand = calculateRegionSplitCost(VirtReg, Order, BestCost, in tryAssignCSRFirstTime()
2278 doRegionSplit(VirtReg, BestCand, false/*HasCompact*/, NewVRegs); in tryAssignCSRFirstTime()
2359 void RAGreedy::tryHintRecoloring(LiveInterval &VirtReg) { in tryHintRecoloring() argument
2366 unsigned Reg = VirtReg.reg; in tryHintRecoloring()
2478 unsigned RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg, in selectOrSplitImpl() argument
2484 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); in selectOrSplitImpl()
2485 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) { in selectOrSplitImpl()
2491 unsigned CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg, in selectOrSplitImpl()
2501 LiveRangeStage Stage = getStage(VirtReg); in selectOrSplitImpl()
2503 << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n'); in selectOrSplitImpl()
2510 tryEvict(VirtReg, Order, NewVRegs, CostPerUseLimit)) { in selectOrSplitImpl()
2511 unsigned Hint = MRI->getSimpleHint(VirtReg.reg); in selectOrSplitImpl()
2518 SetOfBrokenHints.insert(&VirtReg); in selectOrSplitImpl()
2528 setStage(VirtReg, RS_Split); in selectOrSplitImpl()
2530 NewVRegs.push_back(VirtReg.reg); in selectOrSplitImpl()
2536 if (Stage >= RS_Done || !VirtReg.isSpillable()) in selectOrSplitImpl()
2537 return tryLastChanceRecoloring(VirtReg, Order, NewVRegs, FixedRegisters, in selectOrSplitImpl()
2541 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs); in selectOrSplitImpl()
2546 if (EnableDeferredSpilling && getStage(VirtReg) < RS_Memory) { in selectOrSplitImpl()
2551 setStage(VirtReg, RS_Memory); in selectOrSplitImpl()
2553 NewVRegs.push_back(VirtReg.reg); in selectOrSplitImpl()
2556 LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in selectOrSplitImpl()