982                                    SDNode *DefNode, unsigned DefIdx,  in getOperandLatency()  argument
992     return ItinData->getOperandCycle(DefClass, DefIdx);  in getOperandLatency()
994   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
1056                                        unsigned DefIdx) const {  in hasLowDefLatency()
1062   int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in hasLowDefLatency()
1070                                        unsigned DefIdx,  in getOperandLatency()  argument
1075   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
1096     unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const {  in computeOperandLatency()  argument
1106     OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, *UseMI, UseIdx);  in computeOperandLatency()
1109     OperLatency = ItinData->getOperandCycle(DefClass, DefIdx);  in computeOperandLatency()
1124     const MachineInstr &MI, unsigned DefIdx,  in getRegSequenceInputs()  argument
1130     return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);  in getRegSequenceInputs()
1134   assert(DefIdx == 0 && "REG_SEQUENCE only has one def");  in getRegSequenceInputs()
1149     const MachineInstr &MI, unsigned DefIdx,  in getExtractSubregInputs()  argument
1155     return getExtractSubregLikeInputs(MI, DefIdx, InputReg);  in getExtractSubregInputs()
1159   assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");  in getExtractSubregInputs()
1172     const MachineInstr &MI, unsigned DefIdx,  in getInsertSubregInputs()  argument
1178     return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);  in getInsertSubregInputs()
1182   assert(DefIdx == 0 && "INSERT_SUBREG only has one def");  in getInsertSubregInputs()