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Lines Matching refs:ItinData

981 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()  argument
984 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
992 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
994 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
997 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
999 if (!ItinData || ItinData->isEmpty()) in getInstrLatency()
1005 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); in getInstrLatency()
1012 unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() argument
1014 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
1018 int UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps()
1043 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
1048 if (!ItinData) in getInstrLatency()
1051 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrLatency()
1057 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries(); in hasLowDefLatency() local
1058 if (!ItinData || ItinData->isEmpty()) in hasLowDefLatency()
1062 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1068 int TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
1075 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1081 const InstrItineraryData *ItinData, const MachineInstr &DefMI) const { in computeDefOperandLatency() argument
1084 if (!ItinData) in computeDefOperandLatency()
1085 return getInstrLatency(ItinData, DefMI); in computeDefOperandLatency()
1087 if(ItinData->isEmpty()) in computeDefOperandLatency()
1088 return defaultDefLatency(ItinData->SchedModel, DefMI); in computeDefOperandLatency()
1095 const InstrItineraryData *ItinData, const MachineInstr &DefMI, in computeOperandLatency() argument
1098 int DefLatency = computeDefOperandLatency(ItinData, DefMI); in computeOperandLatency()
1102 assert(ItinData && !ItinData->isEmpty() && "computeDefOperandLatency fail"); in computeOperandLatency()
1106 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, *UseMI, UseIdx); in computeOperandLatency()
1109 OperLatency = ItinData->getOperandCycle(DefClass, DefIdx); in computeOperandLatency()
1115 unsigned InstrLatency = getInstrLatency(ItinData, DefMI); in computeOperandLatency()
1119 defaultDefLatency(ItinData->SchedModel, DefMI)); in computeOperandLatency()