115   bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
119                           unsigned RegA, unsigned RegB, unsigned Dist);
534 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {  in regsAreCompatible()  argument
535   if (RegA == RegB)  in regsAreCompatible()
537   if (!RegA || !RegB)  in regsAreCompatible()
539   return TRI->regsOverlap(RegA, RegB);  in regsAreCompatible()
664     unsigned RegA = MI->getOperand(0).getReg();  in commuteInstruction()  local
665     SrcRegMap[RegA] = FromRegC;  in commuteInstruction()
674 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){  in isProfitableToConv3Addr()  argument
684   unsigned ToRegA = getMappedReg(RegA, DstRegMap);  in isProfitableToConv3Addr()
693                                               unsigned RegA, unsigned RegB,  in convertInstTo3Addr()  argument
725   SrcRegMap.erase(RegA);  in convertInstTo3Addr()
1463     unsigned RegA = DstMO.getReg();  in processTiedPairs()  local
1470     if (RegA == RegB) {  in processTiedPairs()
1477     LastCopiedReg = RegA;  in processTiedPairs()
1489              MI->getOperand(i).getReg() != RegA);  in processTiedPairs()
1494                                       TII->get(TargetOpcode::COPY), RegA);  in processTiedPairs()
1500       if (TargetRegisterInfo::isVirtualRegister(RegA)) {  in processTiedPairs()
1501         assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),  in processTiedPairs()
1508         assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))  in processTiedPairs()
1522       if (TargetRegisterInfo::isVirtualRegister(RegA)) {  in processTiedPairs()
1523         LiveInterval &LI = LIS->getInterval(RegA);  in processTiedPairs()
1542     if (TargetRegisterInfo::isVirtualRegister(RegA) &&  in processTiedPairs()
1544       MRI->constrainRegClass(RegA, RC);  in processTiedPairs()
1545     MO.setReg(RegA);  in processTiedPairs()
1552     SrcRegMap[RegA] = RegB;  in processTiedPairs()