Lines Matching full:addend
34 /// Extract the addend encoded in the instruction / memory location.
39 int64_t Addend = 0; in decodeAddend() local
64 Addend = *reinterpret_cast<support::ulittle32_t *>(LocalAddress); in decodeAddend()
66 Addend = *reinterpret_cast<support::ulittle64_t *>(LocalAddress); in decodeAddend()
73 // Get the 26 bit addend encoded in the branch instruction and sign-extend in decodeAddend()
76 Addend = (*p & 0x03FFFFFF) << 2; in decodeAddend()
77 Addend = SignExtend64(Addend, 28); in decodeAddend()
86 // Get the 21 bit addend encoded in the adrp instruction and sign-extend in decodeAddend()
89 Addend = ((*p & 0x60000000) >> 29) | ((*p & 0x01FFFFE0) >> 3) << 12; in decodeAddend()
90 Addend = SignExtend64(Addend, 33); in decodeAddend()
109 // Get the 12 bit addend encoded in the instruction. in decodeAddend()
110 Addend = (*p & 0x003FFC00) >> 10; in decodeAddend()
125 Addend <<= ImplicitShift; in decodeAddend()
129 return Addend; in decodeAddend()
132 /// Extract the addend encoded in the instruction.
134 MachO::RelocationInfoType RelType, int64_t Addend) const { in encodeAddend() argument
159 *reinterpret_cast<support::ulittle32_t *>(LocalAddress) = Addend; in encodeAddend()
161 *reinterpret_cast<support::ulittle64_t *>(LocalAddress) = Addend; in encodeAddend()
168 // Verify addend value. in encodeAddend()
169 assert((Addend & 0x3) == 0 && "Branch target is not aligned"); in encodeAddend()
170 assert(isInt<28>(Addend) && "Branch target is out of range."); in encodeAddend()
172 // Encode the addend as 26 bit immediate in the branch instruction. in encodeAddend()
173 *p = (*p & 0xFC000000) | ((uint32_t)(Addend >> 2) & 0x03FFFFFF); in encodeAddend()
182 // Check that the addend fits into 21 bits (+ 12 lower bits). in encodeAddend()
183 assert((Addend & 0xFFF) == 0 && "ADRP target is not page aligned."); in encodeAddend()
184 assert(isInt<33>(Addend) && "Invalid page reloc value."); in encodeAddend()
186 // Encode the addend into the instruction. in encodeAddend()
187 uint32_t ImmLoValue = ((uint64_t)Addend << 17) & 0x60000000; in encodeAddend()
188 uint32_t ImmHiValue = ((uint64_t)Addend >> 9) & 0x00FFFFE0; in encodeAddend()
219 assert(((Addend & 0xF) == 0) && in encodeAddend()
224 assert(((Addend & 0x1) == 0) && "16-bit LDR/STR not 2-byte aligned."); in encodeAddend()
227 assert(((Addend & 0x3) == 0) && "32-bit LDR/STR not 4-byte aligned."); in encodeAddend()
230 assert(((Addend & 0x7) == 0) && "64-bit LDR/STR not 8-byte aligned."); in encodeAddend()
235 Addend >>= ImplicitShift; in encodeAddend()
236 assert(isUInt<12>(Addend) && "Addend cannot be encoded."); in encodeAddend()
238 // Encode the addend into the instruction. in encodeAddend()
239 *p = (*p & 0xFFC003FF) | ((uint32_t)(Addend << 10) & 0x003FFC00); in encodeAddend()
260 // addend for the following relocation. If found: (1) store the associated in processRelocationRef()
261 // addend, (2) consume the next relocation, and (3) use the stored addend to in processRelocationRef()
262 // override the addend. in processRelocationRef()
279 RE.Addend = decodeAddend(RE); in processRelocationRef()
281 assert((ExplicitAddend == 0 || RE.Addend == 0) && "Relocation has "\ in processRelocationRef()
282 "ARM64_RELOC_ADDEND and embedded addend in the instruction."); in processRelocationRef()
284 RE.Addend = ExplicitAddend; in processRelocationRef()
296 RE.Addend = Value.Offset; in processRelocationRef()
329 encodeAddend(LocalAddress, 1 << RE.Size, RelType, Value + RE.Addend); in resolveRelocation()
336 int64_t PCRelVal = Value - FinalAddress + RE.Addend; in resolveRelocation()
346 ((Value + RE.Addend) & (-4096)) - (FinalAddress & (-4096)); in resolveRelocation()
354 Value += RE.Addend; in resolveRelocation()
365 Value = SectionABase - SectionBBase + RE.Addend; in resolveRelocation()
440 int64_t Addend = in processSubtractRelocation() local
451 RelocationEntry R(SectionID, Offset, MachO::ARM64_RELOC_SUBTRACTOR, (uint64_t)Addend, in processSubtractRelocation()