188   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
189   unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2742   MVT DestVT;  in selectFPToInt()  local
2743   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())  in selectFPToInt()
2757       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;  in selectFPToInt()
2759       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;  in selectFPToInt()
2762       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;  in selectFPToInt()
2764       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;  in selectFPToInt()
2767       DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);  in selectFPToInt()
2775   MVT DestVT;  in selectIntToFP()  local
2776   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())  in selectIntToFP()
2779   if (DestVT == MVT::f16)  in selectIntToFP()
2782   assert((DestVT == MVT::f32 || DestVT == MVT::f64) &&  in selectIntToFP()
2804       Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;  in selectIntToFP()
2806       Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;  in selectIntToFP()
2809       Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;  in selectIntToFP()
2811       Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;  in selectIntToFP()
2814   unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,  in selectIntToFP()
2961       MVT DestVT = VA.getLocVT();  in processCallArgs()  local
2963       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);  in processCallArgs()
2971       MVT DestVT = VA.getLocVT();  in processCallArgs()  local
2973       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);  in processCallArgs()
3739     MVT DestVT = VA.getValVT();  in selectRet()  local
3741     if (RVVT != DestVT) {  in selectRet()
3749       SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);  in selectRet()
3782   MVT DestVT = DestEVT.getSimpleVT();  in selectTrunc()  local
3787   if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&  in selectTrunc()
3788       DestVT != MVT::i1)  in selectTrunc()
3804     switch (DestVT.SimpleTy) {  in selectTrunc()
3835 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {  in emiti1Ext()  argument
3836   assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||  in emiti1Ext()
3837           DestVT == MVT::i64) &&  in emiti1Ext()
3840   if (DestVT == MVT::i8 || DestVT == MVT::i16)  in emiti1Ext()
3841     DestVT = MVT::i32;  in emiti1Ext()
3846     if (DestVT == MVT::i64) {  in emiti1Ext()
3859     if (DestVT == MVT::i64) {  in emiti1Ext()
4244 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntExt()  argument
4246   assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");  in emitIntExt()
4252   if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&  in emitIntExt()
4253        (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||  in emitIntExt()
4265     return emiti1Ext(SrcReg, DestVT, IsZExt);  in emitIntExt()
4267     if (DestVT == MVT::i64)  in emitIntExt()
4274     if (DestVT == MVT::i64)  in emitIntExt()
4281     assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");  in emitIntExt()
4288   if (DestVT == MVT::i8 || DestVT == MVT::i16)  in emitIntExt()
4289     DestVT = MVT::i32;  in emitIntExt()
4290   else if (DestVT == MVT::i64) {  in emitIntExt()
4301       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitIntExt()
4465   MVT DestVT = DestEVT.getSimpleVT();  in selectRem()  local
4466   if (DestVT != MVT::i64 && DestVT != MVT::i32)  in selectRem()
4470   bool Is64bit = (DestVT == MVT::i64);  in selectRem()
4493       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in selectRem()