874   RegPairInfo() : Reg1(AArch64::NoRegister), Reg2(AArch64::NoRegister) {}  in RegPairInfo()
875   unsigned Reg1;  member
905     RPI.Reg1 = CSI[i].getReg();  in computeCalleeSaveRegisterPairs()
907     assert(AArch64::GPR64RegClass.contains(RPI.Reg1) ||  in computeCalleeSaveRegisterPairs()
908            AArch64::FPR64RegClass.contains(RPI.Reg1));  in computeCalleeSaveRegisterPairs()
909     RPI.IsGPR = AArch64::GPR64RegClass.contains(RPI.Reg1);  in computeCalleeSaveRegisterPairs()
934              ((RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) ||  in computeCalleeSaveRegisterPairs()
935               RPI.Reg1 + 1 == RPI.Reg2))) &&  in computeCalleeSaveRegisterPairs()
974     unsigned Reg1 = RPI.Reg1;  in spillCalleeSavedRegisters()  local
992     DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1);  in spillCalleeSavedRegisters()
1001     MBB.addLiveIn(Reg1);  in spillCalleeSavedRegisters()
1009     MIB.addReg(Reg1, getPrologueDeath(MF, Reg1))  in spillCalleeSavedRegisters()
1037     unsigned Reg1 = RPI.Reg1;  in restoreCalleeSavedRegisters()  local
1053     DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1);  in restoreCalleeSavedRegisters()
1068     MIB.addReg(Reg1, getDefRegState(true))  in restoreCalleeSavedRegisters()