Lines Matching refs:Vt
8220 : I<oops, iops, asm, "\t$Vt, [$Rn]", "", pattern> {
8221 bits<5> Vt;
8231 let Inst{4-0} = Vt;
8236 : I<oops, iops, asm, "\t$Vt, [$Rn], $Xm", "$Rn = $wback", []> {
8237 bits<5> Vt;
8249 let Inst{4-0} = Vt;
8257 // "ld1\t$Vt, [$Rn], #16"
8259 // (LD1Twov8b_POST VecListTwo8b:$Vt, GPR64sp:$Rn, XZR)
8260 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
8263 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8267 // "ld1.8b\t$Vt, [$Rn], #16"
8269 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, XZR)
8270 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
8273 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8277 // "ld1\t$Vt, [$Rn]"
8279 // (LD1Twov8b VecListTwo64:$Vt, GPR64sp:$Rn)
8280 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
8282 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8286 // "ld1\t$Vt, [$Rn], $Xm"
8288 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, GPR64pi8:$Xm)
8289 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
8292 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8300 (outs !cast<RegisterOperand>(veclist # "16b"):$Vt),
8303 (outs !cast<RegisterOperand>(veclist # "8h"):$Vt),
8306 (outs !cast<RegisterOperand>(veclist # "4s"):$Vt),
8309 (outs !cast<RegisterOperand>(veclist # "2d"):$Vt),
8312 (outs !cast<RegisterOperand>(veclist # "8b"):$Vt),
8315 (outs !cast<RegisterOperand>(veclist # "4h"):$Vt),
8318 (outs !cast<RegisterOperand>(veclist # "2s"):$Vt),
8324 !cast<RegisterOperand>(veclist # "16b"):$Vt),
8329 !cast<RegisterOperand>(veclist # "8h"):$Vt),
8334 !cast<RegisterOperand>(veclist # "4s"):$Vt),
8339 !cast<RegisterOperand>(veclist # "2d"):$Vt),
8344 !cast<RegisterOperand>(veclist # "8b"):$Vt),
8349 !cast<RegisterOperand>(veclist # "4h"):$Vt),
8354 !cast<RegisterOperand>(veclist # "2s"):$Vt),
8373 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
8376 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
8379 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
8382 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
8385 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
8388 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
8391 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
8396 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
8401 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
8406 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
8411 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
8416 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
8421 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
8426 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
8447 (outs !cast<RegisterOperand>(veclist # "1d"):$Vt),
8452 !cast<RegisterOperand>(veclist # "1d"):$Vt),
8467 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
8472 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
8526 bits<5> Vt;
8534 let Inst{4-0} = Vt;
8540 : I<oops, iops, asm, operands, "$Vt = $dst," # cst, pattern> {
8541 bits<5> Vt;
8549 let Inst{4-0} = Vt;
8556 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn]", "",
8557 (outs listtype:$Vt), (ins GPR64sp:$Rn),
8568 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn], $Xm",
8570 (outs GPR64sp:$wback, listtype:$Vt),
8583 // "ld1r.8b\t$Vt, [$Rn], #1"
8585 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
8586 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
8589 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8593 // "ld1r.8b\t$Vt, [$Rn], #1"
8595 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8596 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
8599 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8603 // "ld1r.8b\t$Vt, [$Rn]"
8605 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8606 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
8608 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8612 // "ld1r.8b\t$Vt, [$Rn], $Xm"
8614 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8615 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
8618 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8678 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8690 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8702 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8715 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8729 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8742 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8756 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8770 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8784 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8796 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8808 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8821 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8834 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8846 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8858 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8871 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8889 (ins listtype:$Vt, VectorIndexB:$idx,
8894 (ins listtype:$Vt, VectorIndexB:$idx,
8903 (ins listtype:$Vt, VectorIndexH:$idx,
8908 (ins listtype:$Vt, VectorIndexH:$idx,
8917 (ins listtype:$Vt, VectorIndexS:$idx,
8922 (ins listtype:$Vt, VectorIndexS:$idx,
8930 (ins listtype:$Vt, VectorIndexD:$idx,
8935 (ins listtype:$Vt, VectorIndexD:$idx,
8942 (outs), (ins listtype:$Vt, VectorIndexB:$idx,
8947 (ins listtype:$Vt, VectorIndexB:$idx,
8954 (outs), (ins listtype:$Vt, VectorIndexH:$idx,
8959 (ins listtype:$Vt, VectorIndexH:$idx,
8966 (outs), (ins listtype:$Vt, VectorIndexS:$idx,
8971 (ins listtype:$Vt, VectorIndexS:$idx,
8978 (outs), (ins listtype:$Vt, VectorIndexD:$idx,
8983 (ins listtype:$Vt, VectorIndexD:$idx,
8990 // "ld1\t$Vt, [$Rn], #1"
8992 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
8993 def : InstAlias<asm # "\t$Vt$idx, [$Rn], #" # Offset,
8996 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
9000 // "ld1.8b\t$Vt, [$Rn], #1"
9002 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
9003 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], #" # Offset,
9006 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
9010 // "ld1.8b\t$Vt, [$Rn]"
9012 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
9013 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn]",
9015 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
9019 // "ld1.8b\t$Vt, [$Rn], $Xm"
9021 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
9022 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], $Xm",
9025 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,