Lines Matching refs:b01
1020 let Inst{20-19} = 0b01;
1035 let Inst{20-19} = 0b01;
2402 let Inst{25-24} = 0b01;
3163 let Inst{11-10} = 0b01;
3595 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
3601 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
3646 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
3655 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
3717 let Inst{23-22} = 0b01; // 64-bit FPR flag
3733 let Inst{23-22} = 0b01; // 64-bit FPR flag
3761 let Inst{23-22} = 0b01; // 64-bit FPR flag
3787 let Inst{23-22} = 0b01; // 64-bit FPR flag
3879 let Inst{23-22} = 0b01; // 64-bit FPR flag
3901 let Inst{23-22} = 0b01; // 64-bit FPR flag
3904 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
3910 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
3938 def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm,
3942 def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm,
3946 def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm,
3954 def DSr : BaseFPConversion<0b00, 0b01, FPR64, FPR32, asm,
3994 let Inst{23-22} = 0b01; // 64-bit size flag
4038 let Inst{23-22} = 0b01; // 64-bit size flag
4056 let Inst{23-22} = 0b01; // 64-bit size flag
4101 let Inst{23-22} = 0b01; // 64-bit size flag
4171 let Inst{23-22} = 0b01;
4176 let Inst{23-22} = 0b01;
4203 let Inst{11-10} = 0b01;
4225 let Inst{23-22} = 0b01;
4266 let Inst{23-22} = 0b01;
4299 let Inst{23-22} = 0b01;
4460 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
4463 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
4482 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
4485 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
4505 def v2f32 : BaseSIMDThreeSameVectorTied<0, U, {S,0b01}, {0b11,opc}, V64,
4509 def v4f32 : BaseSIMDThreeSameVectorTied<1, U, {S,0b01}, {0b11,opc}, V128,
4663 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64,
4666 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
4701 def v4i16 : BaseSIMDVectorLShiftLongBySize<0, 0b01, V64,
4703 def v8i16 : BaseSIMDVectorLShiftLongBySize<1, 0b01, V128,
4721 def v4i16_v2i32 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64,
4724 def v8i16_v4i32 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
4745 def v4i16_v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, 0b00, V64,
4749 def v8i16_v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, 0b00, V128,
4772 def v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, 0b00, V64,
4775 def v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, 0b00, V128,
4797 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64,
4800 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
4836 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64,
4839 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
4973 def v4i16 : BaseSIMDMixedTwoVector<0, U, 0b01, opc, V128, V64,
4976 def v8i16 : BaseSIMDMixedTwoVectorTied<1, U, 0b01, opc, V128, V128,
5029 def v4i16rz : BaseSIMDCmpTwoVector<0, U, 0b01, 0b00, opc, V64,
5032 def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, 0b00, opc, V128,
5645 let Inst{31-30} = 0b01;
5665 let Inst{31-30} = 0b01;
5709 def v1i16: BaseSIMDThreeScalarTied<U, 0b01, R, opc, (outs FPR16:$dst),
5719 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
5736 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
5756 let Inst{31-30} = 0b01;
5771 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5783 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5808 let Inst{31-30} = 0b01;
5830 let Inst{31-30} = 0b01;
5850 let Inst{31-30} = 0b01;
5941 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR16, asm, []>;
5956 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
5971 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR32, asm, []>;
5988 let Inst{31-30} = 0b01;
6046 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR16, V64,
6048 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR16, V128,
6059 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR32, V64,
6061 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR32, V128,
6407 def v8i8Two : BaseSIMDTableLookup<0, 0b01, op, V64, VecListTwo16b,
6415 def v16i8Two : BaseSIMDTableLookup<1, 0b01, op, V128, VecListTwo16b,
6451 def v8i8Two : BaseSIMDTableLookupTied<0, 0b01, op, V64, VecListTwo16b,
6459 def v16i8Two : BaseSIMDTableLookupTied<1, 0b01, op, V128, VecListTwo16b,
7023 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc, V64, V64,
7035 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
7072 def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
7096 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
7109 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
7149 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc, V64, V64,
7161 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
7201 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
7214 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
7254 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
7274 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
7304 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
7352 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
7381 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
7394 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
7439 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
7452 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
7509 let Inst{31-30} = 0b01;
7529 let Inst{31-30} = 0b01;
8302 def v8h : BaseSIMDLdSt<1, 1, opcode, 0b01, asm,
8314 def v4h : BaseSIMDLdSt<0, 1, opcode, 0b01, asm,
8327 def v8h_POST : BaseSIMDLdStPost<1, 1, opcode, 0b01, asm,
8347 def v4h_POST : BaseSIMDLdStPost<0, 1, opcode, 0b01, asm,
8375 def v8h : BaseSIMDLdSt<1, 0, opcode, 0b01, asm, (outs),
8387 def v4h : BaseSIMDLdSt<0, 0, opcode, 0b01, asm, (outs),
8399 def v8h_POST : BaseSIMDLdStPost<1, 0, opcode, 0b01, asm,
8419 def v4h_POST : BaseSIMDLdStPost<0, 0, opcode, 0b01, asm,
8628 def v4h : BaseSIMDLdR<0, R, opcode, S, 0b01, asm,
8630 def v8h : BaseSIMDLdR<1, R, opcode, S, 0b01, asm,
8647 def v4h_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b01, asm,
8650 def v8h_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b01, asm,
9073 def v4i16 : BaseSIMDThreeSameVectorTiedR0<0, U, 0b01, opc, V64, asm, ".4h",
9078 def v8i16 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b01, opc, V128, asm, ".8h",
9097 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
9112 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
9200 def i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
9384 let Sz = 0b01, Acq = Acq, Rel = Rel in def h : BaseCAS<order, "h", GPR32>;
9400 let Sz = 0b01, Acq = Acq, Rel = Rel in
9431 let Sz = 0b01, Acq = Acq, Rel = Rel in def h : BaseSWP<order, "h", GPR32>;
9465 let Sz = 0b01, Acq = Acq, Rel = Rel, opc = opc in